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# Date Author Comment
97a8ea5a 03/12/2013 11:35 am Andreas Färber

cpu: Replace do_interrupt() by CPUClass::do_interrupt method

This removes a global per-target function and thus takes us one step
closer to compiling multiple targets into one executable.

It will also allow to override the interrupt handling for certain CPU...
c05efcb1 02/16/2013 03:51 pm Andreas Färber

cpu: Add CPUArchState pointer to CPUState

The target-specific ENV_GET_CPU() macros have allowed us to navigate
from CPUArchState to CPUState. The reverse direction was not supported.
Avoid introducing CPU_GET_ENV() macros by initializing an untyped
pointer that is initialized in derived instance_init functions....
25733ead 02/16/2013 03:50 pm Andreas Färber

target-xtensa: Move TCG initialization to XtensaCPU initfn

Combine this with breakpoint handler registration, guarding both with
tcg_enabled() to suppress also TCG init for qtest. Rename the handler to
xtensa_breakpoint_handler() since it needs to become global....
5f6c9643 02/16/2013 03:50 pm Andreas Färber

target-xtensa: Introduce QOM realizefn for XtensaCPU

Introduce realizefn and set realized = true in cpu_xtensa_init().

Signed-off-by: Andreas Färber <>
004a5690 02/01/2013 02:35 am Andreas Färber

target-xtensa: Mark as unmigratable

There was no CPU_SAVE_VERSION defined, so neither "cpu_common" VMState
nor cpu_{save,load}() were registered. Their implementation was no-op.
Therefore there is no backwards compatibility to keep, so mark XtensaCPU
as unmigratable at device level....
fcc803d1 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement ATOMCTL SR

ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
4e41d2f5 12/08/2012 08:48 pm Max Filippov

target-xtensa: implement CACHEATTR SR

In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details....
15be3171 06/05/2012 12:00 am Andreas Färber

target-xtensa: Let cpu_xtensa_init() return XtensaCPU

Make the include paths for cpu-qom.h consistent to allow using XtensaCPU
in cpu.h.

Turn cpu_init macro into a static inline function returning
CPUXtensaState for backwards compatibility.

Signed-off-by: Andreas Färber <>...
a4633e16 04/14/2012 02:48 am Andreas Färber

target-xtensa: QOM'ify CPU

Embed CPUXtensaState as first member of XtensaCPU.
Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <>
Signed-off-by: Max Filippov <>
5087a72c 04/14/2012 02:48 am Andreas Färber

target-xtensa: QOM'ify CPU reset

Move code from cpu_state_reset() into QOM xtensa_cpu_reset().
To avoid moving reset_mmu() and dependencies, make it non-static.

Signed-off-by: Andreas Färber <>
Signed-off-by: Max Filippov <>
e554bbc6 04/14/2012 02:48 am Andreas Färber

target-xtensa: Start QOM'ifying CPU init

Move XtensaConfig-independent code from cpu_xtensa_init() into a
QOM initfn, as a start.

Signed-off-by: Andreas Färber <>
Signed-off-by: Max Filippov <>