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Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-xtensa: drop usage of prev_debug_excp_handler
Chains of exception handlers are currently unused feature. Dropping itto be consistent with target-i386 but it may simplify qom-ifying CPUin future like for target-i386.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
target-xtensa: update EXCVADDR in case of page table lookup
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, evenif the miss is handled entirely by processor hardware.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: update autorefill TLB entries conditionally
This is to avoid interference of internal QEMU helpers(cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visibleTLB state.
target-xtensa: control page table lookup explicitly
Hardware pagetable walking may not be nested. Stop guessing and passexplicit flag to the get_physical_addr_mmu function that controls pagetable lookup.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-xtensa: Let cpu_xtensa_init() return XtensaCPU
Make the include paths for cpu-qom.h consistent to allow using XtensaCPUin cpu.h.
Turn cpu_init macro into a static inline function returningCPUXtensaState for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-xtensa: QOM'ify CPU
Embed CPUXtensaState as first member of XtensaCPU.Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU reset
Move code from cpu_state_reset() into QOM xtensa_cpu_reset().To avoid moving reset_mmu() and dependencies, make it non-static.
target-xtensa: Start QOM'ifying CPU init
Move XtensaConfig-independent code from cpu_xtensa_init() into aQOM initfn, as a start.
target-xtensa: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
target-xtensa: Clean includes
Remove some include statements which are not needed.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-xtensa: add DBREAK data breakpoints
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debugwatchpoints.
This implementation is not fully compliant to ISA: when a breakpoint isset to an unmapped/inaccessible memory address it generates TLB/memory...
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK andBREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
target-xtensa: implement info tlb monitor command
Command dumps valid ITLB and DTLB entries.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: fix MMUv3 initialization
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;- ITLB/DTLB way 6 attr field is set to 3 on reset.
target-xtensa: extract core configuration from overlay
Introduce overlay_tool.h that defines core configuration blocks fromdata available in the linux architecture variant overlay.
Overlay data is automatically generated in the core configurationprocess by Tensilica tools and can be directly converted to qemu xtensa...
target-xtensa: remove hand-written xtensa cores implementations
target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values thatcorrespond to default VECBASE value.
target-xtensa: add gdb support
Specific xtensa processor overlay for GDB contains register map inthe gdb/xtensa-config.c. This description is used by the GDB to e.g.parse 'g' response packets and it may be reused in the qemu's gdbstub(only XTREG definitions for non-pseudoregisters are needed)....
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
target-xtensa: add dc232b core and board
This is Diamond 232L Standard Core Rev.B (LE).
target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields inCPUEnv. Only current window is accessible to TCG. On operations thatchange window base helpers copy current window to and from physical...
target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
target-xtensa: implement unaligned exception option
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generatedin case this option is not enabled.
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: add PS register and access control
target-xtensa: implement exceptions
- mark privileged opcodes with ring check;- make debug exception on exception handler entry.
target-xtensa: add target stubs
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.