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# Date Author Comment
2bece2c8 06/16/2010 12:29 pm Richard Henderson

tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.

Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments. Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be...

d9f4bb27 10/04/2009 03:09 pm Andre Przywara

target-i386: add SSE4a instruction support

This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register)....

8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>

fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...

a7812ae4 11/17/2008 04:43 pm pbrook

TCG variable type checking.

Signed-off-by: Paul Brook <>

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

222a3336 10/04/2008 06:27 am balrog

Implement SSE4.1, SSE4.2 (x86).

extensions. Most instructions haven't been tested yet.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

4242b1bd 09/25/2008 09:01 pm balrog

Implement x86 SSSE3 instructions.

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

437a88a5 05/22/2008 07:11 pm bellard

proper helper definition registering (all targets must do that)

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

b8b6a50b 05/15/2008 07:46 pm bellard

converted more helpers to TCG - fixed some SVM issues

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162

5af45186 05/12/2008 07:47 pm bellard

converted SSE/MMX ops to TCG

git-svn-id: svn:// c046a42c-6fe2-441c-8c8c-71466251a162