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target-mips: clean-up in BIT_INSV
This is a small follow-up change to "fix incorrect behaviour for INSV".
It includes two minor modifications:
- sizefilter is constant so it can be moved inside of the block,- several lines of the code are replaced with a call to deposit64....
target-mips: set carry bit correctly in DSPControl register
First we need to clear the bit and then we set the given value.Instruction ADDSC sets the bit and instruction ADDWC uses this bit.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: fix EXTPDP and setting up pos field in the DSPControl reg
This change makes sure that modifications of pos field in the DSPControlregister do not trash other bits in the register. This bug can be triggeredwith the additional test case in mips32-dsp/extpdp.c in this commit....
target-mips: fix incorrect behaviour for EXTP
The mask for EXTP instruction when size=31 has not been correctlycalculated.
The test (mips32-dsp/extp.c) has been extended to include the case thattriggers the issue.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>...
target-mips: fix incorrect behaviour for INSV
Corner case for INSV instruction when size=32 has not been correctlyimplemented. The mask for size should be one bit wider, and preparing thefilter variable should be aware of this case too.
The test for INSV has been extended to include the case that triggers the...
target-mips: fix calculation of overflow for SHLL.PH and SHLL.QB
This change corrects and simplifies how discard is calculated for shiftleft logical vector instructions. It is used to detect overflow and set bit22 in the DSPControl register.
The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases...
target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHR
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format.Otherwise, the results are unpredictable. Once the operands were correctedin the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became...
target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
Fix for rndrashift_short_acc to set correct value to higher 64 bits.This change also corrects conditions when bit 23 of the DSPControl registeris set.
The existing test files have been extended with several examples that...
mips-linux-user: Save and restore fpu and dsp from sigcontext
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: fix DSP overflow macro and affected routines
The previous implementation incorrectly used same macro to detect overflowfor addition and subtraction. This patch makes distinction between thesetwo, and creates separate macros. The affected routines are changed...
target-mips: fix for sign-issue in MULQ_W helper
Correct sign-propagation before multiplication in MULQ_W helper.The change also fixes previously incorrect expected values in thetests for MULQ_RS.W and MULQ_S.W.
Signed-off-by: Petar Jovanovic <petarj@mips.com>...
target-mips: fix for incorrect multiplication with MULQ_S.PH
The change corrects sign-related issue with MULQ_S.PH. It also includesextension to the already existing test which will trigger the issue.
Signed-off-by: Petar Jovanovic <petarj@mips.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: implement DSP (d)append sub-class with TCG
DSP instruction from the (d)append sub-class can be implemented withTCG. Use a different function for these instructions are they are quitedifferent from compare-pick sub-class.
Fix BALIGN instruction for negative value, where the value should be...
target-mips: use DSP unions for reduction add instructions
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: use DSP unions for unary DSP operators
This allow to reduce the number of macros.
target-mips: use DSP unions for binary DSP operators
target-mips: add unions to access DSP elements
Instead of playing with bit shifting, add two unions (one for 32-bitvalues, one for 64-bit ones) to access all the DSP elements with thecorrect type.
This make the code easier to read and less error prone, and allow GCC...
target-mips: Fix helper and tests for dot/cross-dot product instructions
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectlydefines halfword vector elements as unsigned values. This results in wrongoutput which is not triggered in the tests as they also follow this logic....
Fix my email address
Fix my email address, last time it's wrong.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix for helpers for EXTR_* instructions
The change removes some unnecessary and incorrect code for EXTR_S.H.Further, it corrects the mask for shift value in the EXTR_ instructions. It alsoextends the existing tests so they trigger the issues corrected with the change....
target-mips: Fix incorrect reads and writes to DSPControl register
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used inthe MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32these bits must be written as zero, and return zero on read....
target-mips: Fix incorrect shift for SHILO and SHILOV
helper_shilo has not been shifting an accumulator value correctly for negativevalues in 'shift' field. Minor optimization for shift=0 case.This change also adds tests that will trigger issue and check for regressions....
target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask.This change contains both fix for the instruction and to the existing test.
Signed-off-by: Petar Jovanovic <petarj@mips.com>Reviewed-by: Eric Johnson <ericj@mips.com>...
target-mips: use ULL for 64 bit constants
Fix build on a 32 bit host: CC mips-softmmu/target-mips/dsp_helper.o/src/qemu/target-mips/dsp_helper.c: In function 'helper_dextr_rs_w':/src/qemu/target-mips/dsp_helper.c:3556: error: integer constant is too large for 'long' type...
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.
target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.
target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.
target-mips: Add ASE DSP internal functions
Add internal functions using by MIPS ASE DSP instructions.