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Makefile.objs 938 Bytes
e500-ccsr.h 337 Bytes
e500.c 23.1 kB
e500.h 526 Bytes
e500plat.c 1.8 kB
mpc8544ds.c 1.7 kB

Latest revisions

# Date Author Comment
5bac0701 12/14/2012 02:12 pm Alexander Graf

openpic: remove irq_out

The current openpic emulation contains half-ready code for bypass mode.
Remove it, so that when someone wants to finish it they can start from a
clean state.

Signed-off-by: Alexander Graf <>
d0b72631 12/14/2012 02:12 pm Alexander Graf

openpic: convert to qdev

This patch converts the OpenPIC device to qdev. Along the way it
renames the "openpic" target to "raven" and the "mpic" target to
"fsl_mpic_20", to better reflect the actual models they implement.

This way we have a generic OpenPIC device now that can handle...
a911b7a9 12/14/2012 02:12 pm Alexander Graf

PPC: e500: Add MSI support

Now that our interrupt controller supports MSIs, let's expose that feature
to the guest through the device tree!

Signed-off-by: Alexander Graf <>
cdbb912a 12/14/2012 02:12 pm Alexander Graf

mpic: Unify numbering scheme

MPIC interrupt numbers in Linux (device tree) and in QEMU are different,
because QEMU takes the sparseness of the IRQ number space into account.

Remove that cleverness and instead assume a flat number space. This makes
the code easier to understand, because we are actually aligned with Linux...
639e8102 12/14/2012 02:12 pm David Gibson

pseries: Implement PAPR NVRAM

The PAPR specification requires a certain amount of NVRAM, accessed via
RTAS, which we don't currently implement in qemu. This patch addresses
this deficiency, implementing the NVRAM as a VIO device, with some glue to
instantiate it automatically based on a machine option....
dffb1dc2 12/14/2012 02:12 pm Bharat Bhushan

e500: Adding CCSR memory region

All devices are also placed under CCSR memory region.
The CCSR memory region is exported to pci device. The MSI interrupt
generation is the main reason to export the CCSR region to PCI device.
This put the requirement to move mpic under CCSR region, but logically...
3eddc1be 12/14/2012 02:12 pm Bharat Bhushan

Adding BAR0 for e500 PCI controller

PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)...
a1bc20df 10/29/2012 12:45 pm Alexander Graf

PPC: e500: Map PIO space into core memory region

On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is
accessible via MMIO. Do this mapping explicitly by mapping the PIO space
of our PCI bus into a memory region that lives in memory space....
59de4f98 10/29/2012 12:45 pm Bharat Bhushan

e500: Fix serial initialization

it was wrongly using serial_hds0 instead of serial_hds1

Signed-off-by: Bharat Bhushan <>
Reviewed-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
74d042e5 10/29/2012 12:45 pm David Gibson

pseries: Implement qemu initiated shutdowns using EPOW events

At present, using 'system_powerdown' from the monitor or otherwise
instructing qemu to (cleanly) shut down a pseries guest will not work,
because we did not have a method of signalling the shutdown request to the...

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