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Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bitposition. Because of this, the SPE evcmp* family of instructions wouldstore values in the result condition register that were also off by onebit position....
PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t topass it along the stacks.
This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, makingit compile without --disable-werror
Signed-off-by: Alexander Graf <agraf@suse.de>...
PPC64: Fix alternate timebase
Fix the alternate time base the same way as the default timebase. SPR_ATBLshould return a 64-bit value on 64 bit implementations.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed usingtwo separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.
On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full64 bits as return value. If we only take the lower ones, fine. But Linux...
PPC: rename cpu_ppc_reset to cpu_reset for consistency
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: move often used CPU fields at the top of the structure
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Replace REGX with PRIx64
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: add cpu_set_tls
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: malc <av1474@comtv.ru>
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: add exceptions for conditional stores
target-ppc: fix cpu_clone_regs
We only need to make sure that the clone syscall looks like itsucceeded, not clobber 60% of the register set.
Update to a hopefully more future proof FSF address
Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).Build these files into a convenience library, and use that instead ofbuilding for every target.
Remove and poison various target specific macros to avoid bogus target...
target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on thecapabilities of the CPU we're emulating.
Fix PPC reset
Make the ELF loader aware of backwards compatibility
Most 64 bit architectures I'm aware of support running 32 bit codeof the same architecture as well.
So x86_64 can run i386 code easily and ppc64 can run ppc code.
Unfortunately, the current checks are pretty strict. So you can only...
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.This breaks bridge mode for 970 for now, but at least keeps us fromoverwriting physical addresses 0x0 - 0x300, rendering our interrupthandlers useless.
I put in a stub for bridge mode operation that could be enabled...
Implement large pages
The current SLB/PTE code does not support large pages, which arerequired by Linux, as it boots up with the kernel regions up as large.
This patch implements large page support, so we can run Linux.
Signed-off-by: Alexander Graf <alex@csgraf.de>...
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu <yu.liu@freescale.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
Load 32 bit ELF BIOS images also on PPC64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6554 c046a42c-6fe2-441c-8c8c-71466251a162
Rename spe_status to vec_status
Only one of Altivec and SPE will be available on a given chip.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
Add f field to ppc_avr_t
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6505 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Add vscr access macros.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6158 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix type of spe_acc.
ACC is a 64-bit register and needs to be specified as such regardless ofthe target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6090 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add signed fields to ppc_avr_t.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6042 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove remaining warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPR accesses to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove dead code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SLB/TLB instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
Common cpu_loop_exit prototype
All archs use the same cpu_loop_exit, so move the prototype in a commonheader. i386 was carrying a __hidden attribute, but that was empty forthis arch anyway.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: convert POWER2 load/store instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPE load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert altivec load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert fp ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associatedwith a TB. The basic motivation is to move more arch specific code outof generic files. Specifically the long #ifdef clutter in tb_find_fast()...
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert most SPE integer instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix tcg fatal error on i386 host
It looks like the i386 runs out of registers for allocation dueto too many global registers allocated by the ppc target.
Here is a quick and dirty fix that seems to solve the problem.This should be considered as temporary....
target-ppc: xer access prototypes no more used & implemented
Revision 5500 of the qemu repository removed all code usingppc_load_xer & ppc_store_xer as well as their implementation.
Another patch fixes it's usage in kvm-userspace for powerpc, but I think...
target-ppc: convert crf related instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually toavoid defining 5 32-bit registers (TCG doesn't permit to map 8-bitregisters).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: Convert CRF moves to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: cleanup register types
- use target_ulong for gpr and dyngen registers- remove ppc_gpr_t type- define 64-bit dyngen registers for GPE register on 32-bit targets
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
ppc: Convert GPR moves to TCG
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.Introduce TCG variables cpu_gpr[0..31].
For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers...
Move interrupt_request and user_mode_only to common cpu state.Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
PPC: fix definition of msr_spe
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4361 c046a42c-6fe2-441c-8c8c-71466251a162
Cleanup: remove useless TARGET_GPR_BITS definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3799 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC 74xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3798 c046a42c-6fe2-441c-8c8c-71466251a162
Fix incorrect debug prints (reported by Paul Brook).Remove obsolete / duplicated debug prints and improve output consistency.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
Revert foolish patch.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3724 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ppc32 register dumps on 64-bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3723 c046a42c-6fe2-441c-8c8c-71466251a162
Fix PowerPC 7xx definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3713 c046a42c-6fe2-441c-8c8c-71466251a162
Remove shared macro used to define PowerPC implementations instructions sets: tend more to propagate bugged definition than simplify the code.Check and fix PowerPC 6xx implementations definitions.Misc fixes in PowerPC CPU list.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3707 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 620 MMU do not have the same exact behavior as standard 64 bits PowerPC ones.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3706 c046a42c-6fe2-441c-8c8c-71466251a162
New PowerPC CPU flag to define the decrementer and time-base source clock.Use it to properly initialize the clock for the PreP target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3701 c046a42c-6fe2-441c-8c8c-71466251a162
Improve PowerPC instructions set dump.Remove meaningless define from cpu.hMisc cleanups.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3682 c046a42c-6fe2-441c-8c8c-71466251a162
Add definitions for Freescale PowerPC implementations, ie MPC5xx, MPC8xx, e200, e300, e500 and e600 cores.Make those CPUs and PowerPC 440 available for user-mode emulation, thus providing a way of testing their implementation specific instructions.
...
Define Freescale cores specific MMU model, exceptions and input bus. (but do not provide any actual implementation).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3680 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC hypervisor mode is not fundamentally available only for PowerPC 64.Remove TARGET_PPC64 dependency and add code provision to be able to define a fake 32 bits CPU with hypervisor feature support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3678 c046a42c-6fe2-441c-8c8c-71466251a162
Make the PowerPC MMU model, exception model and input bus model typedefed enums.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3660 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing definition for number of input pins for the PowerPC 970 bus.Use proper INPUT_NB definitions to allocate PowerPC input pins structure, fixing a buffer overflow in the 6xx bus case.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3659 c046a42c-6fe2-441c-8c8c-71466251a162
Always make all PowerPC exception definitions visible.Always make the hypervisor timers available.Remove all TARGET_PPC64H checks, keeping a few if (0) tests for casesthat cannot be properly handled with the current PowerPC CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3656 c046a42c-6fe2-441c-8c8c-71466251a162
Always make PowerPC hypervisor mode memory accesses and instructions available for full system emulation, then removing all #if TARGET_PPC64H from micro-ops and code translator.Add new macros to dramatically simplify memory access tables definitions in target-ppc/translate.c....
Fix PowerPC targets compilation on 32 bits hosts:now that the SPE extension is available for all targets, we always need to have some 64 bits temporary registers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3647 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC SPE extension fix: must always preserve GPR high bits when running in 32 bits mode.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
Allow use of SPE extension by all PowerPC targets, adding gprh registers to store GPR MSBs when GPRs are 32 bits.Remove not-needed-anymore ppcemb-linux-user target.Keep ppcemb-softmmu target, which provides 1kB pages support and 36 bits physical address space....
Allow selection of PowerPC CPU giving a PVR.Remove unused pvr_mask field from CPU definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3571 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC 601 need specific callbacks for its BATs setup.Implement PowerPC 601 HID0 register, needed for little-endian mode support.As a consequence, we need to merge hflags coming from MSR with other ones.Use little-endian mode from hflags instead of MSR during code translation....
Fix PowerPC FPSCR update and floating-point exception generation in most useful cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3458 c046a42c-6fe2-441c-8c8c-71466251a162
Add PowerPC power-management state check callback.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3441 c046a42c-6fe2-441c-8c8c-71466251a162
Gprof prooved the PowerPC emulation spent too much time in MSR load and storeroutines. Coming back to a raw MSR storage model then speed-up the emulation.Improve fast MSR updates (wrtee wrteei and mtriee cases).Share rfi family instructions helpers code to avoid bug in duplicated code....
Properly implement non-execute bit on PowerPC segments and PTEs.Fix page protection bits for PowerPC 64 MMU.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3395 c046a42c-6fe2-441c-8c8c-71466251a162
Merge PowerPC 620 input bus definitions with standard PowerPC 6xx.Avoid hardcoding PowerPC interrupts definitions to ease updates.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3393 c046a42c-6fe2-441c-8c8c-71466251a162
There is no need of a specific MMU model for PowerPC 601.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3392 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
Unify '-cpu ?' option.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
Remove synonymous in PowerPC MSR bits definitions.Fix MSR EP bit buggy definition.Remove unuseful MSR flags.Fix MSR bits and flags definitions for most supported PowerPC implementations.Add MSR definitions/flags constistency checks and optional dump....
Implement PowerPC Altivec load & stores, used by Apple firmware for memcpy.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3349 c046a42c-6fe2-441c-8c8c-71466251a162
PowerPC target coding style fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3348 c046a42c-6fe2-441c-8c8c-71466251a162
Reorganize the CPUPPCState structure to group features.Add #ifdef to avoid compiling not relevant resources:- MMU related stuff for user-mode only targets- PowerPC 64 only resources for PowerPC 32 targets- embedded PowerPC extensions for non-ppcemb targets....
Add MSR bits signification per PowerPC implementation flags (to be continued).As a side effect, single step and branch step are available again.Remove irrelevant MSR bits definitions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3342 c046a42c-6fe2-441c-8c8c-71466251a162