root / hw / intc / openpic.c @ ab8131af
History | View | Annotate | Download (45.4 kB)
1 | dbda808a | bellard | /*
|
---|---|---|---|
2 | dbda808a | bellard | * OpenPIC emulation
|
3 | 5fafdf24 | ths | *
|
4 | dbda808a | bellard | * Copyright (c) 2004 Jocelyn Mayer
|
5 | 704c7e5d | Alexander Graf | * 2011 Alexander Graf
|
6 | 5fafdf24 | ths | *
|
7 | dbda808a | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | dbda808a | bellard | * of this software and associated documentation files (the "Software"), to deal
|
9 | dbda808a | bellard | * in the Software without restriction, including without limitation the rights
|
10 | dbda808a | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | dbda808a | bellard | * copies of the Software, and to permit persons to whom the Software is
|
12 | dbda808a | bellard | * furnished to do so, subject to the following conditions:
|
13 | dbda808a | bellard | *
|
14 | dbda808a | bellard | * The above copyright notice and this permission notice shall be included in
|
15 | dbda808a | bellard | * all copies or substantial portions of the Software.
|
16 | dbda808a | bellard | *
|
17 | dbda808a | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | dbda808a | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | dbda808a | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | dbda808a | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | dbda808a | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | dbda808a | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | dbda808a | bellard | * THE SOFTWARE.
|
24 | dbda808a | bellard | */
|
25 | dbda808a | bellard | /*
|
26 | dbda808a | bellard | *
|
27 | dbda808a | bellard | * Based on OpenPic implementations:
|
28 | 67b55785 | blueswir1 | * - Intel GW80314 I/O companion chip developer's manual
|
29 | dbda808a | bellard | * - Motorola MPC8245 & MPC8540 user manuals.
|
30 | dbda808a | bellard | * - Motorola MCP750 (aka Raven) programmer manual.
|
31 | dbda808a | bellard | * - Motorola Harrier programmer manuel
|
32 | dbda808a | bellard | *
|
33 | dbda808a | bellard | * Serial interrupts, as implemented in Raven chipset are not supported yet.
|
34 | 5fafdf24 | ths | *
|
35 | dbda808a | bellard | */
|
36 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
37 | 83c9f4ca | Paolo Bonzini | #include "hw/ppc/mac.h" |
38 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci.h" |
39 | 0d09e41a | Paolo Bonzini | #include "hw/ppc/openpic.h" |
40 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
41 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/msi.h" |
42 | e69a17f6 | Scott Wood | #include "qemu/bitops.h" |
43 | 0d09e41a | Paolo Bonzini | #include "hw/ppc/ppc.h" |
44 | dbda808a | bellard | |
45 | 611493d9 | bellard | //#define DEBUG_OPENPIC
|
46 | dbda808a | bellard | |
47 | dbda808a | bellard | #ifdef DEBUG_OPENPIC
|
48 | 4c4f0e48 | Scott Wood | static const int debug_openpic = 1; |
49 | dbda808a | bellard | #else
|
50 | 4c4f0e48 | Scott Wood | static const int debug_openpic = 0; |
51 | dbda808a | bellard | #endif
|
52 | dbda808a | bellard | |
53 | 4c4f0e48 | Scott Wood | #define DPRINTF(fmt, ...) do { \ |
54 | 4c4f0e48 | Scott Wood | if (debug_openpic) { \
|
55 | 4c4f0e48 | Scott Wood | printf(fmt , ## __VA_ARGS__); \ |
56 | 4c4f0e48 | Scott Wood | } \ |
57 | 4c4f0e48 | Scott Wood | } while (0) |
58 | 4c4f0e48 | Scott Wood | |
59 | e0dfe5b1 | Scott Wood | #define MAX_CPU 32 |
60 | 732aa6ec | Alexander Graf | #define MAX_MSI 8 |
61 | dbda808a | bellard | #define VID 0x03 /* MPIC version ID */ |
62 | dbda808a | bellard | |
63 | d0b72631 | Alexander Graf | /* OpenPIC capability flags */
|
64 | be7c236f | Scott Wood | #define OPENPIC_FLAG_IDR_CRIT (1 << 0) |
65 | e0dfe5b1 | Scott Wood | #define OPENPIC_FLAG_ILR (2 << 0) |
66 | dbda808a | bellard | |
67 | d0b72631 | Alexander Graf | /* OpenPIC address map */
|
68 | 780d16b7 | Alexander Graf | #define OPENPIC_GLB_REG_START 0x0 |
69 | 780d16b7 | Alexander Graf | #define OPENPIC_GLB_REG_SIZE 0x10F0 |
70 | 780d16b7 | Alexander Graf | #define OPENPIC_TMR_REG_START 0x10F0 |
71 | 780d16b7 | Alexander Graf | #define OPENPIC_TMR_REG_SIZE 0x220 |
72 | 732aa6ec | Alexander Graf | #define OPENPIC_MSI_REG_START 0x1600 |
73 | 732aa6ec | Alexander Graf | #define OPENPIC_MSI_REG_SIZE 0x200 |
74 | e0dfe5b1 | Scott Wood | #define OPENPIC_SUMMARY_REG_START 0x3800 |
75 | e0dfe5b1 | Scott Wood | #define OPENPIC_SUMMARY_REG_SIZE 0x800 |
76 | 780d16b7 | Alexander Graf | #define OPENPIC_SRC_REG_START 0x10000 |
77 | 8935a442 | Scott Wood | #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20) |
78 | 780d16b7 | Alexander Graf | #define OPENPIC_CPU_REG_START 0x20000 |
79 | 780d16b7 | Alexander Graf | #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000) |
80 | 780d16b7 | Alexander Graf | |
81 | d0b72631 | Alexander Graf | /* Raven */
|
82 | d0b72631 | Alexander Graf | #define RAVEN_MAX_CPU 2 |
83 | d0b72631 | Alexander Graf | #define RAVEN_MAX_EXT 48 |
84 | d0b72631 | Alexander Graf | #define RAVEN_MAX_IRQ 64 |
85 | 8935a442 | Scott Wood | #define RAVEN_MAX_TMR OPENPIC_MAX_TMR
|
86 | 8935a442 | Scott Wood | #define RAVEN_MAX_IPI OPENPIC_MAX_IPI
|
87 | d0b72631 | Alexander Graf | |
88 | d0b72631 | Alexander Graf | /* Interrupt definitions */
|
89 | d0b72631 | Alexander Graf | #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */ |
90 | d0b72631 | Alexander Graf | #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */ |
91 | d0b72631 | Alexander Graf | #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */ |
92 | d0b72631 | Alexander Graf | #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */ |
93 | d0b72631 | Alexander Graf | /* First doorbell IRQ */
|
94 | d0b72631 | Alexander Graf | #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
|
95 | d0b72631 | Alexander Graf | |
96 | e0dfe5b1 | Scott Wood | typedef struct FslMpicInfo { |
97 | e0dfe5b1 | Scott Wood | int max_ext;
|
98 | e0dfe5b1 | Scott Wood | } FslMpicInfo; |
99 | dbda808a | bellard | |
100 | e0dfe5b1 | Scott Wood | static FslMpicInfo fsl_mpic_20 = {
|
101 | e0dfe5b1 | Scott Wood | .max_ext = 12,
|
102 | e0dfe5b1 | Scott Wood | }; |
103 | b7169916 | aurel32 | |
104 | e0dfe5b1 | Scott Wood | static FslMpicInfo fsl_mpic_42 = {
|
105 | e0dfe5b1 | Scott Wood | .max_ext = 12,
|
106 | e0dfe5b1 | Scott Wood | }; |
107 | 3e772232 | Bharat Bhushan | |
108 | be7c236f | Scott Wood | #define FRR_NIRQ_SHIFT 16 |
109 | be7c236f | Scott Wood | #define FRR_NCPU_SHIFT 8 |
110 | be7c236f | Scott Wood | #define FRR_VID_SHIFT 0 |
111 | 825463b3 | Alexander Graf | |
112 | 825463b3 | Alexander Graf | #define VID_REVISION_1_2 2 |
113 | d0b72631 | Alexander Graf | #define VID_REVISION_1_3 3 |
114 | 825463b3 | Alexander Graf | |
115 | be7c236f | Scott Wood | #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */ |
116 | 825463b3 | Alexander Graf | |
117 | be7c236f | Scott Wood | #define GCR_RESET 0x80000000 |
118 | 68c2dd70 | Alexander Graf | #define GCR_MODE_PASS 0x00000000 |
119 | 68c2dd70 | Alexander Graf | #define GCR_MODE_MIXED 0x20000000 |
120 | 68c2dd70 | Alexander Graf | #define GCR_MODE_PROXY 0x60000000 |
121 | 71c6cacb | Scott Wood | |
122 | be7c236f | Scott Wood | #define TBCR_CI 0x80000000 /* count inhibit */ |
123 | be7c236f | Scott Wood | #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ |
124 | 825463b3 | Alexander Graf | |
125 | 1945dbc1 | Alexander Graf | #define IDR_EP_SHIFT 31 |
126 | 1945dbc1 | Alexander Graf | #define IDR_EP_MASK (1 << IDR_EP_SHIFT) |
127 | 1945dbc1 | Alexander Graf | #define IDR_CI0_SHIFT 30 |
128 | 1945dbc1 | Alexander Graf | #define IDR_CI1_SHIFT 29 |
129 | 1945dbc1 | Alexander Graf | #define IDR_P1_SHIFT 1 |
130 | 1945dbc1 | Alexander Graf | #define IDR_P0_SHIFT 0 |
131 | b7169916 | aurel32 | |
132 | e0dfe5b1 | Scott Wood | #define ILR_INTTGT_MASK 0x000000ff |
133 | e0dfe5b1 | Scott Wood | #define ILR_INTTGT_INT 0x00 |
134 | e0dfe5b1 | Scott Wood | #define ILR_INTTGT_CINT 0x01 /* critical */ |
135 | e0dfe5b1 | Scott Wood | #define ILR_INTTGT_MCP 0x02 /* machine check */ |
136 | e0dfe5b1 | Scott Wood | |
137 | e0dfe5b1 | Scott Wood | /* The currently supported INTTGT values happen to be the same as QEMU's
|
138 | e0dfe5b1 | Scott Wood | * openpic output codes, but don't depend on this. The output codes
|
139 | e0dfe5b1 | Scott Wood | * could change (unlikely, but...) or support could be added for
|
140 | e0dfe5b1 | Scott Wood | * more INTTGT values.
|
141 | e0dfe5b1 | Scott Wood | */
|
142 | e0dfe5b1 | Scott Wood | static const int inttgt_output[][2] = { |
143 | e0dfe5b1 | Scott Wood | { ILR_INTTGT_INT, OPENPIC_OUTPUT_INT }, |
144 | e0dfe5b1 | Scott Wood | { ILR_INTTGT_CINT, OPENPIC_OUTPUT_CINT }, |
145 | e0dfe5b1 | Scott Wood | { ILR_INTTGT_MCP, OPENPIC_OUTPUT_MCK }, |
146 | e0dfe5b1 | Scott Wood | }; |
147 | e0dfe5b1 | Scott Wood | |
148 | e0dfe5b1 | Scott Wood | static int inttgt_to_output(int inttgt) |
149 | e0dfe5b1 | Scott Wood | { |
150 | e0dfe5b1 | Scott Wood | int i;
|
151 | e0dfe5b1 | Scott Wood | |
152 | e0dfe5b1 | Scott Wood | for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) { |
153 | e0dfe5b1 | Scott Wood | if (inttgt_output[i][0] == inttgt) { |
154 | e0dfe5b1 | Scott Wood | return inttgt_output[i][1]; |
155 | e0dfe5b1 | Scott Wood | } |
156 | e0dfe5b1 | Scott Wood | } |
157 | e0dfe5b1 | Scott Wood | |
158 | e0dfe5b1 | Scott Wood | fprintf(stderr, "%s: unsupported inttgt %d\n", __func__, inttgt);
|
159 | e0dfe5b1 | Scott Wood | return OPENPIC_OUTPUT_INT;
|
160 | e0dfe5b1 | Scott Wood | } |
161 | e0dfe5b1 | Scott Wood | |
162 | e0dfe5b1 | Scott Wood | static int output_to_inttgt(int output) |
163 | e0dfe5b1 | Scott Wood | { |
164 | e0dfe5b1 | Scott Wood | int i;
|
165 | e0dfe5b1 | Scott Wood | |
166 | e0dfe5b1 | Scott Wood | for (i = 0; i < ARRAY_SIZE(inttgt_output); i++) { |
167 | e0dfe5b1 | Scott Wood | if (inttgt_output[i][1] == output) { |
168 | e0dfe5b1 | Scott Wood | return inttgt_output[i][0]; |
169 | e0dfe5b1 | Scott Wood | } |
170 | e0dfe5b1 | Scott Wood | } |
171 | e0dfe5b1 | Scott Wood | |
172 | e0dfe5b1 | Scott Wood | abort(); |
173 | e0dfe5b1 | Scott Wood | } |
174 | e0dfe5b1 | Scott Wood | |
175 | 732aa6ec | Alexander Graf | #define MSIIR_OFFSET 0x140 |
176 | 732aa6ec | Alexander Graf | #define MSIIR_SRS_SHIFT 29 |
177 | 732aa6ec | Alexander Graf | #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT) |
178 | 732aa6ec | Alexander Graf | #define MSIIR_IBS_SHIFT 24 |
179 | 732aa6ec | Alexander Graf | #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT) |
180 | 732aa6ec | Alexander Graf | |
181 | 704c7e5d | Alexander Graf | static int get_current_cpu(void) |
182 | 704c7e5d | Alexander Graf | { |
183 | 55e5c285 | Andreas Färber | CPUState *cpu_single_cpu; |
184 | 55e5c285 | Andreas Färber | |
185 | c3203fa5 | Scott Wood | if (!cpu_single_env) {
|
186 | c3203fa5 | Scott Wood | return -1; |
187 | c3203fa5 | Scott Wood | } |
188 | c3203fa5 | Scott Wood | |
189 | 55e5c285 | Andreas Färber | cpu_single_cpu = ENV_GET_CPU(cpu_single_env); |
190 | 55e5c285 | Andreas Färber | return cpu_single_cpu->cpu_index;
|
191 | 704c7e5d | Alexander Graf | } |
192 | 704c7e5d | Alexander Graf | |
193 | a8170e5e | Avi Kivity | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
194 | 704c7e5d | Alexander Graf | int idx);
|
195 | a8170e5e | Avi Kivity | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
196 | 704c7e5d | Alexander Graf | uint32_t val, int idx);
|
197 | 704c7e5d | Alexander Graf | |
198 | 6c5e84c2 | Scott Wood | typedef enum IRQType { |
199 | 6c5e84c2 | Scott Wood | IRQ_TYPE_NORMAL = 0,
|
200 | 6c5e84c2 | Scott Wood | IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
|
201 | 6c5e84c2 | Scott Wood | IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
|
202 | 6c5e84c2 | Scott Wood | } IRQType; |
203 | 6c5e84c2 | Scott Wood | |
204 | af7e9e74 | Alexander Graf | typedef struct IRQQueue { |
205 | e69a17f6 | Scott Wood | /* Round up to the nearest 64 IRQs so that the queue length
|
206 | e69a17f6 | Scott Wood | * won't change when moving between 32 and 64 bit hosts.
|
207 | e69a17f6 | Scott Wood | */
|
208 | 8935a442 | Scott Wood | unsigned long queue[BITS_TO_LONGS((OPENPIC_MAX_IRQ + 63) & ~63)]; |
209 | dbda808a | bellard | int next;
|
210 | dbda808a | bellard | int priority;
|
211 | af7e9e74 | Alexander Graf | } IRQQueue; |
212 | dbda808a | bellard | |
213 | af7e9e74 | Alexander Graf | typedef struct IRQSource { |
214 | be7c236f | Scott Wood | uint32_t ivpr; /* IRQ vector/priority register */
|
215 | be7c236f | Scott Wood | uint32_t idr; /* IRQ destination register */
|
216 | 5e22c276 | Scott Wood | uint32_t destmask; /* bitmap of CPU destinations */
|
217 | dbda808a | bellard | int last_cpu;
|
218 | 5e22c276 | Scott Wood | int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */ |
219 | 611493d9 | bellard | int pending; /* TRUE if IRQ is pending */ |
220 | 6c5e84c2 | Scott Wood | IRQType type; |
221 | 6c5e84c2 | Scott Wood | bool level:1; /* level-triggered */ |
222 | 72c1da2c | Scott Wood | bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */ |
223 | af7e9e74 | Alexander Graf | } IRQSource; |
224 | dbda808a | bellard | |
225 | be7c236f | Scott Wood | #define IVPR_MASK_SHIFT 31 |
226 | be7c236f | Scott Wood | #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) |
227 | be7c236f | Scott Wood | #define IVPR_ACTIVITY_SHIFT 30 |
228 | be7c236f | Scott Wood | #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) |
229 | be7c236f | Scott Wood | #define IVPR_MODE_SHIFT 29 |
230 | be7c236f | Scott Wood | #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) |
231 | be7c236f | Scott Wood | #define IVPR_POLARITY_SHIFT 23 |
232 | be7c236f | Scott Wood | #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) |
233 | be7c236f | Scott Wood | #define IVPR_SENSE_SHIFT 22 |
234 | be7c236f | Scott Wood | #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) |
235 | be7c236f | Scott Wood | |
236 | be7c236f | Scott Wood | #define IVPR_PRIORITY_MASK (0xF << 16) |
237 | be7c236f | Scott Wood | #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) |
238 | be7c236f | Scott Wood | #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
|
239 | be7c236f | Scott Wood | |
240 | be7c236f | Scott Wood | /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
|
241 | be7c236f | Scott Wood | #define IDR_EP 0x80000000 /* external pin */ |
242 | be7c236f | Scott Wood | #define IDR_CI 0x40000000 /* critical interrupt */ |
243 | 71c6cacb | Scott Wood | |
244 | af7e9e74 | Alexander Graf | typedef struct IRQDest { |
245 | eb438427 | Scott Wood | int32_t ctpr; /* CPU current task priority */
|
246 | af7e9e74 | Alexander Graf | IRQQueue raised; |
247 | af7e9e74 | Alexander Graf | IRQQueue servicing; |
248 | e9df014c | j_mayer | qemu_irq *irqs; |
249 | 9f1d4b1d | Scott Wood | |
250 | 9f1d4b1d | Scott Wood | /* Count of IRQ sources asserting on non-INT outputs */
|
251 | 9f1d4b1d | Scott Wood | uint32_t outputs_active[OPENPIC_OUTPUT_NB]; |
252 | af7e9e74 | Alexander Graf | } IRQDest; |
253 | dbda808a | bellard | |
254 | e1766344 | Andreas Färber | #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
|
255 | e1766344 | Andreas Färber | |
256 | 6d544ee8 | Alexander Graf | typedef struct OpenPICState { |
257 | e1766344 | Andreas Färber | /*< private >*/
|
258 | e1766344 | Andreas Färber | SysBusDevice parent_obj; |
259 | e1766344 | Andreas Färber | /*< public >*/
|
260 | e1766344 | Andreas Färber | |
261 | 23c5e4ca | Avi Kivity | MemoryRegion mem; |
262 | 71cf9e62 | Fabien Chouteau | |
263 | 5861a338 | Alexander Graf | /* Behavior control */
|
264 | e0dfe5b1 | Scott Wood | FslMpicInfo *fsl; |
265 | d0b72631 | Alexander Graf | uint32_t model; |
266 | 5861a338 | Alexander Graf | uint32_t flags; |
267 | 825463b3 | Alexander Graf | uint32_t nb_irqs; |
268 | 825463b3 | Alexander Graf | uint32_t vid; |
269 | be7c236f | Scott Wood | uint32_t vir; /* Vendor identification register */
|
270 | 0fe04622 | Scott Wood | uint32_t vector_mask; |
271 | be7c236f | Scott Wood | uint32_t tfrr_reset; |
272 | be7c236f | Scott Wood | uint32_t ivpr_reset; |
273 | be7c236f | Scott Wood | uint32_t idr_reset; |
274 | dbbbfd60 | Alexander Graf | uint32_t brr1; |
275 | 68c2dd70 | Alexander Graf | uint32_t mpic_mode_mask; |
276 | 5861a338 | Alexander Graf | |
277 | 71cf9e62 | Fabien Chouteau | /* Sub-regions */
|
278 | e0dfe5b1 | Scott Wood | MemoryRegion sub_io_mem[6];
|
279 | 71cf9e62 | Fabien Chouteau | |
280 | dbda808a | bellard | /* Global registers */
|
281 | be7c236f | Scott Wood | uint32_t frr; /* Feature reporting register */
|
282 | be7c236f | Scott Wood | uint32_t gcr; /* Global configuration register */
|
283 | be7c236f | Scott Wood | uint32_t pir; /* Processor initialization register */
|
284 | dbda808a | bellard | uint32_t spve; /* Spurious vector register */
|
285 | be7c236f | Scott Wood | uint32_t tfrr; /* Timer frequency reporting register */
|
286 | dbda808a | bellard | /* Source registers */
|
287 | 8935a442 | Scott Wood | IRQSource src[OPENPIC_MAX_IRQ]; |
288 | dbda808a | bellard | /* Local registers per output pin */
|
289 | af7e9e74 | Alexander Graf | IRQDest dst[MAX_CPU]; |
290 | d0b72631 | Alexander Graf | uint32_t nb_cpus; |
291 | dbda808a | bellard | /* Timer registers */
|
292 | dbda808a | bellard | struct {
|
293 | be7c236f | Scott Wood | uint32_t tccr; /* Global timer current count register */
|
294 | be7c236f | Scott Wood | uint32_t tbcr; /* Global timer base count register */
|
295 | 8935a442 | Scott Wood | } timers[OPENPIC_MAX_TMR]; |
296 | 732aa6ec | Alexander Graf | /* Shared MSI registers */
|
297 | 732aa6ec | Alexander Graf | struct {
|
298 | 732aa6ec | Alexander Graf | uint32_t msir; /* Shared Message Signaled Interrupt Register */
|
299 | 732aa6ec | Alexander Graf | } msi[MAX_MSI]; |
300 | d0b72631 | Alexander Graf | uint32_t max_irq; |
301 | d0b72631 | Alexander Graf | uint32_t irq_ipi0; |
302 | d0b72631 | Alexander Graf | uint32_t irq_tim0; |
303 | 732aa6ec | Alexander Graf | uint32_t irq_msi; |
304 | 6d544ee8 | Alexander Graf | } OpenPICState; |
305 | dbda808a | bellard | |
306 | af7e9e74 | Alexander Graf | static inline void IRQ_setbit(IRQQueue *q, int n_IRQ) |
307 | dbda808a | bellard | { |
308 | e69a17f6 | Scott Wood | set_bit(n_IRQ, q->queue); |
309 | dbda808a | bellard | } |
310 | dbda808a | bellard | |
311 | af7e9e74 | Alexander Graf | static inline void IRQ_resetbit(IRQQueue *q, int n_IRQ) |
312 | dbda808a | bellard | { |
313 | e69a17f6 | Scott Wood | clear_bit(n_IRQ, q->queue); |
314 | dbda808a | bellard | } |
315 | dbda808a | bellard | |
316 | af7e9e74 | Alexander Graf | static inline int IRQ_testbit(IRQQueue *q, int n_IRQ) |
317 | dbda808a | bellard | { |
318 | e69a17f6 | Scott Wood | return test_bit(n_IRQ, q->queue);
|
319 | dbda808a | bellard | } |
320 | dbda808a | bellard | |
321 | af7e9e74 | Alexander Graf | static void IRQ_check(OpenPICState *opp, IRQQueue *q) |
322 | dbda808a | bellard | { |
323 | 4417c733 | Scott Wood | int irq = -1; |
324 | 4417c733 | Scott Wood | int next = -1; |
325 | 4417c733 | Scott Wood | int priority = -1; |
326 | 4417c733 | Scott Wood | |
327 | 4417c733 | Scott Wood | for (;;) {
|
328 | 4417c733 | Scott Wood | irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
|
329 | 4417c733 | Scott Wood | if (irq == opp->max_irq) {
|
330 | 4417c733 | Scott Wood | break;
|
331 | 4417c733 | Scott Wood | } |
332 | 76aec1f8 | Alexander Graf | |
333 | 4417c733 | Scott Wood | DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
|
334 | 4417c733 | Scott Wood | irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority); |
335 | 76aec1f8 | Alexander Graf | |
336 | 4417c733 | Scott Wood | if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
|
337 | 4417c733 | Scott Wood | next = irq; |
338 | 4417c733 | Scott Wood | priority = IVPR_PRIORITY(opp->src[irq].ivpr); |
339 | 060fbfe1 | Aurelien Jarno | } |
340 | dbda808a | bellard | } |
341 | 76aec1f8 | Alexander Graf | |
342 | dbda808a | bellard | q->next = next; |
343 | dbda808a | bellard | q->priority = priority; |
344 | dbda808a | bellard | } |
345 | dbda808a | bellard | |
346 | af7e9e74 | Alexander Graf | static int IRQ_get_next(OpenPICState *opp, IRQQueue *q) |
347 | dbda808a | bellard | { |
348 | 3c94378e | Scott Wood | /* XXX: optimize */
|
349 | 3c94378e | Scott Wood | IRQ_check(opp, q); |
350 | dbda808a | bellard | |
351 | dbda808a | bellard | return q->next;
|
352 | dbda808a | bellard | } |
353 | dbda808a | bellard | |
354 | 9f1d4b1d | Scott Wood | static void IRQ_local_pipe(OpenPICState *opp, int n_CPU, int n_IRQ, |
355 | 9f1d4b1d | Scott Wood | bool active, bool was_active) |
356 | dbda808a | bellard | { |
357 | af7e9e74 | Alexander Graf | IRQDest *dst; |
358 | af7e9e74 | Alexander Graf | IRQSource *src; |
359 | dbda808a | bellard | int priority;
|
360 | dbda808a | bellard | |
361 | dbda808a | bellard | dst = &opp->dst[n_CPU]; |
362 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
363 | 5e22c276 | Scott Wood | |
364 | 9f1d4b1d | Scott Wood | DPRINTF("%s: IRQ %d active %d was %d\n",
|
365 | 9f1d4b1d | Scott Wood | __func__, n_IRQ, active, was_active); |
366 | 9f1d4b1d | Scott Wood | |
367 | 5e22c276 | Scott Wood | if (src->output != OPENPIC_OUTPUT_INT) {
|
368 | 9f1d4b1d | Scott Wood | DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
|
369 | 9f1d4b1d | Scott Wood | __func__, src->output, n_IRQ, active, was_active, |
370 | 9f1d4b1d | Scott Wood | dst->outputs_active[src->output]); |
371 | 9f1d4b1d | Scott Wood | |
372 | 5e22c276 | Scott Wood | /* On Freescale MPIC, critical interrupts ignore priority,
|
373 | 5e22c276 | Scott Wood | * IACK, EOI, etc. Before MPIC v4.1 they also ignore
|
374 | 5e22c276 | Scott Wood | * masking.
|
375 | 5e22c276 | Scott Wood | */
|
376 | 9f1d4b1d | Scott Wood | if (active) {
|
377 | 9f1d4b1d | Scott Wood | if (!was_active && dst->outputs_active[src->output]++ == 0) { |
378 | 9f1d4b1d | Scott Wood | DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
|
379 | 9f1d4b1d | Scott Wood | __func__, src->output, n_CPU, n_IRQ); |
380 | 9f1d4b1d | Scott Wood | qemu_irq_raise(dst->irqs[src->output]); |
381 | 9f1d4b1d | Scott Wood | } |
382 | 9f1d4b1d | Scott Wood | } else {
|
383 | 9f1d4b1d | Scott Wood | if (was_active && --dst->outputs_active[src->output] == 0) { |
384 | 9f1d4b1d | Scott Wood | DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
|
385 | 9f1d4b1d | Scott Wood | __func__, src->output, n_CPU, n_IRQ); |
386 | 9f1d4b1d | Scott Wood | qemu_irq_lower(dst->irqs[src->output]); |
387 | 9f1d4b1d | Scott Wood | } |
388 | 9f1d4b1d | Scott Wood | } |
389 | 9f1d4b1d | Scott Wood | |
390 | 060fbfe1 | Aurelien Jarno | return;
|
391 | dbda808a | bellard | } |
392 | 5e22c276 | Scott Wood | |
393 | be7c236f | Scott Wood | priority = IVPR_PRIORITY(src->ivpr); |
394 | 9f1d4b1d | Scott Wood | |
395 | 9f1d4b1d | Scott Wood | /* Even if the interrupt doesn't have enough priority,
|
396 | 9f1d4b1d | Scott Wood | * it is still raised, in case ctpr is lowered later.
|
397 | 9f1d4b1d | Scott Wood | */
|
398 | 9f1d4b1d | Scott Wood | if (active) {
|
399 | 9f1d4b1d | Scott Wood | IRQ_setbit(&dst->raised, n_IRQ); |
400 | 9f1d4b1d | Scott Wood | } else {
|
401 | 9f1d4b1d | Scott Wood | IRQ_resetbit(&dst->raised, n_IRQ); |
402 | dbda808a | bellard | } |
403 | 9f1d4b1d | Scott Wood | |
404 | 3c94378e | Scott Wood | IRQ_check(opp, &dst->raised); |
405 | 9f1d4b1d | Scott Wood | |
406 | 9f1d4b1d | Scott Wood | if (active && priority <= dst->ctpr) {
|
407 | 9f1d4b1d | Scott Wood | DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
|
408 | 9f1d4b1d | Scott Wood | __func__, n_IRQ, priority, dst->ctpr, n_CPU); |
409 | 9f1d4b1d | Scott Wood | active = 0;
|
410 | e9df014c | j_mayer | } |
411 | 9f1d4b1d | Scott Wood | |
412 | 9f1d4b1d | Scott Wood | if (active) {
|
413 | 9f1d4b1d | Scott Wood | if (IRQ_get_next(opp, &dst->servicing) >= 0 && |
414 | 9f1d4b1d | Scott Wood | priority <= dst->servicing.priority) { |
415 | 9f1d4b1d | Scott Wood | DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
|
416 | 9f1d4b1d | Scott Wood | __func__, n_IRQ, dst->servicing.next, n_CPU); |
417 | 9f1d4b1d | Scott Wood | } else {
|
418 | 9f1d4b1d | Scott Wood | DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
|
419 | 9f1d4b1d | Scott Wood | __func__, n_CPU, n_IRQ, dst->raised.next); |
420 | 9f1d4b1d | Scott Wood | qemu_irq_raise(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
421 | 9f1d4b1d | Scott Wood | } |
422 | 9f1d4b1d | Scott Wood | } else {
|
423 | 9f1d4b1d | Scott Wood | IRQ_get_next(opp, &dst->servicing); |
424 | 9f1d4b1d | Scott Wood | if (dst->raised.priority > dst->ctpr &&
|
425 | 9f1d4b1d | Scott Wood | dst->raised.priority > dst->servicing.priority) { |
426 | 9f1d4b1d | Scott Wood | DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
|
427 | 9f1d4b1d | Scott Wood | __func__, n_IRQ, dst->raised.next, dst->raised.priority, |
428 | 9f1d4b1d | Scott Wood | dst->ctpr, dst->servicing.priority, n_CPU); |
429 | 9f1d4b1d | Scott Wood | /* IRQ line stays asserted */
|
430 | 9f1d4b1d | Scott Wood | } else {
|
431 | 9f1d4b1d | Scott Wood | DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
|
432 | 9f1d4b1d | Scott Wood | __func__, n_IRQ, dst->ctpr, dst->servicing.priority, n_CPU); |
433 | 9f1d4b1d | Scott Wood | qemu_irq_lower(opp->dst[n_CPU].irqs[OPENPIC_OUTPUT_INT]); |
434 | 9f1d4b1d | Scott Wood | } |
435 | dbda808a | bellard | } |
436 | dbda808a | bellard | } |
437 | dbda808a | bellard | |
438 | 611493d9 | bellard | /* update pic state because registers for n_IRQ have changed value */
|
439 | 6d544ee8 | Alexander Graf | static void openpic_update_irq(OpenPICState *opp, int n_IRQ) |
440 | dbda808a | bellard | { |
441 | af7e9e74 | Alexander Graf | IRQSource *src; |
442 | 9f1d4b1d | Scott Wood | bool active, was_active;
|
443 | dbda808a | bellard | int i;
|
444 | dbda808a | bellard | |
445 | dbda808a | bellard | src = &opp->src[n_IRQ]; |
446 | 9f1d4b1d | Scott Wood | active = src->pending; |
447 | 611493d9 | bellard | |
448 | 72c1da2c | Scott Wood | if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
|
449 | 060fbfe1 | Aurelien Jarno | /* Interrupt source is disabled */
|
450 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
|
451 | 9f1d4b1d | Scott Wood | active = false;
|
452 | dbda808a | bellard | } |
453 | 9f1d4b1d | Scott Wood | |
454 | 9f1d4b1d | Scott Wood | was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK); |
455 | 9f1d4b1d | Scott Wood | |
456 | 9f1d4b1d | Scott Wood | /*
|
457 | 9f1d4b1d | Scott Wood | * We don't have a similar check for already-active because
|
458 | 9f1d4b1d | Scott Wood | * ctpr may have changed and we need to withdraw the interrupt.
|
459 | 9f1d4b1d | Scott Wood | */
|
460 | 9f1d4b1d | Scott Wood | if (!active && !was_active) {
|
461 | 9f1d4b1d | Scott Wood | DPRINTF("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
|
462 | 060fbfe1 | Aurelien Jarno | return;
|
463 | dbda808a | bellard | } |
464 | 9f1d4b1d | Scott Wood | |
465 | 9f1d4b1d | Scott Wood | if (active) {
|
466 | 9f1d4b1d | Scott Wood | src->ivpr |= IVPR_ACTIVITY_MASK; |
467 | 9f1d4b1d | Scott Wood | } else {
|
468 | 9f1d4b1d | Scott Wood | src->ivpr &= ~IVPR_ACTIVITY_MASK; |
469 | 611493d9 | bellard | } |
470 | 9f1d4b1d | Scott Wood | |
471 | f40c360c | Scott Wood | if (src->destmask == 0) { |
472 | 060fbfe1 | Aurelien Jarno | /* No target */
|
473 | e9df014c | j_mayer | DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
|
474 | 060fbfe1 | Aurelien Jarno | return;
|
475 | dbda808a | bellard | } |
476 | 611493d9 | bellard | |
477 | f40c360c | Scott Wood | if (src->destmask == (1 << src->last_cpu)) { |
478 | e9df014c | j_mayer | /* Only one CPU is allowed to receive this IRQ */
|
479 | 9f1d4b1d | Scott Wood | IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active); |
480 | be7c236f | Scott Wood | } else if (!(src->ivpr & IVPR_MODE_MASK)) { |
481 | 611493d9 | bellard | /* Directed delivery mode */
|
482 | 611493d9 | bellard | for (i = 0; i < opp->nb_cpus; i++) { |
483 | 5e22c276 | Scott Wood | if (src->destmask & (1 << i)) { |
484 | 9f1d4b1d | Scott Wood | IRQ_local_pipe(opp, i, n_IRQ, active, was_active); |
485 | 1945dbc1 | Alexander Graf | } |
486 | 611493d9 | bellard | } |
487 | dbda808a | bellard | } else {
|
488 | 611493d9 | bellard | /* Distributed delivery mode */
|
489 | e9df014c | j_mayer | for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
490 | af7e9e74 | Alexander Graf | if (i == opp->nb_cpus) {
|
491 | 611493d9 | bellard | i = 0;
|
492 | af7e9e74 | Alexander Graf | } |
493 | 5e22c276 | Scott Wood | if (src->destmask & (1 << i)) { |
494 | 9f1d4b1d | Scott Wood | IRQ_local_pipe(opp, i, n_IRQ, active, was_active); |
495 | 611493d9 | bellard | src->last_cpu = i; |
496 | 611493d9 | bellard | break;
|
497 | 611493d9 | bellard | } |
498 | 611493d9 | bellard | } |
499 | 611493d9 | bellard | } |
500 | 611493d9 | bellard | } |
501 | 611493d9 | bellard | |
502 | d537cf6c | pbrook | static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
503 | 611493d9 | bellard | { |
504 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
505 | af7e9e74 | Alexander Graf | IRQSource *src; |
506 | 611493d9 | bellard | |
507 | 8935a442 | Scott Wood | if (n_IRQ >= OPENPIC_MAX_IRQ) {
|
508 | 65b9d0d5 | Scott Wood | fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ);
|
509 | 65b9d0d5 | Scott Wood | abort(); |
510 | 65b9d0d5 | Scott Wood | } |
511 | 611493d9 | bellard | |
512 | 611493d9 | bellard | src = &opp->src[n_IRQ]; |
513 | be7c236f | Scott Wood | DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
|
514 | be7c236f | Scott Wood | n_IRQ, level, src->ivpr); |
515 | 6c5e84c2 | Scott Wood | if (src->level) {
|
516 | 611493d9 | bellard | /* level-sensitive irq */
|
517 | 611493d9 | bellard | src->pending = level; |
518 | 9f1d4b1d | Scott Wood | openpic_update_irq(opp, n_IRQ); |
519 | 611493d9 | bellard | } else {
|
520 | 611493d9 | bellard | /* edge-sensitive irq */
|
521 | af7e9e74 | Alexander Graf | if (level) {
|
522 | 611493d9 | bellard | src->pending = 1;
|
523 | 9f1d4b1d | Scott Wood | openpic_update_irq(opp, n_IRQ); |
524 | 9f1d4b1d | Scott Wood | } |
525 | 9f1d4b1d | Scott Wood | |
526 | 9f1d4b1d | Scott Wood | if (src->output != OPENPIC_OUTPUT_INT) {
|
527 | 9f1d4b1d | Scott Wood | /* Edge-triggered interrupts shouldn't be used
|
528 | 9f1d4b1d | Scott Wood | * with non-INT delivery, but just in case,
|
529 | 9f1d4b1d | Scott Wood | * try to make it do something sane rather than
|
530 | 9f1d4b1d | Scott Wood | * cause an interrupt storm. This is close to
|
531 | 9f1d4b1d | Scott Wood | * what you'd probably see happen in real hardware.
|
532 | 9f1d4b1d | Scott Wood | */
|
533 | 9f1d4b1d | Scott Wood | src->pending = 0;
|
534 | 9f1d4b1d | Scott Wood | openpic_update_irq(opp, n_IRQ); |
535 | af7e9e74 | Alexander Graf | } |
536 | dbda808a | bellard | } |
537 | dbda808a | bellard | } |
538 | dbda808a | bellard | |
539 | d0b72631 | Alexander Graf | static void openpic_reset(DeviceState *d) |
540 | dbda808a | bellard | { |
541 | e1766344 | Andreas Färber | OpenPICState *opp = OPENPIC(d); |
542 | dbda808a | bellard | int i;
|
543 | dbda808a | bellard | |
544 | be7c236f | Scott Wood | opp->gcr = GCR_RESET; |
545 | f8407028 | bellard | /* Initialise controller registers */
|
546 | be7c236f | Scott Wood | opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
|
547 | be7c236f | Scott Wood | ((opp->nb_cpus - 1) << FRR_NCPU_SHIFT) |
|
548 | be7c236f | Scott Wood | (opp->vid << FRR_VID_SHIFT); |
549 | 825463b3 | Alexander Graf | |
550 | be7c236f | Scott Wood | opp->pir = 0;
|
551 | 0fe04622 | Scott Wood | opp->spve = -1 & opp->vector_mask;
|
552 | be7c236f | Scott Wood | opp->tfrr = opp->tfrr_reset; |
553 | dbda808a | bellard | /* Initialise IRQ sources */
|
554 | b7169916 | aurel32 | for (i = 0; i < opp->max_irq; i++) { |
555 | be7c236f | Scott Wood | opp->src[i].ivpr = opp->ivpr_reset; |
556 | be7c236f | Scott Wood | opp->src[i].idr = opp->idr_reset; |
557 | 6c5e84c2 | Scott Wood | |
558 | 6c5e84c2 | Scott Wood | switch (opp->src[i].type) {
|
559 | 6c5e84c2 | Scott Wood | case IRQ_TYPE_NORMAL:
|
560 | 6c5e84c2 | Scott Wood | opp->src[i].level = !!(opp->ivpr_reset & IVPR_SENSE_MASK); |
561 | 6c5e84c2 | Scott Wood | break;
|
562 | 6c5e84c2 | Scott Wood | |
563 | 6c5e84c2 | Scott Wood | case IRQ_TYPE_FSLINT:
|
564 | 6c5e84c2 | Scott Wood | opp->src[i].ivpr |= IVPR_POLARITY_MASK; |
565 | 6c5e84c2 | Scott Wood | break;
|
566 | 6c5e84c2 | Scott Wood | |
567 | 6c5e84c2 | Scott Wood | case IRQ_TYPE_FSLSPECIAL:
|
568 | 6c5e84c2 | Scott Wood | break;
|
569 | 6c5e84c2 | Scott Wood | } |
570 | dbda808a | bellard | } |
571 | dbda808a | bellard | /* Initialise IRQ destinations */
|
572 | e9df014c | j_mayer | for (i = 0; i < MAX_CPU; i++) { |
573 | be7c236f | Scott Wood | opp->dst[i].ctpr = 15;
|
574 | af7e9e74 | Alexander Graf | memset(&opp->dst[i].raised, 0, sizeof(IRQQueue)); |
575 | d14ed254 | Alexander Graf | opp->dst[i].raised.next = -1;
|
576 | af7e9e74 | Alexander Graf | memset(&opp->dst[i].servicing, 0, sizeof(IRQQueue)); |
577 | d14ed254 | Alexander Graf | opp->dst[i].servicing.next = -1;
|
578 | dbda808a | bellard | } |
579 | dbda808a | bellard | /* Initialise timers */
|
580 | 8935a442 | Scott Wood | for (i = 0; i < OPENPIC_MAX_TMR; i++) { |
581 | be7c236f | Scott Wood | opp->timers[i].tccr = 0;
|
582 | be7c236f | Scott Wood | opp->timers[i].tbcr = TBCR_CI; |
583 | dbda808a | bellard | } |
584 | dbda808a | bellard | /* Go out of RESET state */
|
585 | be7c236f | Scott Wood | opp->gcr = 0;
|
586 | dbda808a | bellard | } |
587 | dbda808a | bellard | |
588 | be7c236f | Scott Wood | static inline uint32_t read_IRQreg_idr(OpenPICState *opp, int n_IRQ) |
589 | dbda808a | bellard | { |
590 | be7c236f | Scott Wood | return opp->src[n_IRQ].idr;
|
591 | 8d3a8c1e | Alexander Graf | } |
592 | dbda808a | bellard | |
593 | e0dfe5b1 | Scott Wood | static inline uint32_t read_IRQreg_ilr(OpenPICState *opp, int n_IRQ) |
594 | e0dfe5b1 | Scott Wood | { |
595 | e0dfe5b1 | Scott Wood | if (opp->flags & OPENPIC_FLAG_ILR) {
|
596 | e0dfe5b1 | Scott Wood | return output_to_inttgt(opp->src[n_IRQ].output);
|
597 | e0dfe5b1 | Scott Wood | } |
598 | e0dfe5b1 | Scott Wood | |
599 | e0dfe5b1 | Scott Wood | return 0xffffffff; |
600 | e0dfe5b1 | Scott Wood | } |
601 | e0dfe5b1 | Scott Wood | |
602 | be7c236f | Scott Wood | static inline uint32_t read_IRQreg_ivpr(OpenPICState *opp, int n_IRQ) |
603 | 8d3a8c1e | Alexander Graf | { |
604 | be7c236f | Scott Wood | return opp->src[n_IRQ].ivpr;
|
605 | dbda808a | bellard | } |
606 | dbda808a | bellard | |
607 | be7c236f | Scott Wood | static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val) |
608 | dbda808a | bellard | { |
609 | 5e22c276 | Scott Wood | IRQSource *src = &opp->src[n_IRQ]; |
610 | 5e22c276 | Scott Wood | uint32_t normal_mask = (1UL << opp->nb_cpus) - 1; |
611 | 5e22c276 | Scott Wood | uint32_t crit_mask = 0;
|
612 | 5e22c276 | Scott Wood | uint32_t mask = normal_mask; |
613 | 5e22c276 | Scott Wood | int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
|
614 | 5e22c276 | Scott Wood | int i;
|
615 | 5e22c276 | Scott Wood | |
616 | 5e22c276 | Scott Wood | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
|
617 | 5e22c276 | Scott Wood | crit_mask = mask << crit_shift; |
618 | 5e22c276 | Scott Wood | mask |= crit_mask | IDR_EP; |
619 | 5e22c276 | Scott Wood | } |
620 | 5e22c276 | Scott Wood | |
621 | 5e22c276 | Scott Wood | src->idr = val & mask; |
622 | 5e22c276 | Scott Wood | DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
|
623 | 5e22c276 | Scott Wood | |
624 | 5e22c276 | Scott Wood | if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
|
625 | 5e22c276 | Scott Wood | if (src->idr & crit_mask) {
|
626 | 5e22c276 | Scott Wood | if (src->idr & normal_mask) {
|
627 | 5e22c276 | Scott Wood | DPRINTF("%s: IRQ configured for multiple output types, using "
|
628 | 5e22c276 | Scott Wood | "critical\n", __func__);
|
629 | 5e22c276 | Scott Wood | } |
630 | dbda808a | bellard | |
631 | 5e22c276 | Scott Wood | src->output = OPENPIC_OUTPUT_CINT; |
632 | 72c1da2c | Scott Wood | src->nomask = true;
|
633 | 5e22c276 | Scott Wood | src->destmask = 0;
|
634 | 5e22c276 | Scott Wood | |
635 | 5e22c276 | Scott Wood | for (i = 0; i < opp->nb_cpus; i++) { |
636 | 5e22c276 | Scott Wood | int n_ci = IDR_CI0_SHIFT - i;
|
637 | dbda808a | bellard | |
638 | 5e22c276 | Scott Wood | if (src->idr & (1UL << n_ci)) { |
639 | 5e22c276 | Scott Wood | src->destmask |= 1UL << i;
|
640 | 5e22c276 | Scott Wood | } |
641 | 5e22c276 | Scott Wood | } |
642 | 5e22c276 | Scott Wood | } else {
|
643 | 5e22c276 | Scott Wood | src->output = OPENPIC_OUTPUT_INT; |
644 | 72c1da2c | Scott Wood | src->nomask = false;
|
645 | 5e22c276 | Scott Wood | src->destmask = src->idr & normal_mask; |
646 | 5e22c276 | Scott Wood | } |
647 | 5e22c276 | Scott Wood | } else {
|
648 | 5e22c276 | Scott Wood | src->destmask = src->idr; |
649 | 5e22c276 | Scott Wood | } |
650 | 11de8b71 | Alexander Graf | } |
651 | 11de8b71 | Alexander Graf | |
652 | e0dfe5b1 | Scott Wood | static inline void write_IRQreg_ilr(OpenPICState *opp, int n_IRQ, uint32_t val) |
653 | e0dfe5b1 | Scott Wood | { |
654 | e0dfe5b1 | Scott Wood | if (opp->flags & OPENPIC_FLAG_ILR) {
|
655 | e0dfe5b1 | Scott Wood | IRQSource *src = &opp->src[n_IRQ]; |
656 | e0dfe5b1 | Scott Wood | |
657 | e0dfe5b1 | Scott Wood | src->output = inttgt_to_output(val & ILR_INTTGT_MASK); |
658 | e0dfe5b1 | Scott Wood | DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
|
659 | e0dfe5b1 | Scott Wood | src->output); |
660 | e0dfe5b1 | Scott Wood | |
661 | e0dfe5b1 | Scott Wood | /* TODO: on MPIC v4.0 only, set nomask for non-INT */
|
662 | e0dfe5b1 | Scott Wood | } |
663 | e0dfe5b1 | Scott Wood | } |
664 | e0dfe5b1 | Scott Wood | |
665 | be7c236f | Scott Wood | static inline void write_IRQreg_ivpr(OpenPICState *opp, int n_IRQ, uint32_t val) |
666 | 11de8b71 | Alexander Graf | { |
667 | 6c5e84c2 | Scott Wood | uint32_t mask; |
668 | 6c5e84c2 | Scott Wood | |
669 | 6c5e84c2 | Scott Wood | /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
|
670 | 6c5e84c2 | Scott Wood | * the polarity bit is read-only on internal interrupts.
|
671 | 6c5e84c2 | Scott Wood | */
|
672 | 6c5e84c2 | Scott Wood | mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK | |
673 | 6c5e84c2 | Scott Wood | IVPR_POLARITY_MASK | opp->vector_mask; |
674 | 6c5e84c2 | Scott Wood | |
675 | 11de8b71 | Alexander Graf | /* ACTIVITY bit is read-only */
|
676 | 6c5e84c2 | Scott Wood | opp->src[n_IRQ].ivpr = |
677 | 6c5e84c2 | Scott Wood | (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask); |
678 | 6c5e84c2 | Scott Wood | |
679 | 6c5e84c2 | Scott Wood | /* For FSL internal interrupts, The sense bit is reserved and zero,
|
680 | 6c5e84c2 | Scott Wood | * and the interrupt is always level-triggered. Timers and IPIs
|
681 | 6c5e84c2 | Scott Wood | * have no sense or polarity bits, and are edge-triggered.
|
682 | 6c5e84c2 | Scott Wood | */
|
683 | 6c5e84c2 | Scott Wood | switch (opp->src[n_IRQ].type) {
|
684 | 6c5e84c2 | Scott Wood | case IRQ_TYPE_NORMAL:
|
685 | 6c5e84c2 | Scott Wood | opp->src[n_IRQ].level = !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK); |
686 | 6c5e84c2 | Scott Wood | break;
|
687 | 6c5e84c2 | Scott Wood | |
688 | 6c5e84c2 | Scott Wood | case IRQ_TYPE_FSLINT:
|
689 | 6c5e84c2 | Scott Wood | opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK; |
690 | 6c5e84c2 | Scott Wood | break;
|
691 | 6c5e84c2 | Scott Wood | |
692 | 6c5e84c2 | Scott Wood | case IRQ_TYPE_FSLSPECIAL:
|
693 | 6c5e84c2 | Scott Wood | opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK); |
694 | 6c5e84c2 | Scott Wood | break;
|
695 | 6c5e84c2 | Scott Wood | } |
696 | 6c5e84c2 | Scott Wood | |
697 | 11de8b71 | Alexander Graf | openpic_update_irq(opp, n_IRQ); |
698 | be7c236f | Scott Wood | DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
|
699 | be7c236f | Scott Wood | opp->src[n_IRQ].ivpr); |
700 | dbda808a | bellard | } |
701 | dbda808a | bellard | |
702 | 7f11573b | Alexander Graf | static void openpic_gcr_write(OpenPICState *opp, uint64_t val) |
703 | 7f11573b | Alexander Graf | { |
704 | e49798b1 | Alexander Graf | bool mpic_proxy = false; |
705 | 1ac3d713 | Alexander Graf | |
706 | 7f11573b | Alexander Graf | if (val & GCR_RESET) {
|
707 | e1766344 | Andreas Färber | openpic_reset(DEVICE(opp)); |
708 | 1ac3d713 | Alexander Graf | return;
|
709 | 1ac3d713 | Alexander Graf | } |
710 | 7f11573b | Alexander Graf | |
711 | 1ac3d713 | Alexander Graf | opp->gcr &= ~opp->mpic_mode_mask; |
712 | 1ac3d713 | Alexander Graf | opp->gcr |= val & opp->mpic_mode_mask; |
713 | 7f11573b | Alexander Graf | |
714 | 1ac3d713 | Alexander Graf | /* Set external proxy mode */
|
715 | 1ac3d713 | Alexander Graf | if ((val & opp->mpic_mode_mask) == GCR_MODE_PROXY) {
|
716 | e49798b1 | Alexander Graf | mpic_proxy = true;
|
717 | 7f11573b | Alexander Graf | } |
718 | e49798b1 | Alexander Graf | |
719 | e49798b1 | Alexander Graf | ppce500_set_mpic_proxy(mpic_proxy); |
720 | 7f11573b | Alexander Graf | } |
721 | 7f11573b | Alexander Graf | |
722 | b9b2aaa3 | Alexander Graf | static void openpic_gbl_write(void *opaque, hwaddr addr, uint64_t val, |
723 | b9b2aaa3 | Alexander Graf | unsigned len)
|
724 | dbda808a | bellard | { |
725 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
726 | af7e9e74 | Alexander Graf | IRQDest *dst; |
727 | e9df014c | j_mayer | int idx;
|
728 | dbda808a | bellard | |
729 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
730 | 4c4f0e48 | Scott Wood | __func__, addr, val); |
731 | af7e9e74 | Alexander Graf | if (addr & 0xF) { |
732 | dbda808a | bellard | return;
|
733 | af7e9e74 | Alexander Graf | } |
734 | dbda808a | bellard | switch (addr) {
|
735 | 3e772232 | Bharat Bhushan | case 0x00: /* Block Revision Register1 (BRR1) is Readonly */ |
736 | 3e772232 | Bharat Bhushan | break;
|
737 | 704c7e5d | Alexander Graf | case 0x40: |
738 | 704c7e5d | Alexander Graf | case 0x50: |
739 | 704c7e5d | Alexander Graf | case 0x60: |
740 | 704c7e5d | Alexander Graf | case 0x70: |
741 | 704c7e5d | Alexander Graf | case 0x80: |
742 | 704c7e5d | Alexander Graf | case 0x90: |
743 | 704c7e5d | Alexander Graf | case 0xA0: |
744 | 704c7e5d | Alexander Graf | case 0xB0: |
745 | 704c7e5d | Alexander Graf | openpic_cpu_write_internal(opp, addr, val, get_current_cpu()); |
746 | dbda808a | bellard | break;
|
747 | be7c236f | Scott Wood | case 0x1000: /* FRR */ |
748 | dbda808a | bellard | break;
|
749 | be7c236f | Scott Wood | case 0x1020: /* GCR */ |
750 | 7f11573b | Alexander Graf | openpic_gcr_write(opp, val); |
751 | 060fbfe1 | Aurelien Jarno | break;
|
752 | be7c236f | Scott Wood | case 0x1080: /* VIR */ |
753 | 060fbfe1 | Aurelien Jarno | break;
|
754 | be7c236f | Scott Wood | case 0x1090: /* PIR */ |
755 | e9df014c | j_mayer | for (idx = 0; idx < opp->nb_cpus; idx++) { |
756 | be7c236f | Scott Wood | if ((val & (1 << idx)) && !(opp->pir & (1 << idx))) { |
757 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
|
758 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
759 | e9df014c | j_mayer | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); |
760 | be7c236f | Scott Wood | } else if (!(val & (1 << idx)) && (opp->pir & (1 << idx))) { |
761 | e9df014c | j_mayer | DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx);
|
762 | e9df014c | j_mayer | dst = &opp->dst[idx]; |
763 | e9df014c | j_mayer | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); |
764 | e9df014c | j_mayer | } |
765 | dbda808a | bellard | } |
766 | be7c236f | Scott Wood | opp->pir = val; |
767 | 060fbfe1 | Aurelien Jarno | break;
|
768 | be7c236f | Scott Wood | case 0x10A0: /* IPI_IVPR */ |
769 | 704c7e5d | Alexander Graf | case 0x10B0: |
770 | 704c7e5d | Alexander Graf | case 0x10C0: |
771 | 704c7e5d | Alexander Graf | case 0x10D0: |
772 | dbda808a | bellard | { |
773 | dbda808a | bellard | int idx;
|
774 | 704c7e5d | Alexander Graf | idx = (addr - 0x10A0) >> 4; |
775 | be7c236f | Scott Wood | write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val); |
776 | dbda808a | bellard | } |
777 | dbda808a | bellard | break;
|
778 | 704c7e5d | Alexander Graf | case 0x10E0: /* SPVE */ |
779 | 0fe04622 | Scott Wood | opp->spve = val & opp->vector_mask; |
780 | dbda808a | bellard | break;
|
781 | dbda808a | bellard | default:
|
782 | dbda808a | bellard | break;
|
783 | dbda808a | bellard | } |
784 | dbda808a | bellard | } |
785 | dbda808a | bellard | |
786 | b9b2aaa3 | Alexander Graf | static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) |
787 | dbda808a | bellard | { |
788 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
789 | dbda808a | bellard | uint32_t retval; |
790 | dbda808a | bellard | |
791 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
792 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
793 | af7e9e74 | Alexander Graf | if (addr & 0xF) { |
794 | dbda808a | bellard | return retval;
|
795 | af7e9e74 | Alexander Graf | } |
796 | dbda808a | bellard | switch (addr) {
|
797 | be7c236f | Scott Wood | case 0x1000: /* FRR */ |
798 | be7c236f | Scott Wood | retval = opp->frr; |
799 | dbda808a | bellard | break;
|
800 | be7c236f | Scott Wood | case 0x1020: /* GCR */ |
801 | be7c236f | Scott Wood | retval = opp->gcr; |
802 | 060fbfe1 | Aurelien Jarno | break;
|
803 | be7c236f | Scott Wood | case 0x1080: /* VIR */ |
804 | be7c236f | Scott Wood | retval = opp->vir; |
805 | 060fbfe1 | Aurelien Jarno | break;
|
806 | be7c236f | Scott Wood | case 0x1090: /* PIR */ |
807 | dbda808a | bellard | retval = 0x00000000;
|
808 | 060fbfe1 | Aurelien Jarno | break;
|
809 | 3e772232 | Bharat Bhushan | case 0x00: /* Block Revision Register1 (BRR1) */ |
810 | 0d404683 | Scott Wood | retval = opp->brr1; |
811 | 0d404683 | Scott Wood | break;
|
812 | 704c7e5d | Alexander Graf | case 0x40: |
813 | 704c7e5d | Alexander Graf | case 0x50: |
814 | 704c7e5d | Alexander Graf | case 0x60: |
815 | 704c7e5d | Alexander Graf | case 0x70: |
816 | 704c7e5d | Alexander Graf | case 0x80: |
817 | 704c7e5d | Alexander Graf | case 0x90: |
818 | 704c7e5d | Alexander Graf | case 0xA0: |
819 | dbda808a | bellard | case 0xB0: |
820 | 704c7e5d | Alexander Graf | retval = openpic_cpu_read_internal(opp, addr, get_current_cpu()); |
821 | 704c7e5d | Alexander Graf | break;
|
822 | be7c236f | Scott Wood | case 0x10A0: /* IPI_IVPR */ |
823 | 704c7e5d | Alexander Graf | case 0x10B0: |
824 | 704c7e5d | Alexander Graf | case 0x10C0: |
825 | 704c7e5d | Alexander Graf | case 0x10D0: |
826 | dbda808a | bellard | { |
827 | dbda808a | bellard | int idx;
|
828 | 704c7e5d | Alexander Graf | idx = (addr - 0x10A0) >> 4; |
829 | be7c236f | Scott Wood | retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx); |
830 | dbda808a | bellard | } |
831 | 060fbfe1 | Aurelien Jarno | break;
|
832 | 704c7e5d | Alexander Graf | case 0x10E0: /* SPVE */ |
833 | dbda808a | bellard | retval = opp->spve; |
834 | dbda808a | bellard | break;
|
835 | dbda808a | bellard | default:
|
836 | dbda808a | bellard | break;
|
837 | dbda808a | bellard | } |
838 | 4c4f0e48 | Scott Wood | DPRINTF("%s: => 0x%08x\n", __func__, retval);
|
839 | dbda808a | bellard | |
840 | dbda808a | bellard | return retval;
|
841 | dbda808a | bellard | } |
842 | dbda808a | bellard | |
843 | 6d544ee8 | Alexander Graf | static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val, |
844 | b9b2aaa3 | Alexander Graf | unsigned len)
|
845 | dbda808a | bellard | { |
846 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
847 | dbda808a | bellard | int idx;
|
848 | dbda808a | bellard | |
849 | 03274d44 | Scott Wood | addr += 0x10f0;
|
850 | 03274d44 | Scott Wood | |
851 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
852 | 4c4f0e48 | Scott Wood | __func__, addr, val); |
853 | af7e9e74 | Alexander Graf | if (addr & 0xF) { |
854 | dbda808a | bellard | return;
|
855 | af7e9e74 | Alexander Graf | } |
856 | c38c0b8a | Alexander Graf | |
857 | 03274d44 | Scott Wood | if (addr == 0x10f0) { |
858 | be7c236f | Scott Wood | /* TFRR */
|
859 | be7c236f | Scott Wood | opp->tfrr = val; |
860 | c38c0b8a | Alexander Graf | return;
|
861 | c38c0b8a | Alexander Graf | } |
862 | 03274d44 | Scott Wood | |
863 | 03274d44 | Scott Wood | idx = (addr >> 6) & 0x3; |
864 | 03274d44 | Scott Wood | addr = addr & 0x30;
|
865 | 03274d44 | Scott Wood | |
866 | c38c0b8a | Alexander Graf | switch (addr & 0x30) { |
867 | be7c236f | Scott Wood | case 0x00: /* TCCR */ |
868 | dbda808a | bellard | break;
|
869 | be7c236f | Scott Wood | case 0x10: /* TBCR */ |
870 | be7c236f | Scott Wood | if ((opp->timers[idx].tccr & TCCR_TOG) != 0 && |
871 | be7c236f | Scott Wood | (val & TBCR_CI) == 0 &&
|
872 | be7c236f | Scott Wood | (opp->timers[idx].tbcr & TBCR_CI) != 0) {
|
873 | be7c236f | Scott Wood | opp->timers[idx].tccr &= ~TCCR_TOG; |
874 | 71c6cacb | Scott Wood | } |
875 | be7c236f | Scott Wood | opp->timers[idx].tbcr = val; |
876 | 060fbfe1 | Aurelien Jarno | break;
|
877 | be7c236f | Scott Wood | case 0x20: /* TVPR */ |
878 | be7c236f | Scott Wood | write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val); |
879 | 060fbfe1 | Aurelien Jarno | break;
|
880 | be7c236f | Scott Wood | case 0x30: /* TDR */ |
881 | be7c236f | Scott Wood | write_IRQreg_idr(opp, opp->irq_tim0 + idx, val); |
882 | 060fbfe1 | Aurelien Jarno | break;
|
883 | dbda808a | bellard | } |
884 | dbda808a | bellard | } |
885 | dbda808a | bellard | |
886 | 6d544ee8 | Alexander Graf | static uint64_t openpic_tmr_read(void *opaque, hwaddr addr, unsigned len) |
887 | dbda808a | bellard | { |
888 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
889 | c38c0b8a | Alexander Graf | uint32_t retval = -1;
|
890 | dbda808a | bellard | int idx;
|
891 | dbda808a | bellard | |
892 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
893 | c38c0b8a | Alexander Graf | if (addr & 0xF) { |
894 | c38c0b8a | Alexander Graf | goto out;
|
895 | c38c0b8a | Alexander Graf | } |
896 | c38c0b8a | Alexander Graf | idx = (addr >> 6) & 0x3; |
897 | c38c0b8a | Alexander Graf | if (addr == 0x0) { |
898 | be7c236f | Scott Wood | /* TFRR */
|
899 | be7c236f | Scott Wood | retval = opp->tfrr; |
900 | c38c0b8a | Alexander Graf | goto out;
|
901 | c38c0b8a | Alexander Graf | } |
902 | c38c0b8a | Alexander Graf | switch (addr & 0x30) { |
903 | be7c236f | Scott Wood | case 0x00: /* TCCR */ |
904 | be7c236f | Scott Wood | retval = opp->timers[idx].tccr; |
905 | dbda808a | bellard | break;
|
906 | be7c236f | Scott Wood | case 0x10: /* TBCR */ |
907 | be7c236f | Scott Wood | retval = opp->timers[idx].tbcr; |
908 | 060fbfe1 | Aurelien Jarno | break;
|
909 | be7c236f | Scott Wood | case 0x20: /* TIPV */ |
910 | be7c236f | Scott Wood | retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx); |
911 | 060fbfe1 | Aurelien Jarno | break;
|
912 | c38c0b8a | Alexander Graf | case 0x30: /* TIDE (TIDR) */ |
913 | be7c236f | Scott Wood | retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx); |
914 | 060fbfe1 | Aurelien Jarno | break;
|
915 | dbda808a | bellard | } |
916 | c38c0b8a | Alexander Graf | |
917 | c38c0b8a | Alexander Graf | out:
|
918 | 4c4f0e48 | Scott Wood | DPRINTF("%s: => 0x%08x\n", __func__, retval);
|
919 | dbda808a | bellard | |
920 | dbda808a | bellard | return retval;
|
921 | dbda808a | bellard | } |
922 | dbda808a | bellard | |
923 | b9b2aaa3 | Alexander Graf | static void openpic_src_write(void *opaque, hwaddr addr, uint64_t val, |
924 | b9b2aaa3 | Alexander Graf | unsigned len)
|
925 | dbda808a | bellard | { |
926 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
927 | dbda808a | bellard | int idx;
|
928 | dbda808a | bellard | |
929 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n", |
930 | 4c4f0e48 | Scott Wood | __func__, addr, val); |
931 | e0dfe5b1 | Scott Wood | |
932 | e0dfe5b1 | Scott Wood | addr = addr & 0xffff;
|
933 | dbda808a | bellard | idx = addr >> 5;
|
934 | e0dfe5b1 | Scott Wood | |
935 | e0dfe5b1 | Scott Wood | switch (addr & 0x1f) { |
936 | e0dfe5b1 | Scott Wood | case 0x00: |
937 | be7c236f | Scott Wood | write_IRQreg_ivpr(opp, idx, val); |
938 | e0dfe5b1 | Scott Wood | break;
|
939 | e0dfe5b1 | Scott Wood | case 0x10: |
940 | e0dfe5b1 | Scott Wood | write_IRQreg_idr(opp, idx, val); |
941 | e0dfe5b1 | Scott Wood | break;
|
942 | e0dfe5b1 | Scott Wood | case 0x18: |
943 | e0dfe5b1 | Scott Wood | write_IRQreg_ilr(opp, idx, val); |
944 | e0dfe5b1 | Scott Wood | break;
|
945 | dbda808a | bellard | } |
946 | dbda808a | bellard | } |
947 | dbda808a | bellard | |
948 | b9b2aaa3 | Alexander Graf | static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) |
949 | dbda808a | bellard | { |
950 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
951 | dbda808a | bellard | uint32_t retval; |
952 | dbda808a | bellard | int idx;
|
953 | dbda808a | bellard | |
954 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
955 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
956 | e0dfe5b1 | Scott Wood | |
957 | e0dfe5b1 | Scott Wood | addr = addr & 0xffff;
|
958 | dbda808a | bellard | idx = addr >> 5;
|
959 | e0dfe5b1 | Scott Wood | |
960 | e0dfe5b1 | Scott Wood | switch (addr & 0x1f) { |
961 | e0dfe5b1 | Scott Wood | case 0x00: |
962 | be7c236f | Scott Wood | retval = read_IRQreg_ivpr(opp, idx); |
963 | e0dfe5b1 | Scott Wood | break;
|
964 | e0dfe5b1 | Scott Wood | case 0x10: |
965 | e0dfe5b1 | Scott Wood | retval = read_IRQreg_idr(opp, idx); |
966 | e0dfe5b1 | Scott Wood | break;
|
967 | e0dfe5b1 | Scott Wood | case 0x18: |
968 | e0dfe5b1 | Scott Wood | retval = read_IRQreg_ilr(opp, idx); |
969 | e0dfe5b1 | Scott Wood | break;
|
970 | dbda808a | bellard | } |
971 | dbda808a | bellard | |
972 | e0dfe5b1 | Scott Wood | DPRINTF("%s: => 0x%08x\n", __func__, retval);
|
973 | dbda808a | bellard | return retval;
|
974 | dbda808a | bellard | } |
975 | dbda808a | bellard | |
976 | 732aa6ec | Alexander Graf | static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val, |
977 | 732aa6ec | Alexander Graf | unsigned size)
|
978 | 732aa6ec | Alexander Graf | { |
979 | 732aa6ec | Alexander Graf | OpenPICState *opp = opaque; |
980 | 732aa6ec | Alexander Graf | int idx = opp->irq_msi;
|
981 | 732aa6ec | Alexander Graf | int srs, ibs;
|
982 | 732aa6ec | Alexander Graf | |
983 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", |
984 | 4c4f0e48 | Scott Wood | __func__, addr, val); |
985 | 732aa6ec | Alexander Graf | if (addr & 0xF) { |
986 | 732aa6ec | Alexander Graf | return;
|
987 | 732aa6ec | Alexander Graf | } |
988 | 732aa6ec | Alexander Graf | |
989 | 732aa6ec | Alexander Graf | switch (addr) {
|
990 | 732aa6ec | Alexander Graf | case MSIIR_OFFSET:
|
991 | 732aa6ec | Alexander Graf | srs = val >> MSIIR_SRS_SHIFT; |
992 | 732aa6ec | Alexander Graf | idx += srs; |
993 | 732aa6ec | Alexander Graf | ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT; |
994 | 732aa6ec | Alexander Graf | opp->msi[srs].msir |= 1 << ibs;
|
995 | 732aa6ec | Alexander Graf | openpic_set_irq(opp, idx, 1);
|
996 | 732aa6ec | Alexander Graf | break;
|
997 | 732aa6ec | Alexander Graf | default:
|
998 | 732aa6ec | Alexander Graf | /* most registers are read-only, thus ignored */
|
999 | 732aa6ec | Alexander Graf | break;
|
1000 | 732aa6ec | Alexander Graf | } |
1001 | 732aa6ec | Alexander Graf | } |
1002 | 732aa6ec | Alexander Graf | |
1003 | 732aa6ec | Alexander Graf | static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size) |
1004 | 732aa6ec | Alexander Graf | { |
1005 | 732aa6ec | Alexander Graf | OpenPICState *opp = opaque; |
1006 | 732aa6ec | Alexander Graf | uint64_t r = 0;
|
1007 | 732aa6ec | Alexander Graf | int i, srs;
|
1008 | 732aa6ec | Alexander Graf | |
1009 | 4c4f0e48 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
1010 | 732aa6ec | Alexander Graf | if (addr & 0xF) { |
1011 | 732aa6ec | Alexander Graf | return -1; |
1012 | 732aa6ec | Alexander Graf | } |
1013 | 732aa6ec | Alexander Graf | |
1014 | 732aa6ec | Alexander Graf | srs = addr >> 4;
|
1015 | 732aa6ec | Alexander Graf | |
1016 | 732aa6ec | Alexander Graf | switch (addr) {
|
1017 | 732aa6ec | Alexander Graf | case 0x00: |
1018 | 732aa6ec | Alexander Graf | case 0x10: |
1019 | 732aa6ec | Alexander Graf | case 0x20: |
1020 | 732aa6ec | Alexander Graf | case 0x30: |
1021 | 732aa6ec | Alexander Graf | case 0x40: |
1022 | 732aa6ec | Alexander Graf | case 0x50: |
1023 | 732aa6ec | Alexander Graf | case 0x60: |
1024 | 732aa6ec | Alexander Graf | case 0x70: /* MSIRs */ |
1025 | 732aa6ec | Alexander Graf | r = opp->msi[srs].msir; |
1026 | 732aa6ec | Alexander Graf | /* Clear on read */
|
1027 | 732aa6ec | Alexander Graf | opp->msi[srs].msir = 0;
|
1028 | e99fd8af | Scott Wood | openpic_set_irq(opp, opp->irq_msi + srs, 0);
|
1029 | 732aa6ec | Alexander Graf | break;
|
1030 | 732aa6ec | Alexander Graf | case 0x120: /* MSISR */ |
1031 | 732aa6ec | Alexander Graf | for (i = 0; i < MAX_MSI; i++) { |
1032 | 732aa6ec | Alexander Graf | r |= (opp->msi[i].msir ? 1 : 0) << i; |
1033 | 732aa6ec | Alexander Graf | } |
1034 | 732aa6ec | Alexander Graf | break;
|
1035 | 732aa6ec | Alexander Graf | } |
1036 | 732aa6ec | Alexander Graf | |
1037 | 732aa6ec | Alexander Graf | return r;
|
1038 | 732aa6ec | Alexander Graf | } |
1039 | 732aa6ec | Alexander Graf | |
1040 | e0dfe5b1 | Scott Wood | static uint64_t openpic_summary_read(void *opaque, hwaddr addr, unsigned size) |
1041 | e0dfe5b1 | Scott Wood | { |
1042 | e0dfe5b1 | Scott Wood | uint64_t r = 0;
|
1043 | e0dfe5b1 | Scott Wood | |
1044 | e0dfe5b1 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr); |
1045 | e0dfe5b1 | Scott Wood | |
1046 | e0dfe5b1 | Scott Wood | /* TODO: EISR/EIMR */
|
1047 | e0dfe5b1 | Scott Wood | |
1048 | e0dfe5b1 | Scott Wood | return r;
|
1049 | e0dfe5b1 | Scott Wood | } |
1050 | e0dfe5b1 | Scott Wood | |
1051 | e0dfe5b1 | Scott Wood | static void openpic_summary_write(void *opaque, hwaddr addr, uint64_t val, |
1052 | e0dfe5b1 | Scott Wood | unsigned size)
|
1053 | e0dfe5b1 | Scott Wood | { |
1054 | e0dfe5b1 | Scott Wood | DPRINTF("%s: addr %#" HWADDR_PRIx " <= 0x%08" PRIx64 "\n", |
1055 | e0dfe5b1 | Scott Wood | __func__, addr, val); |
1056 | e0dfe5b1 | Scott Wood | |
1057 | e0dfe5b1 | Scott Wood | /* TODO: EISR/EIMR */
|
1058 | e0dfe5b1 | Scott Wood | } |
1059 | e0dfe5b1 | Scott Wood | |
1060 | a8170e5e | Avi Kivity | static void openpic_cpu_write_internal(void *opaque, hwaddr addr, |
1061 | 704c7e5d | Alexander Graf | uint32_t val, int idx)
|
1062 | dbda808a | bellard | { |
1063 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
1064 | af7e9e74 | Alexander Graf | IRQSource *src; |
1065 | af7e9e74 | Alexander Graf | IRQDest *dst; |
1066 | 704c7e5d | Alexander Graf | int s_IRQ, n_IRQ;
|
1067 | dbda808a | bellard | |
1068 | 4c4f0e48 | Scott Wood | DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx " <= 0x%08x\n", __func__, idx, |
1069 | 704c7e5d | Alexander Graf | addr, val); |
1070 | c3203fa5 | Scott Wood | |
1071 | c3203fa5 | Scott Wood | if (idx < 0) { |
1072 | dbda808a | bellard | return;
|
1073 | c3203fa5 | Scott Wood | } |
1074 | c3203fa5 | Scott Wood | |
1075 | af7e9e74 | Alexander Graf | if (addr & 0xF) { |
1076 | dbda808a | bellard | return;
|
1077 | af7e9e74 | Alexander Graf | } |
1078 | dbda808a | bellard | dst = &opp->dst[idx]; |
1079 | dbda808a | bellard | addr &= 0xFF0;
|
1080 | dbda808a | bellard | switch (addr) {
|
1081 | 704c7e5d | Alexander Graf | case 0x40: /* IPIDR */ |
1082 | dbda808a | bellard | case 0x50: |
1083 | dbda808a | bellard | case 0x60: |
1084 | dbda808a | bellard | case 0x70: |
1085 | dbda808a | bellard | idx = (addr - 0x40) >> 4; |
1086 | a675155e | Alexander Graf | /* we use IDE as mask which CPUs to deliver the IPI to still. */
|
1087 | f40c360c | Scott Wood | opp->src[opp->irq_ipi0 + idx].destmask |= val; |
1088 | b7169916 | aurel32 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
|
1089 | b7169916 | aurel32 | openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
|
1090 | dbda808a | bellard | break;
|
1091 | be7c236f | Scott Wood | case 0x80: /* CTPR */ |
1092 | be7c236f | Scott Wood | dst->ctpr = val & 0x0000000F;
|
1093 | 9f1d4b1d | Scott Wood | |
1094 | 9f1d4b1d | Scott Wood | DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
|
1095 | 9f1d4b1d | Scott Wood | __func__, idx, dst->ctpr, dst->raised.priority, |
1096 | 9f1d4b1d | Scott Wood | dst->servicing.priority); |
1097 | 9f1d4b1d | Scott Wood | |
1098 | 9f1d4b1d | Scott Wood | if (dst->raised.priority <= dst->ctpr) {
|
1099 | 9f1d4b1d | Scott Wood | DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
|
1100 | 9f1d4b1d | Scott Wood | __func__, idx); |
1101 | 9f1d4b1d | Scott Wood | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
1102 | 9f1d4b1d | Scott Wood | } else if (dst->raised.priority > dst->servicing.priority) { |
1103 | 9f1d4b1d | Scott Wood | DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
|
1104 | 9f1d4b1d | Scott Wood | __func__, idx, dst->raised.next); |
1105 | 9f1d4b1d | Scott Wood | qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); |
1106 | 9f1d4b1d | Scott Wood | } |
1107 | 9f1d4b1d | Scott Wood | |
1108 | 060fbfe1 | Aurelien Jarno | break;
|
1109 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
1110 | 060fbfe1 | Aurelien Jarno | /* Read-only register */
|
1111 | 060fbfe1 | Aurelien Jarno | break;
|
1112 | be7c236f | Scott Wood | case 0xA0: /* IACK */ |
1113 | 060fbfe1 | Aurelien Jarno | /* Read-only register */
|
1114 | 060fbfe1 | Aurelien Jarno | break;
|
1115 | be7c236f | Scott Wood | case 0xB0: /* EOI */ |
1116 | be7c236f | Scott Wood | DPRINTF("EOI\n");
|
1117 | 060fbfe1 | Aurelien Jarno | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
1118 | 65b9d0d5 | Scott Wood | |
1119 | 65b9d0d5 | Scott Wood | if (s_IRQ < 0) { |
1120 | 65b9d0d5 | Scott Wood | DPRINTF("%s: EOI with no interrupt in service\n", __func__);
|
1121 | 65b9d0d5 | Scott Wood | break;
|
1122 | 65b9d0d5 | Scott Wood | } |
1123 | 65b9d0d5 | Scott Wood | |
1124 | 060fbfe1 | Aurelien Jarno | IRQ_resetbit(&dst->servicing, s_IRQ); |
1125 | 060fbfe1 | Aurelien Jarno | /* Set up next servicing IRQ */
|
1126 | 060fbfe1 | Aurelien Jarno | s_IRQ = IRQ_get_next(opp, &dst->servicing); |
1127 | e9df014c | j_mayer | /* Check queued interrupts. */
|
1128 | e9df014c | j_mayer | n_IRQ = IRQ_get_next(opp, &dst->raised); |
1129 | e9df014c | j_mayer | src = &opp->src[n_IRQ]; |
1130 | e9df014c | j_mayer | if (n_IRQ != -1 && |
1131 | e9df014c | j_mayer | (s_IRQ == -1 ||
|
1132 | be7c236f | Scott Wood | IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) { |
1133 | e9df014c | j_mayer | DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
|
1134 | e9df014c | j_mayer | idx, n_IRQ); |
1135 | 5e22c276 | Scott Wood | qemu_irq_raise(opp->dst[idx].irqs[OPENPIC_OUTPUT_INT]); |
1136 | e9df014c | j_mayer | } |
1137 | 060fbfe1 | Aurelien Jarno | break;
|
1138 | dbda808a | bellard | default:
|
1139 | dbda808a | bellard | break;
|
1140 | dbda808a | bellard | } |
1141 | dbda808a | bellard | } |
1142 | dbda808a | bellard | |
1143 | b9b2aaa3 | Alexander Graf | static void openpic_cpu_write(void *opaque, hwaddr addr, uint64_t val, |
1144 | b9b2aaa3 | Alexander Graf | unsigned len)
|
1145 | 704c7e5d | Alexander Graf | { |
1146 | 704c7e5d | Alexander Graf | openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12); |
1147 | 704c7e5d | Alexander Graf | } |
1148 | 704c7e5d | Alexander Graf | |
1149 | a898a8fc | Scott Wood | |
1150 | a898a8fc | Scott Wood | static uint32_t openpic_iack(OpenPICState *opp, IRQDest *dst, int cpu) |
1151 | a898a8fc | Scott Wood | { |
1152 | a898a8fc | Scott Wood | IRQSource *src; |
1153 | a898a8fc | Scott Wood | int retval, irq;
|
1154 | a898a8fc | Scott Wood | |
1155 | a898a8fc | Scott Wood | DPRINTF("Lower OpenPIC INT output\n");
|
1156 | a898a8fc | Scott Wood | qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
1157 | a898a8fc | Scott Wood | |
1158 | a898a8fc | Scott Wood | irq = IRQ_get_next(opp, &dst->raised); |
1159 | a898a8fc | Scott Wood | DPRINTF("IACK: irq=%d\n", irq);
|
1160 | a898a8fc | Scott Wood | |
1161 | a898a8fc | Scott Wood | if (irq == -1) { |
1162 | a898a8fc | Scott Wood | /* No more interrupt pending */
|
1163 | a898a8fc | Scott Wood | return opp->spve;
|
1164 | a898a8fc | Scott Wood | } |
1165 | a898a8fc | Scott Wood | |
1166 | a898a8fc | Scott Wood | src = &opp->src[irq]; |
1167 | a898a8fc | Scott Wood | if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
|
1168 | a898a8fc | Scott Wood | !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) { |
1169 | 9f1d4b1d | Scott Wood | fprintf(stderr, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
|
1170 | 9f1d4b1d | Scott Wood | __func__, irq, dst->ctpr, src->ivpr); |
1171 | 9f1d4b1d | Scott Wood | openpic_update_irq(opp, irq); |
1172 | a898a8fc | Scott Wood | retval = opp->spve; |
1173 | a898a8fc | Scott Wood | } else {
|
1174 | a898a8fc | Scott Wood | /* IRQ enter servicing state */
|
1175 | a898a8fc | Scott Wood | IRQ_setbit(&dst->servicing, irq); |
1176 | a898a8fc | Scott Wood | retval = IVPR_VECTOR(opp, src->ivpr); |
1177 | a898a8fc | Scott Wood | } |
1178 | 9f1d4b1d | Scott Wood | |
1179 | a898a8fc | Scott Wood | if (!src->level) {
|
1180 | a898a8fc | Scott Wood | /* edge-sensitive IRQ */
|
1181 | a898a8fc | Scott Wood | src->ivpr &= ~IVPR_ACTIVITY_MASK; |
1182 | a898a8fc | Scott Wood | src->pending = 0;
|
1183 | 9f1d4b1d | Scott Wood | IRQ_resetbit(&dst->raised, irq); |
1184 | a898a8fc | Scott Wood | } |
1185 | a898a8fc | Scott Wood | |
1186 | 8935a442 | Scott Wood | if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) {
|
1187 | f40c360c | Scott Wood | src->destmask &= ~(1 << cpu);
|
1188 | f40c360c | Scott Wood | if (src->destmask && !src->level) {
|
1189 | a898a8fc | Scott Wood | /* trigger on CPUs that didn't know about it yet */
|
1190 | a898a8fc | Scott Wood | openpic_set_irq(opp, irq, 1);
|
1191 | a898a8fc | Scott Wood | openpic_set_irq(opp, irq, 0);
|
1192 | a898a8fc | Scott Wood | /* if all CPUs knew about it, set active bit again */
|
1193 | a898a8fc | Scott Wood | src->ivpr |= IVPR_ACTIVITY_MASK; |
1194 | a898a8fc | Scott Wood | } |
1195 | a898a8fc | Scott Wood | } |
1196 | a898a8fc | Scott Wood | |
1197 | a898a8fc | Scott Wood | return retval;
|
1198 | a898a8fc | Scott Wood | } |
1199 | a898a8fc | Scott Wood | |
1200 | a8170e5e | Avi Kivity | static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, |
1201 | 704c7e5d | Alexander Graf | int idx)
|
1202 | dbda808a | bellard | { |
1203 | 6d544ee8 | Alexander Graf | OpenPICState *opp = opaque; |
1204 | af7e9e74 | Alexander Graf | IRQDest *dst; |
1205 | dbda808a | bellard | uint32_t retval; |
1206 | 3b46e624 | ths | |
1207 | 4c4f0e48 | Scott Wood | DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx "\n", __func__, idx, addr); |
1208 | dbda808a | bellard | retval = 0xFFFFFFFF;
|
1209 | c3203fa5 | Scott Wood | |
1210 | c3203fa5 | Scott Wood | if (idx < 0) { |
1211 | c3203fa5 | Scott Wood | return retval;
|
1212 | c3203fa5 | Scott Wood | } |
1213 | c3203fa5 | Scott Wood | |
1214 | af7e9e74 | Alexander Graf | if (addr & 0xF) { |
1215 | dbda808a | bellard | return retval;
|
1216 | af7e9e74 | Alexander Graf | } |
1217 | dbda808a | bellard | dst = &opp->dst[idx]; |
1218 | dbda808a | bellard | addr &= 0xFF0;
|
1219 | dbda808a | bellard | switch (addr) {
|
1220 | be7c236f | Scott Wood | case 0x80: /* CTPR */ |
1221 | be7c236f | Scott Wood | retval = dst->ctpr; |
1222 | 060fbfe1 | Aurelien Jarno | break;
|
1223 | dbda808a | bellard | case 0x90: /* WHOAMI */ |
1224 | 060fbfe1 | Aurelien Jarno | retval = idx; |
1225 | 060fbfe1 | Aurelien Jarno | break;
|
1226 | be7c236f | Scott Wood | case 0xA0: /* IACK */ |
1227 | a898a8fc | Scott Wood | retval = openpic_iack(opp, dst, idx); |
1228 | 060fbfe1 | Aurelien Jarno | break;
|
1229 | be7c236f | Scott Wood | case 0xB0: /* EOI */ |
1230 | 060fbfe1 | Aurelien Jarno | retval = 0;
|
1231 | 060fbfe1 | Aurelien Jarno | break;
|
1232 | dbda808a | bellard | default:
|
1233 | dbda808a | bellard | break;
|
1234 | dbda808a | bellard | } |
1235 | 4c4f0e48 | Scott Wood | DPRINTF("%s: => 0x%08x\n", __func__, retval);
|
1236 | dbda808a | bellard | |
1237 | dbda808a | bellard | return retval;
|
1238 | dbda808a | bellard | } |
1239 | dbda808a | bellard | |
1240 | b9b2aaa3 | Alexander Graf | static uint64_t openpic_cpu_read(void *opaque, hwaddr addr, unsigned len) |
1241 | 704c7e5d | Alexander Graf | { |
1242 | 704c7e5d | Alexander Graf | return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12); |
1243 | 704c7e5d | Alexander Graf | } |
1244 | 704c7e5d | Alexander Graf | |
1245 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_glb_ops_le = { |
1246 | 780d16b7 | Alexander Graf | .write = openpic_gbl_write, |
1247 | 780d16b7 | Alexander Graf | .read = openpic_gbl_read, |
1248 | 780d16b7 | Alexander Graf | .endianness = DEVICE_LITTLE_ENDIAN, |
1249 | 780d16b7 | Alexander Graf | .impl = { |
1250 | 780d16b7 | Alexander Graf | .min_access_size = 4,
|
1251 | 780d16b7 | Alexander Graf | .max_access_size = 4,
|
1252 | 780d16b7 | Alexander Graf | }, |
1253 | 780d16b7 | Alexander Graf | }; |
1254 | dbda808a | bellard | |
1255 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_glb_ops_be = { |
1256 | 35732cb4 | Alexander Graf | .write = openpic_gbl_write, |
1257 | 35732cb4 | Alexander Graf | .read = openpic_gbl_read, |
1258 | 35732cb4 | Alexander Graf | .endianness = DEVICE_BIG_ENDIAN, |
1259 | 35732cb4 | Alexander Graf | .impl = { |
1260 | 35732cb4 | Alexander Graf | .min_access_size = 4,
|
1261 | 35732cb4 | Alexander Graf | .max_access_size = 4,
|
1262 | 35732cb4 | Alexander Graf | }, |
1263 | 35732cb4 | Alexander Graf | }; |
1264 | 35732cb4 | Alexander Graf | |
1265 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_tmr_ops_le = { |
1266 | 6d544ee8 | Alexander Graf | .write = openpic_tmr_write, |
1267 | 6d544ee8 | Alexander Graf | .read = openpic_tmr_read, |
1268 | 780d16b7 | Alexander Graf | .endianness = DEVICE_LITTLE_ENDIAN, |
1269 | 780d16b7 | Alexander Graf | .impl = { |
1270 | 780d16b7 | Alexander Graf | .min_access_size = 4,
|
1271 | 780d16b7 | Alexander Graf | .max_access_size = 4,
|
1272 | 780d16b7 | Alexander Graf | }, |
1273 | 780d16b7 | Alexander Graf | }; |
1274 | dbda808a | bellard | |
1275 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_tmr_ops_be = { |
1276 | 6d544ee8 | Alexander Graf | .write = openpic_tmr_write, |
1277 | 6d544ee8 | Alexander Graf | .read = openpic_tmr_read, |
1278 | 35732cb4 | Alexander Graf | .endianness = DEVICE_BIG_ENDIAN, |
1279 | 35732cb4 | Alexander Graf | .impl = { |
1280 | 35732cb4 | Alexander Graf | .min_access_size = 4,
|
1281 | 35732cb4 | Alexander Graf | .max_access_size = 4,
|
1282 | 35732cb4 | Alexander Graf | }, |
1283 | 35732cb4 | Alexander Graf | }; |
1284 | 35732cb4 | Alexander Graf | |
1285 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_cpu_ops_le = { |
1286 | 780d16b7 | Alexander Graf | .write = openpic_cpu_write, |
1287 | 780d16b7 | Alexander Graf | .read = openpic_cpu_read, |
1288 | 780d16b7 | Alexander Graf | .endianness = DEVICE_LITTLE_ENDIAN, |
1289 | 780d16b7 | Alexander Graf | .impl = { |
1290 | 780d16b7 | Alexander Graf | .min_access_size = 4,
|
1291 | 780d16b7 | Alexander Graf | .max_access_size = 4,
|
1292 | 780d16b7 | Alexander Graf | }, |
1293 | 780d16b7 | Alexander Graf | }; |
1294 | dbda808a | bellard | |
1295 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_cpu_ops_be = { |
1296 | 35732cb4 | Alexander Graf | .write = openpic_cpu_write, |
1297 | 35732cb4 | Alexander Graf | .read = openpic_cpu_read, |
1298 | 35732cb4 | Alexander Graf | .endianness = DEVICE_BIG_ENDIAN, |
1299 | 35732cb4 | Alexander Graf | .impl = { |
1300 | 35732cb4 | Alexander Graf | .min_access_size = 4,
|
1301 | 35732cb4 | Alexander Graf | .max_access_size = 4,
|
1302 | 35732cb4 | Alexander Graf | }, |
1303 | 35732cb4 | Alexander Graf | }; |
1304 | 35732cb4 | Alexander Graf | |
1305 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_src_ops_le = { |
1306 | 780d16b7 | Alexander Graf | .write = openpic_src_write, |
1307 | 780d16b7 | Alexander Graf | .read = openpic_src_read, |
1308 | 23c5e4ca | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
1309 | b9b2aaa3 | Alexander Graf | .impl = { |
1310 | b9b2aaa3 | Alexander Graf | .min_access_size = 4,
|
1311 | b9b2aaa3 | Alexander Graf | .max_access_size = 4,
|
1312 | b9b2aaa3 | Alexander Graf | }, |
1313 | 23c5e4ca | Avi Kivity | }; |
1314 | 23c5e4ca | Avi Kivity | |
1315 | 35732cb4 | Alexander Graf | static const MemoryRegionOps openpic_src_ops_be = { |
1316 | 35732cb4 | Alexander Graf | .write = openpic_src_write, |
1317 | 35732cb4 | Alexander Graf | .read = openpic_src_read, |
1318 | 35732cb4 | Alexander Graf | .endianness = DEVICE_BIG_ENDIAN, |
1319 | 35732cb4 | Alexander Graf | .impl = { |
1320 | 35732cb4 | Alexander Graf | .min_access_size = 4,
|
1321 | 35732cb4 | Alexander Graf | .max_access_size = 4,
|
1322 | 35732cb4 | Alexander Graf | }, |
1323 | 35732cb4 | Alexander Graf | }; |
1324 | 35732cb4 | Alexander Graf | |
1325 | e0dfe5b1 | Scott Wood | static const MemoryRegionOps openpic_msi_ops_be = { |
1326 | 732aa6ec | Alexander Graf | .read = openpic_msi_read, |
1327 | 732aa6ec | Alexander Graf | .write = openpic_msi_write, |
1328 | e0dfe5b1 | Scott Wood | .endianness = DEVICE_BIG_ENDIAN, |
1329 | 732aa6ec | Alexander Graf | .impl = { |
1330 | 732aa6ec | Alexander Graf | .min_access_size = 4,
|
1331 | 732aa6ec | Alexander Graf | .max_access_size = 4,
|
1332 | 732aa6ec | Alexander Graf | }, |
1333 | 732aa6ec | Alexander Graf | }; |
1334 | 732aa6ec | Alexander Graf | |
1335 | e0dfe5b1 | Scott Wood | static const MemoryRegionOps openpic_summary_ops_be = { |
1336 | e0dfe5b1 | Scott Wood | .read = openpic_summary_read, |
1337 | e0dfe5b1 | Scott Wood | .write = openpic_summary_write, |
1338 | 732aa6ec | Alexander Graf | .endianness = DEVICE_BIG_ENDIAN, |
1339 | 732aa6ec | Alexander Graf | .impl = { |
1340 | 732aa6ec | Alexander Graf | .min_access_size = 4,
|
1341 | 732aa6ec | Alexander Graf | .max_access_size = 4,
|
1342 | 732aa6ec | Alexander Graf | }, |
1343 | 732aa6ec | Alexander Graf | }; |
1344 | 732aa6ec | Alexander Graf | |
1345 | af7e9e74 | Alexander Graf | static void openpic_save_IRQ_queue(QEMUFile* f, IRQQueue *q) |
1346 | 67b55785 | blueswir1 | { |
1347 | 67b55785 | blueswir1 | unsigned int i; |
1348 | 67b55785 | blueswir1 | |
1349 | e69a17f6 | Scott Wood | for (i = 0; i < ARRAY_SIZE(q->queue); i++) { |
1350 | e69a17f6 | Scott Wood | /* Always put the lower half of a 64-bit long first, in case we
|
1351 | e69a17f6 | Scott Wood | * restore on a 32-bit host. The least significant bits correspond
|
1352 | e69a17f6 | Scott Wood | * to lower IRQ numbers in the bitmap.
|
1353 | e69a17f6 | Scott Wood | */
|
1354 | e69a17f6 | Scott Wood | qemu_put_be32(f, (uint32_t)q->queue[i]); |
1355 | e69a17f6 | Scott Wood | #if LONG_MAX > 0x7FFFFFFF |
1356 | e69a17f6 | Scott Wood | qemu_put_be32(f, (uint32_t)(q->queue[i] >> 32));
|
1357 | e69a17f6 | Scott Wood | #endif
|
1358 | e69a17f6 | Scott Wood | } |
1359 | 67b55785 | blueswir1 | |
1360 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->next); |
1361 | 67b55785 | blueswir1 | qemu_put_sbe32s(f, &q->priority); |
1362 | 67b55785 | blueswir1 | } |
1363 | 67b55785 | blueswir1 | |
1364 | 67b55785 | blueswir1 | static void openpic_save(QEMUFile* f, void *opaque) |
1365 | 67b55785 | blueswir1 | { |
1366 | 6d544ee8 | Alexander Graf | OpenPICState *opp = (OpenPICState *)opaque; |
1367 | 67b55785 | blueswir1 | unsigned int i; |
1368 | 67b55785 | blueswir1 | |
1369 | be7c236f | Scott Wood | qemu_put_be32s(f, &opp->gcr); |
1370 | be7c236f | Scott Wood | qemu_put_be32s(f, &opp->vir); |
1371 | be7c236f | Scott Wood | qemu_put_be32s(f, &opp->pir); |
1372 | 67b55785 | blueswir1 | qemu_put_be32s(f, &opp->spve); |
1373 | be7c236f | Scott Wood | qemu_put_be32s(f, &opp->tfrr); |
1374 | 67b55785 | blueswir1 | |
1375 | d0b72631 | Alexander Graf | qemu_put_be32s(f, &opp->nb_cpus); |
1376 | b7169916 | aurel32 | |
1377 | b7169916 | aurel32 | for (i = 0; i < opp->nb_cpus; i++) { |
1378 | eb438427 | Scott Wood | qemu_put_sbe32s(f, &opp->dst[i].ctpr); |
1379 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].raised); |
1380 | 67b55785 | blueswir1 | openpic_save_IRQ_queue(f, &opp->dst[i].servicing); |
1381 | 9f1d4b1d | Scott Wood | qemu_put_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, |
1382 | 9f1d4b1d | Scott Wood | sizeof(opp->dst[i].outputs_active));
|
1383 | 67b55785 | blueswir1 | } |
1384 | 67b55785 | blueswir1 | |
1385 | 8935a442 | Scott Wood | for (i = 0; i < OPENPIC_MAX_TMR; i++) { |
1386 | be7c236f | Scott Wood | qemu_put_be32s(f, &opp->timers[i].tccr); |
1387 | be7c236f | Scott Wood | qemu_put_be32s(f, &opp->timers[i].tbcr); |
1388 | 67b55785 | blueswir1 | } |
1389 | 5e22c276 | Scott Wood | |
1390 | 5e22c276 | Scott Wood | for (i = 0; i < opp->max_irq; i++) { |
1391 | 5e22c276 | Scott Wood | qemu_put_be32s(f, &opp->src[i].ivpr); |
1392 | 5e22c276 | Scott Wood | qemu_put_be32s(f, &opp->src[i].idr); |
1393 | f40c360c | Scott Wood | qemu_get_be32s(f, &opp->src[i].destmask); |
1394 | 5e22c276 | Scott Wood | qemu_put_sbe32s(f, &opp->src[i].last_cpu); |
1395 | 5e22c276 | Scott Wood | qemu_put_sbe32s(f, &opp->src[i].pending); |
1396 | 67b55785 | blueswir1 | } |
1397 | 67b55785 | blueswir1 | } |
1398 | 67b55785 | blueswir1 | |
1399 | af7e9e74 | Alexander Graf | static void openpic_load_IRQ_queue(QEMUFile* f, IRQQueue *q) |
1400 | 67b55785 | blueswir1 | { |
1401 | 67b55785 | blueswir1 | unsigned int i; |
1402 | 67b55785 | blueswir1 | |
1403 | e69a17f6 | Scott Wood | for (i = 0; i < ARRAY_SIZE(q->queue); i++) { |
1404 | e69a17f6 | Scott Wood | unsigned long val; |
1405 | e69a17f6 | Scott Wood | |
1406 | e69a17f6 | Scott Wood | val = qemu_get_be32(f); |
1407 | e69a17f6 | Scott Wood | #if LONG_MAX > 0x7FFFFFFF |
1408 | e69a17f6 | Scott Wood | val <<= 32;
|
1409 | e69a17f6 | Scott Wood | val |= qemu_get_be32(f); |
1410 | e69a17f6 | Scott Wood | #endif
|
1411 | e69a17f6 | Scott Wood | |
1412 | e69a17f6 | Scott Wood | q->queue[i] = val; |
1413 | e69a17f6 | Scott Wood | } |
1414 | 67b55785 | blueswir1 | |
1415 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->next); |
1416 | 67b55785 | blueswir1 | qemu_get_sbe32s(f, &q->priority); |
1417 | 67b55785 | blueswir1 | } |
1418 | 67b55785 | blueswir1 | |
1419 | 67b55785 | blueswir1 | static int openpic_load(QEMUFile* f, void *opaque, int version_id) |
1420 | 67b55785 | blueswir1 | { |
1421 | 6d544ee8 | Alexander Graf | OpenPICState *opp = (OpenPICState *)opaque; |
1422 | 67b55785 | blueswir1 | unsigned int i; |
1423 | 67b55785 | blueswir1 | |
1424 | af7e9e74 | Alexander Graf | if (version_id != 1) { |
1425 | 67b55785 | blueswir1 | return -EINVAL;
|
1426 | af7e9e74 | Alexander Graf | } |
1427 | 67b55785 | blueswir1 | |
1428 | be7c236f | Scott Wood | qemu_get_be32s(f, &opp->gcr); |
1429 | be7c236f | Scott Wood | qemu_get_be32s(f, &opp->vir); |
1430 | be7c236f | Scott Wood | qemu_get_be32s(f, &opp->pir); |
1431 | 67b55785 | blueswir1 | qemu_get_be32s(f, &opp->spve); |
1432 | be7c236f | Scott Wood | qemu_get_be32s(f, &opp->tfrr); |
1433 | 67b55785 | blueswir1 | |
1434 | d0b72631 | Alexander Graf | qemu_get_be32s(f, &opp->nb_cpus); |
1435 | b7169916 | aurel32 | |
1436 | b7169916 | aurel32 | for (i = 0; i < opp->nb_cpus; i++) { |
1437 | eb438427 | Scott Wood | qemu_get_sbe32s(f, &opp->dst[i].ctpr); |
1438 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].raised); |
1439 | 67b55785 | blueswir1 | openpic_load_IRQ_queue(f, &opp->dst[i].servicing); |
1440 | 9f1d4b1d | Scott Wood | qemu_get_buffer(f, (uint8_t *)&opp->dst[i].outputs_active, |
1441 | 9f1d4b1d | Scott Wood | sizeof(opp->dst[i].outputs_active));
|
1442 | 67b55785 | blueswir1 | } |
1443 | 67b55785 | blueswir1 | |
1444 | 8935a442 | Scott Wood | for (i = 0; i < OPENPIC_MAX_TMR; i++) { |
1445 | be7c236f | Scott Wood | qemu_get_be32s(f, &opp->timers[i].tccr); |
1446 | be7c236f | Scott Wood | qemu_get_be32s(f, &opp->timers[i].tbcr); |
1447 | 67b55785 | blueswir1 | } |
1448 | 67b55785 | blueswir1 | |
1449 | 5e22c276 | Scott Wood | for (i = 0; i < opp->max_irq; i++) { |
1450 | 5e22c276 | Scott Wood | uint32_t val; |
1451 | 67b55785 | blueswir1 | |
1452 | 5e22c276 | Scott Wood | val = qemu_get_be32(f); |
1453 | 5e22c276 | Scott Wood | write_IRQreg_idr(opp, i, val); |
1454 | 5e22c276 | Scott Wood | val = qemu_get_be32(f); |
1455 | 5e22c276 | Scott Wood | write_IRQreg_ivpr(opp, i, val); |
1456 | 5861a338 | Alexander Graf | |
1457 | 5e22c276 | Scott Wood | qemu_get_be32s(f, &opp->src[i].ivpr); |
1458 | 5e22c276 | Scott Wood | qemu_get_be32s(f, &opp->src[i].idr); |
1459 | f40c360c | Scott Wood | qemu_get_be32s(f, &opp->src[i].destmask); |
1460 | 5e22c276 | Scott Wood | qemu_get_sbe32s(f, &opp->src[i].last_cpu); |
1461 | 5e22c276 | Scott Wood | qemu_get_sbe32s(f, &opp->src[i].pending); |
1462 | 5861a338 | Alexander Graf | } |
1463 | 5e22c276 | Scott Wood | |
1464 | 5e22c276 | Scott Wood | return 0; |
1465 | b7169916 | aurel32 | } |
1466 | b7169916 | aurel32 | |
1467 | af7e9e74 | Alexander Graf | typedef struct MemReg { |
1468 | d0b72631 | Alexander Graf | const char *name; |
1469 | d0b72631 | Alexander Graf | MemoryRegionOps const *ops;
|
1470 | d0b72631 | Alexander Graf | hwaddr start_addr; |
1471 | d0b72631 | Alexander Graf | ram_addr_t size; |
1472 | af7e9e74 | Alexander Graf | } MemReg; |
1473 | d0b72631 | Alexander Graf | |
1474 | e0dfe5b1 | Scott Wood | static void fsl_common_init(OpenPICState *opp) |
1475 | e0dfe5b1 | Scott Wood | { |
1476 | e0dfe5b1 | Scott Wood | int i;
|
1477 | 8935a442 | Scott Wood | int virq = OPENPIC_MAX_SRC;
|
1478 | e0dfe5b1 | Scott Wood | |
1479 | e0dfe5b1 | Scott Wood | opp->vid = VID_REVISION_1_2; |
1480 | e0dfe5b1 | Scott Wood | opp->vir = VIR_GENERIC; |
1481 | e0dfe5b1 | Scott Wood | opp->vector_mask = 0xFFFF;
|
1482 | e0dfe5b1 | Scott Wood | opp->tfrr_reset = 0;
|
1483 | e0dfe5b1 | Scott Wood | opp->ivpr_reset = IVPR_MASK_MASK; |
1484 | e0dfe5b1 | Scott Wood | opp->idr_reset = 1 << 0; |
1485 | 8935a442 | Scott Wood | opp->max_irq = OPENPIC_MAX_IRQ; |
1486 | e0dfe5b1 | Scott Wood | |
1487 | e0dfe5b1 | Scott Wood | opp->irq_ipi0 = virq; |
1488 | 8935a442 | Scott Wood | virq += OPENPIC_MAX_IPI; |
1489 | e0dfe5b1 | Scott Wood | opp->irq_tim0 = virq; |
1490 | 8935a442 | Scott Wood | virq += OPENPIC_MAX_TMR; |
1491 | e0dfe5b1 | Scott Wood | |
1492 | 8935a442 | Scott Wood | assert(virq <= OPENPIC_MAX_IRQ); |
1493 | e0dfe5b1 | Scott Wood | |
1494 | e0dfe5b1 | Scott Wood | opp->irq_msi = 224;
|
1495 | e0dfe5b1 | Scott Wood | |
1496 | e0dfe5b1 | Scott Wood | msi_supported = true;
|
1497 | e0dfe5b1 | Scott Wood | for (i = 0; i < opp->fsl->max_ext; i++) { |
1498 | e0dfe5b1 | Scott Wood | opp->src[i].level = false;
|
1499 | e0dfe5b1 | Scott Wood | } |
1500 | e0dfe5b1 | Scott Wood | |
1501 | e0dfe5b1 | Scott Wood | /* Internal interrupts, including message and MSI */
|
1502 | 8935a442 | Scott Wood | for (i = 16; i < OPENPIC_MAX_SRC; i++) { |
1503 | e0dfe5b1 | Scott Wood | opp->src[i].type = IRQ_TYPE_FSLINT; |
1504 | e0dfe5b1 | Scott Wood | opp->src[i].level = true;
|
1505 | e0dfe5b1 | Scott Wood | } |
1506 | e0dfe5b1 | Scott Wood | |
1507 | e0dfe5b1 | Scott Wood | /* timers and IPIs */
|
1508 | 8935a442 | Scott Wood | for (i = OPENPIC_MAX_SRC; i < virq; i++) {
|
1509 | e0dfe5b1 | Scott Wood | opp->src[i].type = IRQ_TYPE_FSLSPECIAL; |
1510 | e0dfe5b1 | Scott Wood | opp->src[i].level = false;
|
1511 | e0dfe5b1 | Scott Wood | } |
1512 | e0dfe5b1 | Scott Wood | } |
1513 | e0dfe5b1 | Scott Wood | |
1514 | e0dfe5b1 | Scott Wood | static void map_list(OpenPICState *opp, const MemReg *list, int *count) |
1515 | e0dfe5b1 | Scott Wood | { |
1516 | e0dfe5b1 | Scott Wood | while (list->name) {
|
1517 | e0dfe5b1 | Scott Wood | assert(*count < ARRAY_SIZE(opp->sub_io_mem)); |
1518 | e0dfe5b1 | Scott Wood | |
1519 | e0dfe5b1 | Scott Wood | memory_region_init_io(&opp->sub_io_mem[*count], list->ops, opp, |
1520 | e0dfe5b1 | Scott Wood | list->name, list->size); |
1521 | e0dfe5b1 | Scott Wood | |
1522 | e0dfe5b1 | Scott Wood | memory_region_add_subregion(&opp->mem, list->start_addr, |
1523 | e0dfe5b1 | Scott Wood | &opp->sub_io_mem[*count]); |
1524 | e0dfe5b1 | Scott Wood | |
1525 | e0dfe5b1 | Scott Wood | (*count)++; |
1526 | e0dfe5b1 | Scott Wood | list++; |
1527 | e0dfe5b1 | Scott Wood | } |
1528 | e0dfe5b1 | Scott Wood | } |
1529 | e0dfe5b1 | Scott Wood | |
1530 | cbe72019 | Andreas Färber | static void openpic_init(Object *obj) |
1531 | dbda808a | bellard | { |
1532 | cbe72019 | Andreas Färber | OpenPICState *opp = OPENPIC(obj); |
1533 | cbe72019 | Andreas Färber | |
1534 | cbe72019 | Andreas Färber | memory_region_init(&opp->mem, "openpic", 0x40000); |
1535 | cbe72019 | Andreas Färber | } |
1536 | cbe72019 | Andreas Färber | |
1537 | cbe72019 | Andreas Färber | static void openpic_realize(DeviceState *dev, Error **errp) |
1538 | cbe72019 | Andreas Färber | { |
1539 | cbe72019 | Andreas Färber | SysBusDevice *d = SYS_BUS_DEVICE(dev); |
1540 | e1766344 | Andreas Färber | OpenPICState *opp = OPENPIC(dev); |
1541 | d0b72631 | Alexander Graf | int i, j;
|
1542 | e0dfe5b1 | Scott Wood | int list_count = 0; |
1543 | e0dfe5b1 | Scott Wood | static const MemReg list_le[] = { |
1544 | e0dfe5b1 | Scott Wood | {"glb", &openpic_glb_ops_le,
|
1545 | 732aa6ec | Alexander Graf | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, |
1546 | e0dfe5b1 | Scott Wood | {"tmr", &openpic_tmr_ops_le,
|
1547 | 732aa6ec | Alexander Graf | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, |
1548 | e0dfe5b1 | Scott Wood | {"src", &openpic_src_ops_le,
|
1549 | 732aa6ec | Alexander Graf | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, |
1550 | e0dfe5b1 | Scott Wood | {"cpu", &openpic_cpu_ops_le,
|
1551 | 732aa6ec | Alexander Graf | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, |
1552 | e0dfe5b1 | Scott Wood | {NULL}
|
1553 | 780d16b7 | Alexander Graf | }; |
1554 | e0dfe5b1 | Scott Wood | static const MemReg list_be[] = { |
1555 | e0dfe5b1 | Scott Wood | {"glb", &openpic_glb_ops_be,
|
1556 | 732aa6ec | Alexander Graf | OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE}, |
1557 | e0dfe5b1 | Scott Wood | {"tmr", &openpic_tmr_ops_be,
|
1558 | 732aa6ec | Alexander Graf | OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE}, |
1559 | e0dfe5b1 | Scott Wood | {"src", &openpic_src_ops_be,
|
1560 | 732aa6ec | Alexander Graf | OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE}, |
1561 | e0dfe5b1 | Scott Wood | {"cpu", &openpic_cpu_ops_be,
|
1562 | 732aa6ec | Alexander Graf | OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE}, |
1563 | e0dfe5b1 | Scott Wood | {NULL}
|
1564 | d0b72631 | Alexander Graf | }; |
1565 | e0dfe5b1 | Scott Wood | static const MemReg list_fsl[] = { |
1566 | e0dfe5b1 | Scott Wood | {"msi", &openpic_msi_ops_be,
|
1567 | e0dfe5b1 | Scott Wood | OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE}, |
1568 | e0dfe5b1 | Scott Wood | {"summary", &openpic_summary_ops_be,
|
1569 | e0dfe5b1 | Scott Wood | OPENPIC_SUMMARY_REG_START, OPENPIC_SUMMARY_REG_SIZE}, |
1570 | e0dfe5b1 | Scott Wood | {NULL}
|
1571 | e0dfe5b1 | Scott Wood | }; |
1572 | e0dfe5b1 | Scott Wood | |
1573 | d0b72631 | Alexander Graf | switch (opp->model) {
|
1574 | d0b72631 | Alexander Graf | case OPENPIC_MODEL_FSL_MPIC_20:
|
1575 | d0b72631 | Alexander Graf | default:
|
1576 | e0dfe5b1 | Scott Wood | opp->fsl = &fsl_mpic_20; |
1577 | e0dfe5b1 | Scott Wood | opp->brr1 = 0x00400200;
|
1578 | be7c236f | Scott Wood | opp->flags |= OPENPIC_FLAG_IDR_CRIT; |
1579 | d0b72631 | Alexander Graf | opp->nb_irqs = 80;
|
1580 | e0dfe5b1 | Scott Wood | opp->mpic_mode_mask = GCR_MODE_MIXED; |
1581 | 68c2dd70 | Alexander Graf | |
1582 | e0dfe5b1 | Scott Wood | fsl_common_init(opp); |
1583 | e0dfe5b1 | Scott Wood | map_list(opp, list_be, &list_count); |
1584 | e0dfe5b1 | Scott Wood | map_list(opp, list_fsl, &list_count); |
1585 | 6c5e84c2 | Scott Wood | |
1586 | e0dfe5b1 | Scott Wood | break;
|
1587 | 6c5e84c2 | Scott Wood | |
1588 | e0dfe5b1 | Scott Wood | case OPENPIC_MODEL_FSL_MPIC_42:
|
1589 | e0dfe5b1 | Scott Wood | opp->fsl = &fsl_mpic_42; |
1590 | e0dfe5b1 | Scott Wood | opp->brr1 = 0x00400402;
|
1591 | e0dfe5b1 | Scott Wood | opp->flags |= OPENPIC_FLAG_ILR; |
1592 | e0dfe5b1 | Scott Wood | opp->nb_irqs = 196;
|
1593 | e0dfe5b1 | Scott Wood | opp->mpic_mode_mask = GCR_MODE_PROXY; |
1594 | 6c5e84c2 | Scott Wood | |
1595 | e0dfe5b1 | Scott Wood | fsl_common_init(opp); |
1596 | e0dfe5b1 | Scott Wood | map_list(opp, list_be, &list_count); |
1597 | e0dfe5b1 | Scott Wood | map_list(opp, list_fsl, &list_count); |
1598 | 6c5e84c2 | Scott Wood | |
1599 | d0b72631 | Alexander Graf | break;
|
1600 | 6c5e84c2 | Scott Wood | |
1601 | d0b72631 | Alexander Graf | case OPENPIC_MODEL_RAVEN:
|
1602 | d0b72631 | Alexander Graf | opp->nb_irqs = RAVEN_MAX_EXT; |
1603 | d0b72631 | Alexander Graf | opp->vid = VID_REVISION_1_3; |
1604 | be7c236f | Scott Wood | opp->vir = VIR_GENERIC; |
1605 | 0fe04622 | Scott Wood | opp->vector_mask = 0xFF;
|
1606 | be7c236f | Scott Wood | opp->tfrr_reset = 4160000;
|
1607 | be7c236f | Scott Wood | opp->ivpr_reset = IVPR_MASK_MASK | IVPR_MODE_MASK; |
1608 | be7c236f | Scott Wood | opp->idr_reset = 0;
|
1609 | d0b72631 | Alexander Graf | opp->max_irq = RAVEN_MAX_IRQ; |
1610 | d0b72631 | Alexander Graf | opp->irq_ipi0 = RAVEN_IPI_IRQ; |
1611 | d0b72631 | Alexander Graf | opp->irq_tim0 = RAVEN_TMR_IRQ; |
1612 | dbbbfd60 | Alexander Graf | opp->brr1 = -1;
|
1613 | 86e56a88 | Alexander Graf | opp->mpic_mode_mask = GCR_MODE_MIXED; |
1614 | d0b72631 | Alexander Graf | |
1615 | d0b72631 | Alexander Graf | if (opp->nb_cpus != 1) { |
1616 | cbe72019 | Andreas Färber | error_setg(errp, "Only UP supported today");
|
1617 | cbe72019 | Andreas Färber | return;
|
1618 | d0b72631 | Alexander Graf | } |
1619 | 780d16b7 | Alexander Graf | |
1620 | e0dfe5b1 | Scott Wood | map_list(opp, list_le, &list_count); |
1621 | e0dfe5b1 | Scott Wood | break;
|
1622 | 780d16b7 | Alexander Graf | } |
1623 | 3b46e624 | ths | |
1624 | d0b72631 | Alexander Graf | for (i = 0; i < opp->nb_cpus; i++) { |
1625 | d0b72631 | Alexander Graf | opp->dst[i].irqs = g_new(qemu_irq, OPENPIC_OUTPUT_NB); |
1626 | d0b72631 | Alexander Graf | for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { |
1627 | cbe72019 | Andreas Färber | sysbus_init_irq(d, &opp->dst[i].irqs[j]); |
1628 | d0b72631 | Alexander Graf | } |
1629 | d0b72631 | Alexander Graf | } |
1630 | d0b72631 | Alexander Graf | |
1631 | cbe72019 | Andreas Färber | register_savevm(dev, "openpic", 0, 2, |
1632 | 0be71e32 | Alex Williamson | openpic_save, openpic_load, opp); |
1633 | b7169916 | aurel32 | |
1634 | cbe72019 | Andreas Färber | sysbus_init_mmio(d, &opp->mem); |
1635 | cbe72019 | Andreas Färber | qdev_init_gpio_in(dev, openpic_set_irq, opp->max_irq); |
1636 | b7169916 | aurel32 | } |
1637 | b7169916 | aurel32 | |
1638 | d0b72631 | Alexander Graf | static Property openpic_properties[] = {
|
1639 | d0b72631 | Alexander Graf | DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20),
|
1640 | d0b72631 | Alexander Graf | DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1), |
1641 | d0b72631 | Alexander Graf | DEFINE_PROP_END_OF_LIST(), |
1642 | d0b72631 | Alexander Graf | }; |
1643 | 71cf9e62 | Fabien Chouteau | |
1644 | cbe72019 | Andreas Färber | static void openpic_class_init(ObjectClass *oc, void *data) |
1645 | d0b72631 | Alexander Graf | { |
1646 | cbe72019 | Andreas Färber | DeviceClass *dc = DEVICE_CLASS(oc); |
1647 | b7169916 | aurel32 | |
1648 | cbe72019 | Andreas Färber | dc->realize = openpic_realize; |
1649 | d0b72631 | Alexander Graf | dc->props = openpic_properties; |
1650 | d0b72631 | Alexander Graf | dc->reset = openpic_reset; |
1651 | d0b72631 | Alexander Graf | } |
1652 | 71cf9e62 | Fabien Chouteau | |
1653 | 8c43a6f0 | Andreas Färber | static const TypeInfo openpic_info = { |
1654 | e1766344 | Andreas Färber | .name = TYPE_OPENPIC, |
1655 | d0b72631 | Alexander Graf | .parent = TYPE_SYS_BUS_DEVICE, |
1656 | d0b72631 | Alexander Graf | .instance_size = sizeof(OpenPICState),
|
1657 | cbe72019 | Andreas Färber | .instance_init = openpic_init, |
1658 | d0b72631 | Alexander Graf | .class_init = openpic_class_init, |
1659 | d0b72631 | Alexander Graf | }; |
1660 | b7169916 | aurel32 | |
1661 | d0b72631 | Alexander Graf | static void openpic_register_types(void) |
1662 | d0b72631 | Alexander Graf | { |
1663 | d0b72631 | Alexander Graf | type_register_static(&openpic_info); |
1664 | dbda808a | bellard | } |
1665 | d0b72631 | Alexander Graf | |
1666 | d0b72631 | Alexander Graf | type_init(openpic_register_types) |