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root / hw / intc @ ab8131af

Name Size
Makefile.objs 985 Bytes
apic.c 23.5 kB
apic_common.c 10.8 kB
arm_gic.c 21.5 kB
arm_gic_common.c 5.5 kB
arm_gic_kvm.c 5.4 kB
armv7m_nvic.c 18 kB
etraxfs_pic.c 4.9 kB
exynos4210_combiner.c 15.1 kB
exynos4210_gic.c 14 kB
gic_internal.h 5.1 kB
grlib_irqmp.c 9.5 kB
heathrow_pic.c 5.8 kB
i8259.c 13.4 kB
i8259_common.c 4.9 kB
imx_avic.c 11.7 kB
ioapic.c 7.4 kB
ioapic_common.c 3.3 kB
lm32_pic.c 4.6 kB
omap_intc.c 17.7 kB
openpic.c 45.4 kB
openpic_kvm.c 7.5 kB
pl190.c 7.8 kB
puv3_intc.c 3.2 kB
realview_gic.c 2.1 kB
sh_intc.c 13.4 kB
slavio_intctl.c 13.8 kB
xilinx_intc.c 5 kB

Latest revisions

# Date Author Comment
cbe72019 07/01/2013 02:11 am Andreas Färber

intc/openpic: Convert to QOM realize

Split qdev initfn into instance_init and realize functions.
Change one occurrence of "klass" while at it.

Signed-off-by: Andreas Färber <>
Reviewed-by: Peter Crosthwaite <>...
dd49c038 07/01/2013 02:11 am Andreas Färber

intc/openpic_kvm: Fix QOM and build issues

Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
8935a442 07/01/2013 02:11 am Scott Wood

openpic: factor out some common defines into openpic.h

...for use by the KVM in-kernel irqchip stub.

Signed-off-by: Scott Wood <>
Signed-off-by: Alexander Graf <>
d85937e6 07/01/2013 02:11 am Scott Wood

kvm/openpic: in-kernel mpic support

Enables support for the in-kernel MPIC that thas been merged into the
KVM next branch. This includes irqfd/KVM_IRQ_LINE support from Alex
Graf (along with some other improvements).

Note from Alex regarding kvm_irqchip_create():...
e1766344 07/01/2013 02:11 am Andreas Färber

intc/openpic: QOM'ify

Introduce type constant and cast macro.

Signed-off-by: Andreas Färber <>
Reviewed-by: Peter Crosthwaite <>
Signed-off-by: Alexander Graf <>
45fdd3bf 06/18/2013 10:45 am Peter Crosthwaite

intc/xilinx_intc: Handle level interrupt retriggering

Acking a level sensitive interrupt should have no effect if the
interrupt pin is still asserted. The current implementation requires
and edge condition to occur for setting a level sensitive IRQ, which...
fa96d614 06/18/2013 10:45 am Peter Crosthwaite

intc/xilinx_intc: Inhibit write to ISR when HIE

When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.

Signed-off-by: Peter Crosthwaite <>
Signed-off-by: Edgar E. Iglesias <>
afd59989 06/18/2013 10:45 am Peter Crosthwaite

intc/xilinx_intc: Dont lower IRQ when HIE cleared

This is a little strange. It is lowering the parent IRQ pin on input
when HIE is cleared. There is no such behaviour in the real hardware.

ISR changes based on interrupt pin state are already guarded on HIE...
6327c221 06/18/2013 10:44 am Peter Crosthwaite

intc/xilinx_intc: Don't clear level sens. IRQs without ACK

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER).

Signed-off-by: Peter Crosthwaite <>...
371a775d 06/15/2013 01:53 pm Blue Swirl

Merge branch 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu

  • 'realize-isa.v2' of git://github.com/afaerber/qemu-cpu:
    qdev: Drop FROM_QBUS() macro
    isa: QOM'ify ISADevice
    isa: QOM'ify ISABus
    i8259: Convert PICCommonState to use QOM realizefn...

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