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exec: Make ldl_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Add MSR VSX and Associated Exception
This patch adds support for the VSX bit of the PowerPC MachineState Register (MSR) as well as the corresponding VSX Unavailableexception.
The VSX bit is added to the defined bits masks of the Power7 andPower8 CPU models....
cpu: Use QTAILQ for CPU list
Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthandmacros.
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: USE LPCR_ILE to control exception endian on POWER7
On POWER7, LPCR_ILE is used to control what endian guests taketheir exceptions in so use it instead of MSR_ILE.
Signed-off-by: Anton Blanchard <anton@samba.org>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>...
cpu: Make first_cpu and next_cpu CPUState
Move next_cpu from CPU_COMMON to CPUState.Move first_cpu variable to qom/cpu.h.
gdbstub needs to use CPUState::env_ptr for now.cpu_copy() no longer needs to save and restore cpu_next.
Acked-by: Paolo Bonzini <pbonzini@redhat.com>...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
PPC: Bring EPR support closer to reality
We already used to support the external proxy facility of FSL MPICs,but only implemented it halfway correctly.
This patch adds support for
ppc/booke: fix crit/mcheck/debug exceptions
Book E does not play games with certain bits of xSRR1 being MSR savebits and others being error status. xSRR1 is the old MSR, period.This was causing things like MSR[CE] to be lost, even in the savedversion, as soon as you take an exception....
target-ppc: Pass PowerPCCPU to powerpc_excp()
Needed for changing cpu_ppc_hypercall() argument type to PowerPCCPU.
target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall
Adapt emulate_spapr_hypercall() accordingly.
Needed for changing spapr_hypercall() argument type to PowerPCCPU.
PPC: Add support for MSR_CM
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG tosupport running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Move load and store helpers, switch to AREG0 free mode
Add an explicit CPUPPCState parameter instead of relying on AREG0and rename op_helper.c (which only contains load and store helpers)to mem_helper.c. Remove AREG0 swapping intlb_fill().
Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation...
ppc: Move exception helpers from helper.c to excp_helper.c
Move exception helpers from helper.c to excp_helper.c andmake cpu_dump_rfi() static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>...
ppc: Split exception helpers
Move exception helpers from op_helper.c to excp_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: Avoid AREG0 for exception helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.