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1 | 87ecb68b | pbrook | #ifndef QEMU_PCI_H
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2 | 87ecb68b | pbrook | #define QEMU_PCI_H
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3 | 87ecb68b | pbrook | |
4 | 376253ec | aliguori | #include "qemu-common.h" |
5 | 376253ec | aliguori | |
6 | 6b1b92d3 | Paul Brook | #include "qdev.h" |
7 | 1e39101c | Avi Kivity | #include "memory.h" |
8 | ec174575 | David Gibson | #include "dma.h" |
9 | 6b1b92d3 | Paul Brook | |
10 | 87ecb68b | pbrook | /* PCI includes legacy ISA access. */
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11 | 87ecb68b | pbrook | #include "isa.h" |
12 | 87ecb68b | pbrook | |
13 | 0428527c | Isaku Yamahata | #include "pcie.h" |
14 | 0428527c | Isaku Yamahata | |
15 | 87ecb68b | pbrook | /* PCI bus */
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16 | 87ecb68b | pbrook | |
17 | 3ae80618 | aliguori | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 | 3ae80618 | aliguori | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
19 | 3ae80618 | aliguori | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
20 | 90a20dbb | Isaku Yamahata | #define PCI_SLOT_MAX 32 |
21 | 6fa84913 | Isaku Yamahata | #define PCI_FUNC_MAX 8 |
22 | 3ae80618 | aliguori | |
23 | a770dc7e | aliguori | /* Class, Vendor and Device IDs from Linux's pci_ids.h */
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24 | a770dc7e | aliguori | #include "pci_ids.h" |
25 | 173a543b | blueswir1 | |
26 | a770dc7e | aliguori | /* QEMU-specific Vendor and Device ID definitions */
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27 | 6f338c34 | aliguori | |
28 | a770dc7e | aliguori | /* IBM (0x1014) */
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29 | a770dc7e | aliguori | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
30 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
31 | deb54399 | aliguori | |
32 | a770dc7e | aliguori | /* Hitachi (0x1054) */
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33 | deb54399 | aliguori | #define PCI_VENDOR_ID_HITACHI 0x1054 |
34 | a770dc7e | aliguori | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
35 | deb54399 | aliguori | |
36 | a770dc7e | aliguori | /* Apple (0x106b) */
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37 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
39 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
40 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
41 | a770dc7e | aliguori | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
42 | deb54399 | aliguori | |
43 | a770dc7e | aliguori | /* Realtek (0x10ec) */
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44 | a770dc7e | aliguori | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
45 | deb54399 | aliguori | |
46 | a770dc7e | aliguori | /* Xilinx (0x10ee) */
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47 | a770dc7e | aliguori | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
48 | deb54399 | aliguori | |
49 | a770dc7e | aliguori | /* Marvell (0x11ab) */
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50 | a770dc7e | aliguori | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
51 | deb54399 | aliguori | |
52 | a770dc7e | aliguori | /* QEMU/Bochs VGA (0x1234) */
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53 | 4ebcf884 | blueswir1 | #define PCI_VENDOR_ID_QEMU 0x1234 |
54 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
55 | 4ebcf884 | blueswir1 | |
56 | a770dc7e | aliguori | /* VMWare (0x15ad) */
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57 | deb54399 | aliguori | #define PCI_VENDOR_ID_VMWARE 0x15ad |
58 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
59 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
60 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
61 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
62 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
63 | deb54399 | aliguori | |
64 | cef3017c | aliguori | /* Intel (0x8086) */
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65 | a770dc7e | aliguori | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
66 | d6fd1e66 | Stefan Weil | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
67 | 1a5a86fb | Alexander Graf | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
68 | 74c62ba8 | aurel32 | |
69 | deb54399 | aliguori | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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70 | d350d97d | aliguori | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
71 | d350d97d | aliguori | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
72 | d350d97d | aliguori | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
73 | d350d97d | aliguori | |
74 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
75 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
76 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
77 | 14d50bef | aliguori | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
78 | 973abc7f | Stefan Hajnoczi | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
79 | d350d97d | aliguori | |
80 | 4f8589e1 | Isaku Yamahata | #define FMT_PCIBUS PRIx64
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81 | 6e355d90 | Isaku Yamahata | |
82 | 87ecb68b | pbrook | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
83 | 87ecb68b | pbrook | uint32_t address, uint32_t data, int len);
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84 | 87ecb68b | pbrook | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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85 | 87ecb68b | pbrook | uint32_t address, int len);
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86 | 87ecb68b | pbrook | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
87 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type);
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88 | 5851e08c | aliguori | typedef int PCIUnregisterFunc(PCIDevice *pci_dev); |
89 | 87ecb68b | pbrook | |
90 | 87ecb68b | pbrook | typedef struct PCIIORegion { |
91 | 6e355d90 | Isaku Yamahata | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
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92 | 6e355d90 | Isaku Yamahata | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
93 | 6e355d90 | Isaku Yamahata | pcibus_t size; |
94 | 87ecb68b | pbrook | uint8_t type; |
95 | 79ff8cb0 | Avi Kivity | MemoryRegion *memory; |
96 | 5968eca3 | Avi Kivity | MemoryRegion *address_space; |
97 | 87ecb68b | pbrook | } PCIIORegion; |
98 | 87ecb68b | pbrook | |
99 | 87ecb68b | pbrook | #define PCI_ROM_SLOT 6 |
100 | 87ecb68b | pbrook | #define PCI_NUM_REGIONS 7 |
101 | 87ecb68b | pbrook | |
102 | fb58a897 | Isaku Yamahata | #include "pci_regs.h" |
103 | fb58a897 | Isaku Yamahata | |
104 | fb58a897 | Isaku Yamahata | /* PCI HEADER_TYPE */
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105 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
106 | 8098ed41 | aurel32 | |
107 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config header */
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108 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_HEADER_SIZE 0x40 |
109 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config space */
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110 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_SPACE_SIZE 0x100 |
111 | a9f49946 | Isaku Yamahata | /* Size of the standart PCIe config space: 4KB */
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112 | a9f49946 | Isaku Yamahata | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
113 | b7ee1603 | Michael S. Tsirkin | |
114 | e369cad7 | Isaku Yamahata | #define PCI_NUM_PINS 4 /* A-D */ |
115 | e369cad7 | Isaku Yamahata | |
116 | 02eb84d0 | Michael S. Tsirkin | /* Bits in cap_present field. */
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117 | 02eb84d0 | Michael S. Tsirkin | enum {
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118 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_MSI = 0x1,
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119 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_MSIX = 0x2,
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120 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_EXPRESS = 0x4,
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121 | 49823868 | Isaku Yamahata | |
122 | 49823868 | Isaku Yamahata | /* multifunction capable device */
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123 | e4c7d2ae | Isaku Yamahata | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
124 | 49823868 | Isaku Yamahata | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
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125 | b1aeb926 | Isaku Yamahata | |
126 | b1aeb926 | Isaku Yamahata | /* command register SERR bit enabled */
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127 | b1aeb926 | Isaku Yamahata | #define QEMU_PCI_CAP_SERR_BITNR 4 |
128 | b1aeb926 | Isaku Yamahata | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
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129 | 1dc324d2 | Michael S. Tsirkin | /* Standard hot plug controller. */
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130 | 1dc324d2 | Michael S. Tsirkin | #define QEMU_PCI_SHPC_BITNR 5 |
131 | 1dc324d2 | Michael S. Tsirkin | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
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132 | 762833b3 | Michael S. Tsirkin | #define QEMU_PCI_SLOTID_BITNR 6 |
133 | 762833b3 | Michael S. Tsirkin | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
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134 | 02eb84d0 | Michael S. Tsirkin | }; |
135 | 02eb84d0 | Michael S. Tsirkin | |
136 | 40021f08 | Anthony Liguori | #define TYPE_PCI_DEVICE "pci-device" |
137 | 40021f08 | Anthony Liguori | #define PCI_DEVICE(obj) \
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138 | 40021f08 | Anthony Liguori | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) |
139 | 40021f08 | Anthony Liguori | #define PCI_DEVICE_CLASS(klass) \
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140 | 40021f08 | Anthony Liguori | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) |
141 | 40021f08 | Anthony Liguori | #define PCI_DEVICE_GET_CLASS(obj) \
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142 | 40021f08 | Anthony Liguori | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) |
143 | 40021f08 | Anthony Liguori | |
144 | 40021f08 | Anthony Liguori | typedef struct PCIDeviceClass { |
145 | 40021f08 | Anthony Liguori | DeviceClass parent_class; |
146 | 40021f08 | Anthony Liguori | |
147 | 40021f08 | Anthony Liguori | int (*init)(PCIDevice *dev);
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148 | 40021f08 | Anthony Liguori | PCIUnregisterFunc *exit; |
149 | 40021f08 | Anthony Liguori | PCIConfigReadFunc *config_read; |
150 | 40021f08 | Anthony Liguori | PCIConfigWriteFunc *config_write; |
151 | 40021f08 | Anthony Liguori | |
152 | 40021f08 | Anthony Liguori | uint16_t vendor_id; |
153 | 40021f08 | Anthony Liguori | uint16_t device_id; |
154 | 40021f08 | Anthony Liguori | uint8_t revision; |
155 | 40021f08 | Anthony Liguori | uint16_t class_id; |
156 | 40021f08 | Anthony Liguori | uint16_t subsystem_vendor_id; /* only for header type = 0 */
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157 | 40021f08 | Anthony Liguori | uint16_t subsystem_id; /* only for header type = 0 */
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158 | 40021f08 | Anthony Liguori | |
159 | 40021f08 | Anthony Liguori | /*
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160 | 40021f08 | Anthony Liguori | * pci-to-pci bridge or normal device.
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161 | 40021f08 | Anthony Liguori | * This doesn't mean pci host switch.
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162 | 40021f08 | Anthony Liguori | * When card bus bridge is supported, this would be enhanced.
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163 | 40021f08 | Anthony Liguori | */
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164 | 40021f08 | Anthony Liguori | int is_bridge;
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165 | 40021f08 | Anthony Liguori | |
166 | 40021f08 | Anthony Liguori | /* pcie stuff */
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167 | 40021f08 | Anthony Liguori | int is_express; /* is this device pci express? */ |
168 | 40021f08 | Anthony Liguori | |
169 | 40021f08 | Anthony Liguori | /* device isn't hot-pluggable */
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170 | 40021f08 | Anthony Liguori | int no_hotplug;
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171 | 40021f08 | Anthony Liguori | |
172 | 40021f08 | Anthony Liguori | /* rom bar */
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173 | 40021f08 | Anthony Liguori | const char *romfile; |
174 | 40021f08 | Anthony Liguori | } PCIDeviceClass; |
175 | 40021f08 | Anthony Liguori | |
176 | 2cdfe53c | Jan Kiszka | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
177 | 2cdfe53c | Jan Kiszka | MSIMessage msg); |
178 | 2cdfe53c | Jan Kiszka | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); |
179 | 2cdfe53c | Jan Kiszka | |
180 | 87ecb68b | pbrook | struct PCIDevice {
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181 | 6b1b92d3 | Paul Brook | DeviceState qdev; |
182 | 5fa45de5 | David Gibson | |
183 | 87ecb68b | pbrook | /* PCI config space */
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184 | a9f49946 | Isaku Yamahata | uint8_t *config; |
185 | b7ee1603 | Michael S. Tsirkin | |
186 | ebabb67a | Stefan Weil | /* Used to enable config checks on load. Note that writable bits are
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187 | bd4b65ee | Michael S. Tsirkin | * never checked even if set in cmask. */
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188 | a9f49946 | Isaku Yamahata | uint8_t *cmask; |
189 | bd4b65ee | Michael S. Tsirkin | |
190 | b7ee1603 | Michael S. Tsirkin | /* Used to implement R/W bytes */
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191 | a9f49946 | Isaku Yamahata | uint8_t *wmask; |
192 | 87ecb68b | pbrook | |
193 | 92ba5f51 | Isaku Yamahata | /* Used to implement RW1C(Write 1 to Clear) bytes */
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194 | 92ba5f51 | Isaku Yamahata | uint8_t *w1cmask; |
195 | 92ba5f51 | Isaku Yamahata | |
196 | 6f4cbd39 | Michael S. Tsirkin | /* Used to allocate config space for capabilities. */
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197 | a9f49946 | Isaku Yamahata | uint8_t *used; |
198 | 6f4cbd39 | Michael S. Tsirkin | |
199 | 87ecb68b | pbrook | /* the following fields are read only */
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200 | 87ecb68b | pbrook | PCIBus *bus; |
201 | 09f1bbcd | Michael Roth | int32_t devfn; |
202 | 87ecb68b | pbrook | char name[64]; |
203 | 87ecb68b | pbrook | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
204 | 5fa45de5 | David Gibson | DMAContext *dma; |
205 | 87ecb68b | pbrook | |
206 | 87ecb68b | pbrook | /* do not access the following fields */
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207 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read; |
208 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write; |
209 | 87ecb68b | pbrook | |
210 | 87ecb68b | pbrook | /* IRQ objects for the INTA-INTD pins. */
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211 | 87ecb68b | pbrook | qemu_irq *irq; |
212 | 87ecb68b | pbrook | |
213 | 87ecb68b | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
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214 | d036bb21 | Michael S. Tsirkin | uint8_t irq_state; |
215 | 02eb84d0 | Michael S. Tsirkin | |
216 | 02eb84d0 | Michael S. Tsirkin | /* Capability bits */
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217 | 02eb84d0 | Michael S. Tsirkin | uint32_t cap_present; |
218 | 02eb84d0 | Michael S. Tsirkin | |
219 | 02eb84d0 | Michael S. Tsirkin | /* Offset of MSI-X capability in config space */
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220 | 02eb84d0 | Michael S. Tsirkin | uint8_t msix_cap; |
221 | 02eb84d0 | Michael S. Tsirkin | |
222 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X entries */
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223 | 02eb84d0 | Michael S. Tsirkin | int msix_entries_nr;
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224 | 02eb84d0 | Michael S. Tsirkin | |
225 | 02eb84d0 | Michael S. Tsirkin | /* Space to store MSIX table */
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226 | 02eb84d0 | Michael S. Tsirkin | uint8_t *msix_table_page; |
227 | 02eb84d0 | Michael S. Tsirkin | /* MMIO index used to map MSIX table and pending bit entries. */
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228 | 95524ae8 | Avi Kivity | MemoryRegion msix_mmio; |
229 | 02eb84d0 | Michael S. Tsirkin | /* Reference-count for entries actually in use by driver. */
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230 | 02eb84d0 | Michael S. Tsirkin | unsigned *msix_entry_used;
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231 | 02eb84d0 | Michael S. Tsirkin | /* Region including the MSI-X table */
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232 | 02eb84d0 | Michael S. Tsirkin | uint32_t msix_bar_size; |
233 | 50322249 | Michael S. Tsirkin | /* MSIX function mask set or MSIX disabled */
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234 | 50322249 | Michael S. Tsirkin | bool msix_function_masked;
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235 | f16c4abf | Juan Quintela | /* Version id needed for VMState */
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236 | f16c4abf | Juan Quintela | int32_t version_id; |
237 | c2039bd0 | Anthony Liguori | |
238 | e4c7d2ae | Isaku Yamahata | /* Offset of MSI capability in config space */
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239 | e4c7d2ae | Isaku Yamahata | uint8_t msi_cap; |
240 | e4c7d2ae | Isaku Yamahata | |
241 | 0428527c | Isaku Yamahata | /* PCI Express */
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242 | 0428527c | Isaku Yamahata | PCIExpressDevice exp; |
243 | 0428527c | Isaku Yamahata | |
244 | 1dc324d2 | Michael S. Tsirkin | /* SHPC */
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245 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc; |
246 | 1dc324d2 | Michael S. Tsirkin | |
247 | c2039bd0 | Anthony Liguori | /* Location of option rom */
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248 | 8c52c8f3 | Gerd Hoffmann | char *romfile;
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249 | 14caaf7f | Avi Kivity | bool has_rom;
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250 | 14caaf7f | Avi Kivity | MemoryRegion rom; |
251 | 88169ddf | Gerd Hoffmann | uint32_t rom_bar; |
252 | 2cdfe53c | Jan Kiszka | |
253 | 2cdfe53c | Jan Kiszka | /* MSI-X notifiers */
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254 | 2cdfe53c | Jan Kiszka | MSIVectorUseNotifier msix_vector_use_notifier; |
255 | 2cdfe53c | Jan Kiszka | MSIVectorReleaseNotifier msix_vector_release_notifier; |
256 | 87ecb68b | pbrook | }; |
257 | 87ecb68b | pbrook | |
258 | e824b2cc | Avi Kivity | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
259 | e824b2cc | Avi Kivity | uint8_t attr, MemoryRegion *memory); |
260 | 16a96f28 | Avi Kivity | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
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261 | 87ecb68b | pbrook | |
262 | ca77089d | Isaku Yamahata | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
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263 | ca77089d | Isaku Yamahata | uint8_t offset, uint8_t size); |
264 | 6f4cbd39 | Michael S. Tsirkin | |
265 | 6f4cbd39 | Michael S. Tsirkin | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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266 | 6f4cbd39 | Michael S. Tsirkin | |
267 | 6f4cbd39 | Michael S. Tsirkin | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
268 | 6f4cbd39 | Michael S. Tsirkin | |
269 | 6f4cbd39 | Michael S. Tsirkin | |
270 | 87ecb68b | pbrook | uint32_t pci_default_read_config(PCIDevice *d, |
271 | 87ecb68b | pbrook | uint32_t address, int len);
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272 | 87ecb68b | pbrook | void pci_default_write_config(PCIDevice *d,
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273 | 87ecb68b | pbrook | uint32_t address, uint32_t val, int len);
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274 | 87ecb68b | pbrook | void pci_device_save(PCIDevice *s, QEMUFile *f);
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275 | 87ecb68b | pbrook | int pci_device_load(PCIDevice *s, QEMUFile *f);
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276 | f5e6fed8 | Avi Kivity | MemoryRegion *pci_address_space(PCIDevice *dev); |
277 | e11d6439 | Richard Henderson | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
278 | 87ecb68b | pbrook | |
279 | 5d4e84c8 | Juan Quintela | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
280 | 87ecb68b | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
281 | e927d487 | Michael S. Tsirkin | |
282 | e927d487 | Michael S. Tsirkin | typedef enum { |
283 | e927d487 | Michael S. Tsirkin | PCI_HOTPLUG_DISABLED, |
284 | e927d487 | Michael S. Tsirkin | PCI_HOTPLUG_ENABLED, |
285 | e927d487 | Michael S. Tsirkin | PCI_COLDPLUG_ENABLED, |
286 | e927d487 | Michael S. Tsirkin | } PCIHotplugState; |
287 | e927d487 | Michael S. Tsirkin | |
288 | e927d487 | Michael S. Tsirkin | typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, |
289 | e927d487 | Michael S. Tsirkin | PCIHotplugState state); |
290 | 21eea4b3 | Gerd Hoffmann | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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291 | 1e39101c | Avi Kivity | const char *name, |
292 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
293 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
294 | 1e39101c | Avi Kivity | uint8_t devfn_min); |
295 | 1e39101c | Avi Kivity | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
296 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
297 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
298 | aee97b84 | Avi Kivity | uint8_t devfn_min); |
299 | 21eea4b3 | Gerd Hoffmann | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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300 | 21eea4b3 | Gerd Hoffmann | void *irq_opaque, int nirq); |
301 | 9ddf8437 | Isaku Yamahata | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
302 | 87c30546 | Isaku Yamahata | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
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303 | 02e2da45 | Paul Brook | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
304 | 02e2da45 | Paul Brook | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
305 | 1e39101c | Avi Kivity | void *irq_opaque,
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306 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
307 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
308 | 1e39101c | Avi Kivity | uint8_t devfn_min, int nirq);
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309 | 0ead87c8 | Isaku Yamahata | void pci_device_reset(PCIDevice *dev);
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310 | 9bb33586 | Isaku Yamahata | void pci_bus_reset(PCIBus *bus);
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311 | 87ecb68b | pbrook | |
312 | 5607c388 | Markus Armbruster | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
313 | 5607c388 | Markus Armbruster | const char *default_devaddr); |
314 | 07caea31 | Markus Armbruster | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
315 | 07caea31 | Markus Armbruster | const char *default_devaddr); |
316 | 87ecb68b | pbrook | int pci_bus_num(PCIBus *s);
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317 | 7aa8cbb9 | Anthony PERARD | void pci_for_each_device(PCIBus *bus, int bus_num, |
318 | 7aa8cbb9 | Anthony PERARD | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), |
319 | 7aa8cbb9 | Anthony PERARD | void *opaque);
|
320 | c469e1dd | Isaku Yamahata | PCIBus *pci_find_root_bus(int domain);
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321 | e075e788 | Isaku Yamahata | int pci_find_domain(const PCIBus *bus); |
322 | 5256d8bf | Isaku Yamahata | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
323 | f3006dd1 | Isaku Yamahata | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
324 | 49bd1458 | Markus Armbruster | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
325 | 87ecb68b | pbrook | |
326 | e9283f8b | Jan Kiszka | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
327 | e9283f8b | Jan Kiszka | unsigned *slotp);
|
328 | 880345c4 | aliguori | |
329 | 4c92325b | Isaku Yamahata | void pci_device_deassert_intx(PCIDevice *dev);
|
330 | 4c92325b | Isaku Yamahata | |
331 | 5fa45de5 | David Gibson | typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int); |
332 | 5fa45de5 | David Gibson | |
333 | 5fa45de5 | David Gibson | void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque); |
334 | 5fa45de5 | David Gibson | |
335 | deb54399 | aliguori | static inline void |
336 | 64d50b8b | Michael S. Tsirkin | pci_set_byte(uint8_t *config, uint8_t val) |
337 | 64d50b8b | Michael S. Tsirkin | { |
338 | 64d50b8b | Michael S. Tsirkin | *config = val; |
339 | 64d50b8b | Michael S. Tsirkin | } |
340 | 64d50b8b | Michael S. Tsirkin | |
341 | 64d50b8b | Michael S. Tsirkin | static inline uint8_t |
342 | cb95c2e4 | Stefan Weil | pci_get_byte(const uint8_t *config)
|
343 | 64d50b8b | Michael S. Tsirkin | { |
344 | 64d50b8b | Michael S. Tsirkin | return *config;
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345 | 64d50b8b | Michael S. Tsirkin | } |
346 | 64d50b8b | Michael S. Tsirkin | |
347 | 64d50b8b | Michael S. Tsirkin | static inline void |
348 | 14e12559 | Michael S. Tsirkin | pci_set_word(uint8_t *config, uint16_t val) |
349 | 14e12559 | Michael S. Tsirkin | { |
350 | 14e12559 | Michael S. Tsirkin | cpu_to_le16wu((uint16_t *)config, val); |
351 | 14e12559 | Michael S. Tsirkin | } |
352 | 14e12559 | Michael S. Tsirkin | |
353 | 14e12559 | Michael S. Tsirkin | static inline uint16_t |
354 | cb95c2e4 | Stefan Weil | pci_get_word(const uint8_t *config)
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355 | 14e12559 | Michael S. Tsirkin | { |
356 | cb95c2e4 | Stefan Weil | return le16_to_cpupu((const uint16_t *)config); |
357 | 14e12559 | Michael S. Tsirkin | } |
358 | 14e12559 | Michael S. Tsirkin | |
359 | 14e12559 | Michael S. Tsirkin | static inline void |
360 | 14e12559 | Michael S. Tsirkin | pci_set_long(uint8_t *config, uint32_t val) |
361 | 14e12559 | Michael S. Tsirkin | { |
362 | 14e12559 | Michael S. Tsirkin | cpu_to_le32wu((uint32_t *)config, val); |
363 | 14e12559 | Michael S. Tsirkin | } |
364 | 14e12559 | Michael S. Tsirkin | |
365 | 14e12559 | Michael S. Tsirkin | static inline uint32_t |
366 | cb95c2e4 | Stefan Weil | pci_get_long(const uint8_t *config)
|
367 | 14e12559 | Michael S. Tsirkin | { |
368 | cb95c2e4 | Stefan Weil | return le32_to_cpupu((const uint32_t *)config); |
369 | 14e12559 | Michael S. Tsirkin | } |
370 | 14e12559 | Michael S. Tsirkin | |
371 | 14e12559 | Michael S. Tsirkin | static inline void |
372 | fb5ce7d2 | Isaku Yamahata | pci_set_quad(uint8_t *config, uint64_t val) |
373 | fb5ce7d2 | Isaku Yamahata | { |
374 | fb5ce7d2 | Isaku Yamahata | cpu_to_le64w((uint64_t *)config, val); |
375 | fb5ce7d2 | Isaku Yamahata | } |
376 | fb5ce7d2 | Isaku Yamahata | |
377 | fb5ce7d2 | Isaku Yamahata | static inline uint64_t |
378 | cb95c2e4 | Stefan Weil | pci_get_quad(const uint8_t *config)
|
379 | fb5ce7d2 | Isaku Yamahata | { |
380 | cb95c2e4 | Stefan Weil | return le64_to_cpup((const uint64_t *)config); |
381 | fb5ce7d2 | Isaku Yamahata | } |
382 | fb5ce7d2 | Isaku Yamahata | |
383 | fb5ce7d2 | Isaku Yamahata | static inline void |
384 | deb54399 | aliguori | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
385 | deb54399 | aliguori | { |
386 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
387 | deb54399 | aliguori | } |
388 | deb54399 | aliguori | |
389 | deb54399 | aliguori | static inline void |
390 | deb54399 | aliguori | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
391 | deb54399 | aliguori | { |
392 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
393 | deb54399 | aliguori | } |
394 | deb54399 | aliguori | |
395 | 173a543b | blueswir1 | static inline void |
396 | cf602c7b | Izik Eidus | pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
397 | cf602c7b | Izik Eidus | { |
398 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
399 | cf602c7b | Izik Eidus | } |
400 | cf602c7b | Izik Eidus | |
401 | cf602c7b | Izik Eidus | static inline void |
402 | 173a543b | blueswir1 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
403 | 173a543b | blueswir1 | { |
404 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
405 | 173a543b | blueswir1 | } |
406 | 173a543b | blueswir1 | |
407 | cf602c7b | Izik Eidus | static inline void |
408 | cf602c7b | Izik Eidus | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
409 | cf602c7b | Izik Eidus | { |
410 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
411 | cf602c7b | Izik Eidus | } |
412 | cf602c7b | Izik Eidus | |
413 | cf602c7b | Izik Eidus | static inline void |
414 | cf602c7b | Izik Eidus | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
415 | cf602c7b | Izik Eidus | { |
416 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
417 | cf602c7b | Izik Eidus | } |
418 | cf602c7b | Izik Eidus | |
419 | aabcf526 | Isaku Yamahata | /*
|
420 | aabcf526 | Isaku Yamahata | * helper functions to do bit mask operation on configuration space.
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421 | aabcf526 | Isaku Yamahata | * Just to set bit, use test-and-set and discard returned value.
|
422 | aabcf526 | Isaku Yamahata | * Just to clear bit, use test-and-clear and discard returned value.
|
423 | aabcf526 | Isaku Yamahata | * NOTE: They aren't atomic.
|
424 | aabcf526 | Isaku Yamahata | */
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425 | aabcf526 | Isaku Yamahata | static inline uint8_t |
426 | aabcf526 | Isaku Yamahata | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
427 | aabcf526 | Isaku Yamahata | { |
428 | aabcf526 | Isaku Yamahata | uint8_t val = pci_get_byte(config); |
429 | aabcf526 | Isaku Yamahata | pci_set_byte(config, val & ~mask); |
430 | aabcf526 | Isaku Yamahata | return val & mask;
|
431 | aabcf526 | Isaku Yamahata | } |
432 | aabcf526 | Isaku Yamahata | |
433 | aabcf526 | Isaku Yamahata | static inline uint8_t |
434 | aabcf526 | Isaku Yamahata | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
435 | aabcf526 | Isaku Yamahata | { |
436 | aabcf526 | Isaku Yamahata | uint8_t val = pci_get_byte(config); |
437 | aabcf526 | Isaku Yamahata | pci_set_byte(config, val | mask); |
438 | aabcf526 | Isaku Yamahata | return val & mask;
|
439 | aabcf526 | Isaku Yamahata | } |
440 | aabcf526 | Isaku Yamahata | |
441 | aabcf526 | Isaku Yamahata | static inline uint16_t |
442 | aabcf526 | Isaku Yamahata | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
443 | aabcf526 | Isaku Yamahata | { |
444 | aabcf526 | Isaku Yamahata | uint16_t val = pci_get_word(config); |
445 | aabcf526 | Isaku Yamahata | pci_set_word(config, val & ~mask); |
446 | aabcf526 | Isaku Yamahata | return val & mask;
|
447 | aabcf526 | Isaku Yamahata | } |
448 | aabcf526 | Isaku Yamahata | |
449 | aabcf526 | Isaku Yamahata | static inline uint16_t |
450 | aabcf526 | Isaku Yamahata | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
451 | aabcf526 | Isaku Yamahata | { |
452 | aabcf526 | Isaku Yamahata | uint16_t val = pci_get_word(config); |
453 | aabcf526 | Isaku Yamahata | pci_set_word(config, val | mask); |
454 | aabcf526 | Isaku Yamahata | return val & mask;
|
455 | aabcf526 | Isaku Yamahata | } |
456 | aabcf526 | Isaku Yamahata | |
457 | aabcf526 | Isaku Yamahata | static inline uint32_t |
458 | aabcf526 | Isaku Yamahata | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
459 | aabcf526 | Isaku Yamahata | { |
460 | aabcf526 | Isaku Yamahata | uint32_t val = pci_get_long(config); |
461 | aabcf526 | Isaku Yamahata | pci_set_long(config, val & ~mask); |
462 | aabcf526 | Isaku Yamahata | return val & mask;
|
463 | aabcf526 | Isaku Yamahata | } |
464 | aabcf526 | Isaku Yamahata | |
465 | aabcf526 | Isaku Yamahata | static inline uint32_t |
466 | aabcf526 | Isaku Yamahata | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
467 | aabcf526 | Isaku Yamahata | { |
468 | aabcf526 | Isaku Yamahata | uint32_t val = pci_get_long(config); |
469 | aabcf526 | Isaku Yamahata | pci_set_long(config, val | mask); |
470 | aabcf526 | Isaku Yamahata | return val & mask;
|
471 | aabcf526 | Isaku Yamahata | } |
472 | aabcf526 | Isaku Yamahata | |
473 | aabcf526 | Isaku Yamahata | static inline uint64_t |
474 | aabcf526 | Isaku Yamahata | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
475 | aabcf526 | Isaku Yamahata | { |
476 | aabcf526 | Isaku Yamahata | uint64_t val = pci_get_quad(config); |
477 | aabcf526 | Isaku Yamahata | pci_set_quad(config, val & ~mask); |
478 | aabcf526 | Isaku Yamahata | return val & mask;
|
479 | aabcf526 | Isaku Yamahata | } |
480 | aabcf526 | Isaku Yamahata | |
481 | aabcf526 | Isaku Yamahata | static inline uint64_t |
482 | aabcf526 | Isaku Yamahata | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
483 | aabcf526 | Isaku Yamahata | { |
484 | aabcf526 | Isaku Yamahata | uint64_t val = pci_get_quad(config); |
485 | aabcf526 | Isaku Yamahata | pci_set_quad(config, val | mask); |
486 | aabcf526 | Isaku Yamahata | return val & mask;
|
487 | aabcf526 | Isaku Yamahata | } |
488 | aabcf526 | Isaku Yamahata | |
489 | c9f50cea | Michael S. Tsirkin | /* Access a register specified by a mask */
|
490 | c9f50cea | Michael S. Tsirkin | static inline void |
491 | c9f50cea | Michael S. Tsirkin | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) |
492 | c9f50cea | Michael S. Tsirkin | { |
493 | c9f50cea | Michael S. Tsirkin | uint8_t val = pci_get_byte(config); |
494 | c9f50cea | Michael S. Tsirkin | uint8_t rval = reg << (ffs(mask) - 1);
|
495 | c9f50cea | Michael S. Tsirkin | pci_set_byte(config, (~mask & val) | (mask & rval)); |
496 | c9f50cea | Michael S. Tsirkin | } |
497 | c9f50cea | Michael S. Tsirkin | |
498 | c9f50cea | Michael S. Tsirkin | static inline uint8_t |
499 | c9f50cea | Michael S. Tsirkin | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) |
500 | c9f50cea | Michael S. Tsirkin | { |
501 | c9f50cea | Michael S. Tsirkin | uint8_t val = pci_get_byte(config); |
502 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
503 | c9f50cea | Michael S. Tsirkin | } |
504 | c9f50cea | Michael S. Tsirkin | |
505 | c9f50cea | Michael S. Tsirkin | static inline void |
506 | c9f50cea | Michael S. Tsirkin | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) |
507 | c9f50cea | Michael S. Tsirkin | { |
508 | c9f50cea | Michael S. Tsirkin | uint16_t val = pci_get_word(config); |
509 | c9f50cea | Michael S. Tsirkin | uint16_t rval = reg << (ffs(mask) - 1);
|
510 | c9f50cea | Michael S. Tsirkin | pci_set_word(config, (~mask & val) | (mask & rval)); |
511 | c9f50cea | Michael S. Tsirkin | } |
512 | c9f50cea | Michael S. Tsirkin | |
513 | c9f50cea | Michael S. Tsirkin | static inline uint16_t |
514 | c9f50cea | Michael S. Tsirkin | pci_get_word_by_mask(uint8_t *config, uint16_t mask) |
515 | c9f50cea | Michael S. Tsirkin | { |
516 | c9f50cea | Michael S. Tsirkin | uint16_t val = pci_get_word(config); |
517 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
518 | c9f50cea | Michael S. Tsirkin | } |
519 | c9f50cea | Michael S. Tsirkin | |
520 | c9f50cea | Michael S. Tsirkin | static inline void |
521 | c9f50cea | Michael S. Tsirkin | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) |
522 | c9f50cea | Michael S. Tsirkin | { |
523 | c9f50cea | Michael S. Tsirkin | uint32_t val = pci_get_long(config); |
524 | c9f50cea | Michael S. Tsirkin | uint32_t rval = reg << (ffs(mask) - 1);
|
525 | c9f50cea | Michael S. Tsirkin | pci_set_long(config, (~mask & val) | (mask & rval)); |
526 | c9f50cea | Michael S. Tsirkin | } |
527 | c9f50cea | Michael S. Tsirkin | |
528 | c9f50cea | Michael S. Tsirkin | static inline uint32_t |
529 | c9f50cea | Michael S. Tsirkin | pci_get_long_by_mask(uint8_t *config, uint32_t mask) |
530 | c9f50cea | Michael S. Tsirkin | { |
531 | c9f50cea | Michael S. Tsirkin | uint32_t val = pci_get_long(config); |
532 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
533 | c9f50cea | Michael S. Tsirkin | } |
534 | c9f50cea | Michael S. Tsirkin | |
535 | c9f50cea | Michael S. Tsirkin | static inline void |
536 | c9f50cea | Michael S. Tsirkin | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) |
537 | c9f50cea | Michael S. Tsirkin | { |
538 | c9f50cea | Michael S. Tsirkin | uint64_t val = pci_get_quad(config); |
539 | c9f50cea | Michael S. Tsirkin | uint64_t rval = reg << (ffs(mask) - 1);
|
540 | c9f50cea | Michael S. Tsirkin | pci_set_quad(config, (~mask & val) | (mask & rval)); |
541 | c9f50cea | Michael S. Tsirkin | } |
542 | c9f50cea | Michael S. Tsirkin | |
543 | c9f50cea | Michael S. Tsirkin | static inline uint64_t |
544 | c9f50cea | Michael S. Tsirkin | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) |
545 | c9f50cea | Michael S. Tsirkin | { |
546 | c9f50cea | Michael S. Tsirkin | uint64_t val = pci_get_quad(config); |
547 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
548 | c9f50cea | Michael S. Tsirkin | } |
549 | c9f50cea | Michael S. Tsirkin | |
550 | 49823868 | Isaku Yamahata | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
551 | 49823868 | Isaku Yamahata | const char *name); |
552 | 49823868 | Isaku Yamahata | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
553 | 49823868 | Isaku Yamahata | bool multifunction,
|
554 | 49823868 | Isaku Yamahata | const char *name); |
555 | 499cf102 | Markus Armbruster | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
556 | 6b1b92d3 | Paul Brook | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
557 | 6b1b92d3 | Paul Brook | |
558 | 3c18685f | Isaku Yamahata | static inline int pci_is_express(const PCIDevice *d) |
559 | a9f49946 | Isaku Yamahata | { |
560 | a9f49946 | Isaku Yamahata | return d->cap_present & QEMU_PCI_CAP_EXPRESS;
|
561 | a9f49946 | Isaku Yamahata | } |
562 | a9f49946 | Isaku Yamahata | |
563 | 3c18685f | Isaku Yamahata | static inline uint32_t pci_config_size(const PCIDevice *d) |
564 | a9f49946 | Isaku Yamahata | { |
565 | a9f49946 | Isaku Yamahata | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
|
566 | a9f49946 | Isaku Yamahata | } |
567 | a9f49946 | Isaku Yamahata | |
568 | ec174575 | David Gibson | /* DMA access functions */
|
569 | d86a77f8 | David Gibson | static inline DMAContext *pci_dma_context(PCIDevice *dev) |
570 | d86a77f8 | David Gibson | { |
571 | 5fa45de5 | David Gibson | return dev->dma;
|
572 | d86a77f8 | David Gibson | } |
573 | d86a77f8 | David Gibson | |
574 | ec174575 | David Gibson | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
575 | ec174575 | David Gibson | void *buf, dma_addr_t len, DMADirection dir)
|
576 | ec174575 | David Gibson | { |
577 | d86a77f8 | David Gibson | dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir); |
578 | ec174575 | David Gibson | return 0; |
579 | ec174575 | David Gibson | } |
580 | ec174575 | David Gibson | |
581 | ec174575 | David Gibson | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, |
582 | ec174575 | David Gibson | void *buf, dma_addr_t len)
|
583 | ec174575 | David Gibson | { |
584 | ec174575 | David Gibson | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
|
585 | ec174575 | David Gibson | } |
586 | ec174575 | David Gibson | |
587 | ec174575 | David Gibson | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, |
588 | ec174575 | David Gibson | const void *buf, dma_addr_t len) |
589 | ec174575 | David Gibson | { |
590 | ec174575 | David Gibson | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); |
591 | ec174575 | David Gibson | } |
592 | ec174575 | David Gibson | |
593 | ec174575 | David Gibson | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
|
594 | ec174575 | David Gibson | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ |
595 | ec174575 | David Gibson | dma_addr_t addr) \ |
596 | ec174575 | David Gibson | { \ |
597 | d86a77f8 | David Gibson | return ld##_l##_dma(pci_dma_context(dev), addr); \ |
598 | ec174575 | David Gibson | } \ |
599 | ec174575 | David Gibson | static inline void st##_s##_pci_dma(PCIDevice *dev, \ |
600 | d86a77f8 | David Gibson | dma_addr_t addr, uint##_bits##_t val) \ |
601 | ec174575 | David Gibson | { \ |
602 | d86a77f8 | David Gibson | st##_s##_dma(pci_dma_context(dev), addr, val); \ |
603 | ec174575 | David Gibson | } |
604 | ec174575 | David Gibson | |
605 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(ub, b, 8);
|
606 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
|
607 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
|
608 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
|
609 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
|
610 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
|
611 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
|
612 | ec174575 | David Gibson | |
613 | ec174575 | David Gibson | #undef PCI_DMA_DEFINE_LDST
|
614 | ec174575 | David Gibson | |
615 | ec174575 | David Gibson | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, |
616 | ec174575 | David Gibson | dma_addr_t *plen, DMADirection dir) |
617 | ec174575 | David Gibson | { |
618 | ec174575 | David Gibson | void *buf;
|
619 | ec174575 | David Gibson | |
620 | d86a77f8 | David Gibson | buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir); |
621 | ec174575 | David Gibson | return buf;
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622 | ec174575 | David Gibson | } |
623 | ec174575 | David Gibson | |
624 | ec174575 | David Gibson | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, |
625 | ec174575 | David Gibson | DMADirection dir, dma_addr_t access_len) |
626 | ec174575 | David Gibson | { |
627 | d86a77f8 | David Gibson | dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len); |
628 | ec174575 | David Gibson | } |
629 | ec174575 | David Gibson | |
630 | ec174575 | David Gibson | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, |
631 | ec174575 | David Gibson | int alloc_hint)
|
632 | ec174575 | David Gibson | { |
633 | c65bcef3 | David Gibson | qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev)); |
634 | ec174575 | David Gibson | } |
635 | ec174575 | David Gibson | |
636 | 701a8f76 | Paolo Bonzini | extern const VMStateDescription vmstate_pci_device; |
637 | 701a8f76 | Paolo Bonzini | |
638 | 701a8f76 | Paolo Bonzini | #define VMSTATE_PCI_DEVICE(_field, _state) { \
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639 | 701a8f76 | Paolo Bonzini | .name = (stringify(_field)), \ |
640 | 701a8f76 | Paolo Bonzini | .size = sizeof(PCIDevice), \
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641 | 701a8f76 | Paolo Bonzini | .vmsd = &vmstate_pci_device, \ |
642 | 701a8f76 | Paolo Bonzini | .flags = VMS_STRUCT, \ |
643 | 701a8f76 | Paolo Bonzini | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ |
644 | 701a8f76 | Paolo Bonzini | } |
645 | 701a8f76 | Paolo Bonzini | |
646 | 701a8f76 | Paolo Bonzini | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
647 | 701a8f76 | Paolo Bonzini | .name = (stringify(_field)), \ |
648 | 701a8f76 | Paolo Bonzini | .size = sizeof(PCIDevice), \
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649 | 701a8f76 | Paolo Bonzini | .vmsd = &vmstate_pci_device, \ |
650 | 701a8f76 | Paolo Bonzini | .flags = VMS_STRUCT|VMS_POINTER, \ |
651 | 701a8f76 | Paolo Bonzini | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ |
652 | 701a8f76 | Paolo Bonzini | } |
653 | 701a8f76 | Paolo Bonzini | |
654 | 87ecb68b | pbrook | #endif |