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Name Size
  core-dc232b
  core-dc233c
  core-fsf
Makefile.objs 172 Bytes
core-dc232b.c 2.1 kB
core-dc233c.c 2.1 kB
core-fsf.c 2 kB
cpu-qom.h 2.6 kB
cpu.c 3 kB
cpu.h 13.7 kB
helper.c 19.1 kB
helper.h 2.3 kB
machine.c 1.7 kB
op_helper.c 25.8 kB
overlay_tool.h 16.9 kB
translate.c 94.4 kB
xtensa-semi.c 9.7 kB

Latest revisions

# Date Author Comment
0c4fabea 11/10/2012 03:49 pm Blue Swirl

target-xtensa: avoid using cpu_single_env

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl <>
Acked-by: Max Filippov <>
Reviewed-by: Andreas Färber <>
3993c6bd 10/31/2012 05:11 am Andreas Färber

cpus: Pass CPUState to [qemu_]cpu_has_work()

For target-mips also change the return type to bool.

Make include paths for cpu-qom.h consistent for alpha and unicore32.

Signed-off-by: Andreas Färber <>
[AF: Updated new target-openrisc function accordingly]...
f0de4132 10/28/2012 03:54 pm Aurelien Jarno

target-xtensa: rename helper flags

Rename helper flags to the new ones. This is purely a mechanical change,
it's possible to use better flags by looking at the helpers.

Cc: Max Filippov <>
Reviewed-by: Richard Henderson <>...
a8170e5e 10/23/2012 04:58 pm Avi Kivity

Rename target_phys_addr_t to hwaddr

target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,...
f783cb22 10/06/2012 01:22 pm Aurelien Jarno

target-xtensa: de-optimize EXTUI

Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shift
are optimized in tcg/tcg-op.h there is no need to do it in
target-xtensa/translate.c.

Acked-by: Max Filippov <>
Signed-off-by: Aurelien Jarno <>
fdefe51c 09/27/2012 10:38 pm Richard Henderson

Emit debug_insn for CPU_LOG_TB_OP_OPT as well.

For all targets that currently call tcg_gen_debug_insn_start,
add CPU_LOG_TB_OP_OPT to the condition that gates it.

This is useful for comparing optimization dumps, when the
pre-optimization dump is merely noise....
4e273869 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement FP1 group

These are comparison and conditional move opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
ef04a846 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement coprocessor context option

In case Coprocessor Context option is enabled CPENABLE SR bits control
whether access to coprocessors is allowed or would rise one of
CoprocessorXDisabled exceptions.

See ISA, 4.4.5 for more details.

FP is coprocessor 0....
0b6df838 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement FP0 arithmetic

These are FP arithmetic opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
b7ee8c6a 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement FP0 conversions

These are FP to integer and integer to FP conversion opcodes.
See ISA, 4.3.10 for more details.

Note that ISA description for utrunc.s is currently incorrect and will
be fixed in future revisions.

Signed-off-by: Max Filippov <>...

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