tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fastpath is taken, which leads to a crash. Fix that by using the a0 registerinstead.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: MMU: separate execute and read/write permissions
On SH4, the ITLB and UTLB configurations are memory mapped, so loadingITLB entries from UTLB has to be simulated correctly. For that the QEMUTLB has to be handle the execute (ITLB) and read/write permissions...
target-sh4: MMU: fix mem_idx computation
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to usermode (SR_MD = 0).
target-sh4: MMU: simplify call to tlb_set_page()
tlb_set_page() doesn't need addresses with offset, but simply thepage aligned addresses.
target-sh4: MMU: fix ITLB priviledge check
There is an ITLB access violation if SR_MD=0 (user mode) whilethe high bit of the protection key is 0 (priviledge mode).
target-sh4: MMU: optimize UTLB accesses
With the current code, the QEMU TLB is setup to match the read/writemode of the MMU fault. This means when read access is done, the pageis setup in read-only mode. When the page is later accessed in writemode, an MMU fault happened, and the page is switch in write-only...
target-sh4: MMU: reduce the size of a TLB entry
Reduce the size of the TLB entry from 32 to 16 bytes, reorganisingmembers and using a bit field.
target-sh4: MMU: remove dead code
target-sh4: MMU: fix store queue addresses
The store queues are located from 0xe0000000 to 0xe3ffffff.
sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should beflushed.
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