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cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
Signed-off-by: Andreas Färber <afaerber@suse.de>
misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memorytype. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes.See ISA, 4.3.10 for more details.
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status userregisters (fcr, fsr).
See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes.See ISA, 4.3.10 for more details.
Note that ISA description for utrunc.s is currently incorrect and willbe fixed in future revisions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: switch to AREG0-free mode
Add env parameter to every helper function that needs it, update'configure' script.
target-xtensa: flush TLB page for new MMU mapping
Both old and new mappings need flushing because their VPN may bedifferent in MMU case.
target-xtensa: extract TLB entry setting method
target-xtensa: update autorefill TLB entries conditionally
This is to avoid interference of internal QEMU helpers(cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visibleTLB state.
target-xtensa: fix tb invalidation for IBREAK and LOOP
Instruction breakpoint/zero overhead loop handling code is built intoTBs pointed to by IBREAKA/LEND SRs. When these or related SRs getchanged TBs at virtual addresses corresponding to their old and their...
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: Move helpers.h to helper.h
Provides a file naming scheme consistent with other targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
target-xtensa: add DBREAK data breakpoints
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debugwatchpoints.
This implementation is not fully compliant to ISA: when a breakpoint isset to an unmapped/inaccessible memory address it generates TLB/memory...
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK andBREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
target-xtensa: fix guest hang on masked CCOMPARE interrupt
QEMU timer is used to post CCOMPARE interrupt when the core is halted.If that CCOMPARE interrupt is masked off then the timer must be rearmedin the callback, otherwise it will be rearmed next time the core goes to...
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields inCPUEnv. Only current window is accessible to TCG. On operations thatchange window base helpers copy current window to and from physical...
target-xtensa: implement loop option
See ISA, 4.3.2 for details.
Operations that change LEND SR value invalidate TBs at the old and atthe new LEND. LEND value at TB compilation time is considered constantand loop instruction is generated based on this value....
target-xtensa: implement unaligned exception option
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generatedin case this option is not enabled.
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA;- RST1: shifts, 16-bit multiplication.
target-xtensa: implement exceptions
- mark privileged opcodes with ring check;- make debug exception on exception handler entry.
target-xtensa: add target stubs
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.