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Name Size
  core-dc232b
  core-dc233c
  core-fsf
Makefile.objs 172 Bytes
core-dc232b.c 2.1 kB
core-dc233c.c 2.1 kB
core-fsf.c 2 kB
cpu-qom.h 2.6 kB
cpu.c 3 kB
cpu.h 13.6 kB
helper.c 19.1 kB
helper.h 2.4 kB
machine.c 1.7 kB
op_helper.c 25.8 kB
overlay_tool.h 16.9 kB
translate.c 94.9 kB
xtensa-semi.c 9.7 kB

Latest revisions

# Date Author Comment
4e273869 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement FP1 group

These are comparison and conditional move opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
ef04a846 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement coprocessor context option

In case Coprocessor Context option is enabled CPENABLE SR bits control
whether access to coprocessors is allowed or would rise one of
CoprocessorXDisabled exceptions.

See ISA, 4.4.5 for more details.

FP is coprocessor 0....
10f6ca03 09/22/2012 08:59 pm Max Filippov

target-xtensa: handle boolean option in overlays

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
dd519cbe 09/22/2012 08:59 pm Max Filippov

target-xtensa: add FP registers

There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).

See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
9ed7ae12 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement LSCX and LSCI groups

These are load/store instructions for FP registers with immediate or
register index and optional base post-update.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
0b6df838 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement FP0 arithmetic

These are FP arithmetic opcodes.
See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
b7ee8c6a 09/22/2012 08:59 pm Max Filippov

target-xtensa: implement FP0 conversions

These are FP to integer and integer to FP conversion opcodes.
See ISA, 4.3.10 for more details.

Note that ISA description for utrunc.s is currently incorrect and will
be fixed in future revisions.

Signed-off-by: Max Filippov <>...
f9cb5045 09/21/2012 02:07 am Max Filippov

target-xtensa: fix extui shift amount

extui opcode only uses lowermost op1 bit for sa4.

Reported-by: malc <>
Signed-off-by: Max Filippov <>
Cc: qemu-stable <>
Signed-off-by: malc <>
c26032b2 09/21/2012 02:07 am Max Filippov

target-xtensa: don't emit extra tcg_gen_goto_tb

Unconditional gen_check_loop_end at the end of disas_xtensa_insn
can emit tcg_gen_goto_tb with slot id already used in the TB (e.g. when
TB ends at LEND with a branch).

Signed-off-by: Max Filippov <>...
c29b1bee 09/08/2012 11:46 am Max Filippov

target-xtensa: fix missing errno codes for mingw32

Put the following errno value mappings under #ifdef:

xtensa-semi.c: In function 'errno_h2g':
xtensa-semi.c:113: error: 'ENOTBLK' undeclared (first use in this function)
xtensa-semi.c:113: error: (Each undeclared identifier is reported only once...

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