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root / target-ppc @ dc364f4c

Name Size
Makefile.objs 455 Bytes
STATUS 10.6 kB
arch_dump.c 6.5 kB
cpu-models.c 64.4 kB
cpu-models.h 29.8 kB
cpu-qom.h 3.6 kB
cpu.h 87.5 kB
excp_helper.c 34.7 kB
fpu_helper.c 48.5 kB
gdbstub.c 3.8 kB
helper.h 15.9 kB
helper_regs.h 3.4 kB
int_helper.c 52.8 kB
kvm-stub.c 400 Bytes
kvm.c 51.7 kB
kvm_ppc.c 1.2 kB
kvm_ppc.h 4.8 kB
machine.c 14.8 kB
mem_helper.c 8.3 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 653 Bytes
misc_helper.c 3.5 kB
mmu-hash32.c 16 kB
mmu-hash32.h 3.2 kB
mmu-hash64.c 15.4 kB
mmu-hash64.h 4.5 kB
mmu_helper.c 88.4 kB
timebase_helper.c 4.3 kB
translate.c 388 kB
translate_init.c 306.1 kB
user_only_helper.c 1.4 kB

Latest revisions

# Date Author Comment
f976b09e 12/22/2013 08:15 pm Alexander Graf

PPC: Fix compilation with TCG debug

The recent VSX patches broken compilation of QEMU when configurated
with --enable-debug, as it was treating "target long" TCG variables
as "i64" which is not true for 32bit targets.

This patch fixes all the places that the compiler has found to use...
c2b63f03 12/20/2013 02:58 am Alexander Graf

PPC: Add VSX to hflags

We generate different code depending on whether MSR_VSX is set or
clear, so it needs to be part of our hflags too which indicate whether
we're still in the same translation block cache bucket.

Signed-off-by: Alexander Graf <>
acc42968 12/20/2013 02:58 am Tom Musta

Add xxsldwi

This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Alexander Graf <>
76c15fe0 12/20/2013 02:58 am Tom Musta

Add xxspltw

This patch adds the VSX Splat Word (xxsplatw) instruction.

This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.

V2: reworked implementation per Richard Henderson's comments.

Signed-off-by: Tom Musta <>...
551e3ef7 12/20/2013 02:58 am Tom Musta

Add xxsel

This patch adds the VSX Select (xxsel) instruction.

The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.

The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This...
79ca8a6a 12/20/2013 02:58 am Tom Musta

Add Power7 VSX Logical Instructions

This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):

- xxland
   - xxlandc
   - xxlor
   - xxlxor
   - xxlnor

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
ce577d2e 12/20/2013 02:58 am Tom Musta

Add xxmrgh/xxmrgl

This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.

V2: Now implemented using deposit (per Richard Henderson's comment)

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
be574920 12/20/2013 02:58 am Tom Musta

Add VSX Vector Move Instructions

This patch adds the vector move instructions:

- xvabsdp - Vector Absolute Value Double-Precision
  - xvnabsdp - Vector Negative Absolute Value Double-Precision
  - xvnegdp - Vector Negate Double-Precision
  - xvcpsgndp - Vector Copy Sign Double-Precision...
df020ce0 12/20/2013 02:58 am Tom Musta

Add VSX Scalar Move Instructions

This patch adds the VSX scalar move instructions:

- xsabsdp (Scalar Absolute Value Double-Precision)
  - xsnabspd (Scalar Negative Absolute Value Double-Precision)
  - xsnegdp (Scalar Negate Double-Precision)
  - xscpsgndp (Scalar Copy Sign Double-Precision)...
b650d6a2 12/20/2013 02:57 am Alexey Kardashevskiy

target-ppc: move POWER7+ to a separate family

So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR masks, it needs a separate
family class.

This adds a new family class, PVR base and mask values and moves...

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