root / target-sparc / op_helper.c @ e1ef36c4
History | View | Annotate | Download (117.3 kB)
1 | e8af50a3 | bellard | #include "exec.h" |
---|---|---|---|
2 | eed152bb | blueswir1 | #include "host-utils.h" |
3 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
4 | b04d9890 | Fabien Chouteau | #include "sysemu.h" |
5 | e8af50a3 | bellard | |
6 | e80cfcfc | bellard | //#define DEBUG_MMU
|
7 | 952a328f | blueswir1 | //#define DEBUG_MXCC
|
8 | 94554550 | blueswir1 | //#define DEBUG_UNALIGNED
|
9 | 6c36d3fa | blueswir1 | //#define DEBUG_UNASSIGNED
|
10 | 8543e2cf | blueswir1 | //#define DEBUG_ASI
|
11 | d81fd722 | blueswir1 | //#define DEBUG_PCALL
|
12 | 7e8695ed | Igor V. Kovalenko | //#define DEBUG_PSTATE
|
13 | b04d9890 | Fabien Chouteau | //#define DEBUG_CACHE_CONTROL
|
14 | e80cfcfc | bellard | |
15 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
16 | 001faf32 | Blue Swirl | #define DPRINTF_MMU(fmt, ...) \
|
17 | 001faf32 | Blue Swirl | do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) |
18 | 952a328f | blueswir1 | #else
|
19 | 001faf32 | Blue Swirl | #define DPRINTF_MMU(fmt, ...) do {} while (0) |
20 | 952a328f | blueswir1 | #endif
|
21 | 952a328f | blueswir1 | |
22 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
23 | 001faf32 | Blue Swirl | #define DPRINTF_MXCC(fmt, ...) \
|
24 | 001faf32 | Blue Swirl | do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0) |
25 | 952a328f | blueswir1 | #else
|
26 | 001faf32 | Blue Swirl | #define DPRINTF_MXCC(fmt, ...) do {} while (0) |
27 | 952a328f | blueswir1 | #endif
|
28 | 952a328f | blueswir1 | |
29 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
30 | 001faf32 | Blue Swirl | #define DPRINTF_ASI(fmt, ...) \
|
31 | 001faf32 | Blue Swirl | do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) |
32 | 8543e2cf | blueswir1 | #endif
|
33 | 8543e2cf | blueswir1 | |
34 | 7e8695ed | Igor V. Kovalenko | #ifdef DEBUG_PSTATE
|
35 | 7e8695ed | Igor V. Kovalenko | #define DPRINTF_PSTATE(fmt, ...) \
|
36 | 7e8695ed | Igor V. Kovalenko | do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) |
37 | 7e8695ed | Igor V. Kovalenko | #else
|
38 | 7e8695ed | Igor V. Kovalenko | #define DPRINTF_PSTATE(fmt, ...) do {} while (0) |
39 | 7e8695ed | Igor V. Kovalenko | #endif
|
40 | 7e8695ed | Igor V. Kovalenko | |
41 | b04d9890 | Fabien Chouteau | #ifdef DEBUG_CACHE_CONTROL
|
42 | b04d9890 | Fabien Chouteau | #define DPRINTF_CACHE_CONTROL(fmt, ...) \
|
43 | b04d9890 | Fabien Chouteau | do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) |
44 | b04d9890 | Fabien Chouteau | #else
|
45 | b04d9890 | Fabien Chouteau | #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) |
46 | b04d9890 | Fabien Chouteau | #endif
|
47 | b04d9890 | Fabien Chouteau | |
48 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
49 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
|
50 | 2cade6a3 | blueswir1 | #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
|
51 | c2bc0e38 | blueswir1 | #else
|
52 | 2cade6a3 | blueswir1 | #define AM_CHECK(env1) (1) |
53 | 2cade6a3 | blueswir1 | #endif
|
54 | c2bc0e38 | blueswir1 | #endif
|
55 | c2bc0e38 | blueswir1 | |
56 | 21ffd181 | Blue Swirl | #define DT0 (env->dt0)
|
57 | 21ffd181 | Blue Swirl | #define DT1 (env->dt1)
|
58 | 21ffd181 | Blue Swirl | #define QT0 (env->qt0)
|
59 | 21ffd181 | Blue Swirl | #define QT1 (env->qt1)
|
60 | 21ffd181 | Blue Swirl | |
61 | b04d9890 | Fabien Chouteau | /* Leon3 cache control */
|
62 | b04d9890 | Fabien Chouteau | |
63 | b04d9890 | Fabien Chouteau | /* Cache control: emulate the behavior of cache control registers but without
|
64 | b04d9890 | Fabien Chouteau | any effect on the emulated */
|
65 | b04d9890 | Fabien Chouteau | |
66 | b04d9890 | Fabien Chouteau | #define CACHE_STATE_MASK 0x3 |
67 | b04d9890 | Fabien Chouteau | #define CACHE_DISABLED 0x0 |
68 | b04d9890 | Fabien Chouteau | #define CACHE_FROZEN 0x1 |
69 | b04d9890 | Fabien Chouteau | #define CACHE_ENABLED 0x3 |
70 | b04d9890 | Fabien Chouteau | |
71 | b04d9890 | Fabien Chouteau | /* Cache Control register fields */
|
72 | b04d9890 | Fabien Chouteau | |
73 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ |
74 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ |
75 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ |
76 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ |
77 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ |
78 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ |
79 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ |
80 | b04d9890 | Fabien Chouteau | #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ |
81 | b04d9890 | Fabien Chouteau | |
82 | 3c7b48b7 | Paul Brook | #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
83 | 3c7b48b7 | Paul Brook | static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
84 | 3c7b48b7 | Paul Brook | int is_asi, int size); |
85 | 3c7b48b7 | Paul Brook | #endif
|
86 | 3c7b48b7 | Paul Brook | |
87 | 9c22a623 | Blue Swirl | #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
88 | 697a77e6 | Igor Kovalenko | // Calculates TSB pointer value for fault page size 8k or 64k
|
89 | 697a77e6 | Igor Kovalenko | static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
|
90 | 697a77e6 | Igor Kovalenko | uint64_t tag_access_register, |
91 | 697a77e6 | Igor Kovalenko | int page_size)
|
92 | 697a77e6 | Igor Kovalenko | { |
93 | 697a77e6 | Igor Kovalenko | uint64_t tsb_base = tsb_register & ~0x1fffULL;
|
94 | 6e8e7d4c | Igor Kovalenko | int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0; |
95 | 6e8e7d4c | Igor Kovalenko | int tsb_size = tsb_register & 0xf; |
96 | 697a77e6 | Igor Kovalenko | |
97 | 697a77e6 | Igor Kovalenko | // discard lower 13 bits which hold tag access context
|
98 | 697a77e6 | Igor Kovalenko | uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
|
99 | 697a77e6 | Igor Kovalenko | |
100 | 697a77e6 | Igor Kovalenko | // now reorder bits
|
101 | 697a77e6 | Igor Kovalenko | uint64_t tsb_base_mask = ~0x1fffULL;
|
102 | 697a77e6 | Igor Kovalenko | uint64_t va = tag_access_va; |
103 | 697a77e6 | Igor Kovalenko | |
104 | 697a77e6 | Igor Kovalenko | // move va bits to correct position
|
105 | 697a77e6 | Igor Kovalenko | if (page_size == 8*1024) { |
106 | 697a77e6 | Igor Kovalenko | va >>= 9;
|
107 | 697a77e6 | Igor Kovalenko | } else if (page_size == 64*1024) { |
108 | 697a77e6 | Igor Kovalenko | va >>= 12;
|
109 | 697a77e6 | Igor Kovalenko | } |
110 | 697a77e6 | Igor Kovalenko | |
111 | 697a77e6 | Igor Kovalenko | if (tsb_size) {
|
112 | 697a77e6 | Igor Kovalenko | tsb_base_mask <<= tsb_size; |
113 | 697a77e6 | Igor Kovalenko | } |
114 | 697a77e6 | Igor Kovalenko | |
115 | 697a77e6 | Igor Kovalenko | // calculate tsb_base mask and adjust va if split is in use
|
116 | 697a77e6 | Igor Kovalenko | if (tsb_split) {
|
117 | 697a77e6 | Igor Kovalenko | if (page_size == 8*1024) { |
118 | 697a77e6 | Igor Kovalenko | va &= ~(1ULL << (13 + tsb_size)); |
119 | 697a77e6 | Igor Kovalenko | } else if (page_size == 64*1024) { |
120 | 697a77e6 | Igor Kovalenko | va |= (1ULL << (13 + tsb_size)); |
121 | 697a77e6 | Igor Kovalenko | } |
122 | 697a77e6 | Igor Kovalenko | tsb_base_mask <<= 1;
|
123 | 697a77e6 | Igor Kovalenko | } |
124 | 697a77e6 | Igor Kovalenko | |
125 | 697a77e6 | Igor Kovalenko | return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL; |
126 | 697a77e6 | Igor Kovalenko | } |
127 | 697a77e6 | Igor Kovalenko | |
128 | 697a77e6 | Igor Kovalenko | // Calculates tag target register value by reordering bits
|
129 | 697a77e6 | Igor Kovalenko | // in tag access register
|
130 | 697a77e6 | Igor Kovalenko | static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
|
131 | 697a77e6 | Igor Kovalenko | { |
132 | 697a77e6 | Igor Kovalenko | return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22); |
133 | 697a77e6 | Igor Kovalenko | } |
134 | 697a77e6 | Igor Kovalenko | |
135 | f707726e | Igor Kovalenko | static void replace_tlb_entry(SparcTLBEntry *tlb, |
136 | f707726e | Igor Kovalenko | uint64_t tlb_tag, uint64_t tlb_tte, |
137 | f707726e | Igor Kovalenko | CPUState *env1) |
138 | 6e8e7d4c | Igor Kovalenko | { |
139 | 6e8e7d4c | Igor Kovalenko | target_ulong mask, size, va, offset; |
140 | 6e8e7d4c | Igor Kovalenko | |
141 | 6e8e7d4c | Igor Kovalenko | // flush page range if translation is valid
|
142 | f707726e | Igor Kovalenko | if (TTE_IS_VALID(tlb->tte)) {
|
143 | 6e8e7d4c | Igor Kovalenko | |
144 | 6e8e7d4c | Igor Kovalenko | mask = 0xffffffffffffe000ULL;
|
145 | 6e8e7d4c | Igor Kovalenko | mask <<= 3 * ((tlb->tte >> 61) & 3); |
146 | 6e8e7d4c | Igor Kovalenko | size = ~mask + 1;
|
147 | 6e8e7d4c | Igor Kovalenko | |
148 | 6e8e7d4c | Igor Kovalenko | va = tlb->tag & mask; |
149 | 6e8e7d4c | Igor Kovalenko | |
150 | 6e8e7d4c | Igor Kovalenko | for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) { |
151 | 6e8e7d4c | Igor Kovalenko | tlb_flush_page(env1, va + offset); |
152 | 6e8e7d4c | Igor Kovalenko | } |
153 | 6e8e7d4c | Igor Kovalenko | } |
154 | 6e8e7d4c | Igor Kovalenko | |
155 | 6e8e7d4c | Igor Kovalenko | tlb->tag = tlb_tag; |
156 | 6e8e7d4c | Igor Kovalenko | tlb->tte = tlb_tte; |
157 | 6e8e7d4c | Igor Kovalenko | } |
158 | 6e8e7d4c | Igor Kovalenko | |
159 | 6e8e7d4c | Igor Kovalenko | static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, |
160 | f707726e | Igor Kovalenko | const char* strmmu, CPUState *env1) |
161 | 6e8e7d4c | Igor Kovalenko | { |
162 | 6e8e7d4c | Igor Kovalenko | unsigned int i; |
163 | 6e8e7d4c | Igor Kovalenko | target_ulong mask; |
164 | 299b520c | Igor V. Kovalenko | uint64_t context; |
165 | 299b520c | Igor V. Kovalenko | |
166 | 299b520c | Igor V. Kovalenko | int is_demap_context = (demap_addr >> 6) & 1; |
167 | 299b520c | Igor V. Kovalenko | |
168 | 299b520c | Igor V. Kovalenko | // demap context
|
169 | 299b520c | Igor V. Kovalenko | switch ((demap_addr >> 4) & 3) { |
170 | 299b520c | Igor V. Kovalenko | case 0: // primary |
171 | 299b520c | Igor V. Kovalenko | context = env1->dmmu.mmu_primary_context; |
172 | 299b520c | Igor V. Kovalenko | break;
|
173 | 299b520c | Igor V. Kovalenko | case 1: // secondary |
174 | 299b520c | Igor V. Kovalenko | context = env1->dmmu.mmu_secondary_context; |
175 | 299b520c | Igor V. Kovalenko | break;
|
176 | 299b520c | Igor V. Kovalenko | case 2: // nucleus |
177 | 299b520c | Igor V. Kovalenko | context = 0;
|
178 | 299b520c | Igor V. Kovalenko | break;
|
179 | 299b520c | Igor V. Kovalenko | case 3: // reserved |
180 | 299b520c | Igor V. Kovalenko | default:
|
181 | 299b520c | Igor V. Kovalenko | return;
|
182 | 299b520c | Igor V. Kovalenko | } |
183 | 6e8e7d4c | Igor Kovalenko | |
184 | 6e8e7d4c | Igor Kovalenko | for (i = 0; i < 64; i++) { |
185 | f707726e | Igor Kovalenko | if (TTE_IS_VALID(tlb[i].tte)) {
|
186 | 6e8e7d4c | Igor Kovalenko | |
187 | 299b520c | Igor V. Kovalenko | if (is_demap_context) {
|
188 | 299b520c | Igor V. Kovalenko | // will remove non-global entries matching context value
|
189 | 299b520c | Igor V. Kovalenko | if (TTE_IS_GLOBAL(tlb[i].tte) ||
|
190 | 299b520c | Igor V. Kovalenko | !tlb_compare_context(&tlb[i], context)) { |
191 | 299b520c | Igor V. Kovalenko | continue;
|
192 | 299b520c | Igor V. Kovalenko | } |
193 | 299b520c | Igor V. Kovalenko | } else {
|
194 | 299b520c | Igor V. Kovalenko | // demap page
|
195 | 299b520c | Igor V. Kovalenko | // will remove any entry matching VA
|
196 | 299b520c | Igor V. Kovalenko | mask = 0xffffffffffffe000ULL;
|
197 | 299b520c | Igor V. Kovalenko | mask <<= 3 * ((tlb[i].tte >> 61) & 3); |
198 | 299b520c | Igor V. Kovalenko | |
199 | 299b520c | Igor V. Kovalenko | if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
|
200 | 299b520c | Igor V. Kovalenko | continue;
|
201 | 299b520c | Igor V. Kovalenko | } |
202 | 299b520c | Igor V. Kovalenko | |
203 | 299b520c | Igor V. Kovalenko | // entry should be global or matching context value
|
204 | 299b520c | Igor V. Kovalenko | if (!TTE_IS_GLOBAL(tlb[i].tte) &&
|
205 | 299b520c | Igor V. Kovalenko | !tlb_compare_context(&tlb[i], context)) { |
206 | 299b520c | Igor V. Kovalenko | continue;
|
207 | 299b520c | Igor V. Kovalenko | } |
208 | 299b520c | Igor V. Kovalenko | } |
209 | 6e8e7d4c | Igor Kovalenko | |
210 | 299b520c | Igor V. Kovalenko | replace_tlb_entry(&tlb[i], 0, 0, env1); |
211 | 6e8e7d4c | Igor Kovalenko | #ifdef DEBUG_MMU
|
212 | 299b520c | Igor V. Kovalenko | DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
|
213 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env1); |
214 | 6e8e7d4c | Igor Kovalenko | #endif
|
215 | 6e8e7d4c | Igor Kovalenko | } |
216 | 6e8e7d4c | Igor Kovalenko | } |
217 | 6e8e7d4c | Igor Kovalenko | } |
218 | 6e8e7d4c | Igor Kovalenko | |
219 | f707726e | Igor Kovalenko | static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, |
220 | f707726e | Igor Kovalenko | uint64_t tlb_tag, uint64_t tlb_tte, |
221 | f707726e | Igor Kovalenko | const char* strmmu, CPUState *env1) |
222 | f707726e | Igor Kovalenko | { |
223 | f707726e | Igor Kovalenko | unsigned int i, replace_used; |
224 | f707726e | Igor Kovalenko | |
225 | f707726e | Igor Kovalenko | // Try replacing invalid entry
|
226 | f707726e | Igor Kovalenko | for (i = 0; i < 64; i++) { |
227 | f707726e | Igor Kovalenko | if (!TTE_IS_VALID(tlb[i].tte)) {
|
228 | f707726e | Igor Kovalenko | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
229 | f707726e | Igor Kovalenko | #ifdef DEBUG_MMU
|
230 | f707726e | Igor Kovalenko | DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
|
231 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env1); |
232 | f707726e | Igor Kovalenko | #endif
|
233 | f707726e | Igor Kovalenko | return;
|
234 | f707726e | Igor Kovalenko | } |
235 | f707726e | Igor Kovalenko | } |
236 | f707726e | Igor Kovalenko | |
237 | f707726e | Igor Kovalenko | // All entries are valid, try replacing unlocked entry
|
238 | f707726e | Igor Kovalenko | |
239 | f707726e | Igor Kovalenko | for (replace_used = 0; replace_used < 2; ++replace_used) { |
240 | f707726e | Igor Kovalenko | |
241 | f707726e | Igor Kovalenko | // Used entries are not replaced on first pass
|
242 | f707726e | Igor Kovalenko | |
243 | f707726e | Igor Kovalenko | for (i = 0; i < 64; i++) { |
244 | f707726e | Igor Kovalenko | if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
|
245 | f707726e | Igor Kovalenko | |
246 | f707726e | Igor Kovalenko | replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); |
247 | f707726e | Igor Kovalenko | #ifdef DEBUG_MMU
|
248 | f707726e | Igor Kovalenko | DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
|
249 | f707726e | Igor Kovalenko | strmmu, (replace_used?"used":"unused"), i); |
250 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env1); |
251 | f707726e | Igor Kovalenko | #endif
|
252 | f707726e | Igor Kovalenko | return;
|
253 | f707726e | Igor Kovalenko | } |
254 | f707726e | Igor Kovalenko | } |
255 | f707726e | Igor Kovalenko | |
256 | f707726e | Igor Kovalenko | // Now reset used bit and search for unused entries again
|
257 | f707726e | Igor Kovalenko | |
258 | f707726e | Igor Kovalenko | for (i = 0; i < 64; i++) { |
259 | f707726e | Igor Kovalenko | TTE_SET_UNUSED(tlb[i].tte); |
260 | f707726e | Igor Kovalenko | } |
261 | f707726e | Igor Kovalenko | } |
262 | f707726e | Igor Kovalenko | |
263 | f707726e | Igor Kovalenko | #ifdef DEBUG_MMU
|
264 | f707726e | Igor Kovalenko | DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
|
265 | f707726e | Igor Kovalenko | #endif
|
266 | f707726e | Igor Kovalenko | // error state?
|
267 | f707726e | Igor Kovalenko | } |
268 | f707726e | Igor Kovalenko | |
269 | 697a77e6 | Igor Kovalenko | #endif
|
270 | 697a77e6 | Igor Kovalenko | |
271 | 41db525e | Richard Henderson | static inline target_ulong address_mask(CPUState *env1, target_ulong addr) |
272 | 2cade6a3 | blueswir1 | { |
273 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
274 | 2cade6a3 | blueswir1 | if (AM_CHECK(env1))
|
275 | 41db525e | Richard Henderson | addr &= 0xffffffffULL;
|
276 | 2cade6a3 | blueswir1 | #endif
|
277 | 41db525e | Richard Henderson | return addr;
|
278 | 2cade6a3 | blueswir1 | } |
279 | 2cade6a3 | blueswir1 | |
280 | 1295001c | Igor V. Kovalenko | /* returns true if access using this ASI is to have address translated by MMU
|
281 | 1295001c | Igor V. Kovalenko | otherwise access is to raw physical address */
|
282 | 1295001c | Igor V. Kovalenko | static inline int is_translating_asi(int asi) |
283 | 1295001c | Igor V. Kovalenko | { |
284 | 1295001c | Igor V. Kovalenko | #ifdef TARGET_SPARC64
|
285 | 1295001c | Igor V. Kovalenko | /* Ultrasparc IIi translating asi
|
286 | 1295001c | Igor V. Kovalenko | - note this list is defined by cpu implementation
|
287 | 1295001c | Igor V. Kovalenko | */
|
288 | 1295001c | Igor V. Kovalenko | switch (asi) {
|
289 | 1295001c | Igor V. Kovalenko | case 0x04 ... 0x11: |
290 | 1295001c | Igor V. Kovalenko | case 0x18 ... 0x19: |
291 | 1295001c | Igor V. Kovalenko | case 0x24 ... 0x2C: |
292 | 1295001c | Igor V. Kovalenko | case 0x70 ... 0x73: |
293 | 1295001c | Igor V. Kovalenko | case 0x78 ... 0x79: |
294 | 1295001c | Igor V. Kovalenko | case 0x80 ... 0xFF: |
295 | 1295001c | Igor V. Kovalenko | return 1; |
296 | 1295001c | Igor V. Kovalenko | |
297 | 1295001c | Igor V. Kovalenko | default:
|
298 | 1295001c | Igor V. Kovalenko | return 0; |
299 | 1295001c | Igor V. Kovalenko | } |
300 | 1295001c | Igor V. Kovalenko | #else
|
301 | 1295001c | Igor V. Kovalenko | /* TODO: check sparc32 bits */
|
302 | 1295001c | Igor V. Kovalenko | return 0; |
303 | 1295001c | Igor V. Kovalenko | #endif
|
304 | 1295001c | Igor V. Kovalenko | } |
305 | 1295001c | Igor V. Kovalenko | |
306 | 1295001c | Igor V. Kovalenko | static inline target_ulong asi_address_mask(CPUState *env1, |
307 | 1295001c | Igor V. Kovalenko | int asi, target_ulong addr)
|
308 | 1295001c | Igor V. Kovalenko | { |
309 | 1295001c | Igor V. Kovalenko | if (is_translating_asi(asi)) {
|
310 | 1295001c | Igor V. Kovalenko | return address_mask(env, addr);
|
311 | 1295001c | Igor V. Kovalenko | } else {
|
312 | 1295001c | Igor V. Kovalenko | return addr;
|
313 | 1295001c | Igor V. Kovalenko | } |
314 | 1295001c | Igor V. Kovalenko | } |
315 | 1295001c | Igor V. Kovalenko | |
316 | f4a5a5ba | blueswir1 | static void raise_exception(int tt) |
317 | 9d893301 | bellard | { |
318 | 9d893301 | bellard | env->exception_index = tt; |
319 | 1162c041 | Blue Swirl | cpu_loop_exit(env); |
320 | 3b46e624 | ths | } |
321 | 9d893301 | bellard | |
322 | a7812ae4 | pbrook | void HELPER(raise_exception)(int tt) |
323 | a7812ae4 | pbrook | { |
324 | a7812ae4 | pbrook | raise_exception(tt); |
325 | a7812ae4 | pbrook | } |
326 | a7812ae4 | pbrook | |
327 | b04d9890 | Fabien Chouteau | void helper_shutdown(void) |
328 | b04d9890 | Fabien Chouteau | { |
329 | b04d9890 | Fabien Chouteau | #if !defined(CONFIG_USER_ONLY)
|
330 | b04d9890 | Fabien Chouteau | qemu_system_shutdown_request(); |
331 | b04d9890 | Fabien Chouteau | #endif
|
332 | b04d9890 | Fabien Chouteau | } |
333 | b04d9890 | Fabien Chouteau | |
334 | 2b29924f | blueswir1 | void helper_check_align(target_ulong addr, uint32_t align)
|
335 | 2b29924f | blueswir1 | { |
336 | c2bc0e38 | blueswir1 | if (addr & align) {
|
337 | c2bc0e38 | blueswir1 | #ifdef DEBUG_UNALIGNED
|
338 | c2bc0e38 | blueswir1 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
339 | c2bc0e38 | blueswir1 | "\n", addr, env->pc);
|
340 | c2bc0e38 | blueswir1 | #endif
|
341 | 2b29924f | blueswir1 | raise_exception(TT_UNALIGNED); |
342 | c2bc0e38 | blueswir1 | } |
343 | 2b29924f | blueswir1 | } |
344 | 2b29924f | blueswir1 | |
345 | 44e7757c | blueswir1 | #define F_HELPER(name, p) void helper_f##name##p(void) |
346 | 44e7757c | blueswir1 | |
347 | 44e7757c | blueswir1 | #define F_BINOP(name) \
|
348 | 714547bb | blueswir1 | float32 helper_f ## name ## s (float32 src1, float32 src2) \ |
349 | 44e7757c | blueswir1 | { \ |
350 | 714547bb | blueswir1 | return float32_ ## name (src1, src2, &env->fp_status); \ |
351 | 44e7757c | blueswir1 | } \ |
352 | 44e7757c | blueswir1 | F_HELPER(name, d) \ |
353 | 44e7757c | blueswir1 | { \ |
354 | 44e7757c | blueswir1 | DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \ |
355 | 4e14008f | blueswir1 | } \ |
356 | 4e14008f | blueswir1 | F_HELPER(name, q) \ |
357 | 4e14008f | blueswir1 | { \ |
358 | 4e14008f | blueswir1 | QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \ |
359 | 44e7757c | blueswir1 | } |
360 | 44e7757c | blueswir1 | |
361 | 44e7757c | blueswir1 | F_BINOP(add); |
362 | 44e7757c | blueswir1 | F_BINOP(sub); |
363 | 44e7757c | blueswir1 | F_BINOP(mul); |
364 | 44e7757c | blueswir1 | F_BINOP(div); |
365 | 44e7757c | blueswir1 | #undef F_BINOP
|
366 | 44e7757c | blueswir1 | |
367 | d84763bc | blueswir1 | void helper_fsmuld(float32 src1, float32 src2)
|
368 | 1a2fb1c0 | blueswir1 | { |
369 | d84763bc | blueswir1 | DT0 = float64_mul(float32_to_float64(src1, &env->fp_status), |
370 | d84763bc | blueswir1 | float32_to_float64(src2, &env->fp_status), |
371 | 44e7757c | blueswir1 | &env->fp_status); |
372 | 44e7757c | blueswir1 | } |
373 | 1a2fb1c0 | blueswir1 | |
374 | 4e14008f | blueswir1 | void helper_fdmulq(void) |
375 | 4e14008f | blueswir1 | { |
376 | 4e14008f | blueswir1 | QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status), |
377 | 4e14008f | blueswir1 | float64_to_float128(DT1, &env->fp_status), |
378 | 4e14008f | blueswir1 | &env->fp_status); |
379 | 4e14008f | blueswir1 | } |
380 | 4e14008f | blueswir1 | |
381 | 714547bb | blueswir1 | float32 helper_fnegs(float32 src) |
382 | 44e7757c | blueswir1 | { |
383 | 714547bb | blueswir1 | return float32_chs(src);
|
384 | 417454b0 | blueswir1 | } |
385 | 417454b0 | blueswir1 | |
386 | 44e7757c | blueswir1 | #ifdef TARGET_SPARC64
|
387 | 44e7757c | blueswir1 | F_HELPER(neg, d) |
388 | 7e8c2b6c | blueswir1 | { |
389 | 44e7757c | blueswir1 | DT0 = float64_chs(DT1); |
390 | 7e8c2b6c | blueswir1 | } |
391 | 4e14008f | blueswir1 | |
392 | 4e14008f | blueswir1 | F_HELPER(neg, q) |
393 | 4e14008f | blueswir1 | { |
394 | 4e14008f | blueswir1 | QT0 = float128_chs(QT1); |
395 | 4e14008f | blueswir1 | } |
396 | 4e14008f | blueswir1 | #endif
|
397 | 44e7757c | blueswir1 | |
398 | 44e7757c | blueswir1 | /* Integer to float conversion. */
|
399 | 714547bb | blueswir1 | float32 helper_fitos(int32_t src) |
400 | a0c4cb4a | bellard | { |
401 | 714547bb | blueswir1 | return int32_to_float32(src, &env->fp_status);
|
402 | a0c4cb4a | bellard | } |
403 | a0c4cb4a | bellard | |
404 | d84763bc | blueswir1 | void helper_fitod(int32_t src)
|
405 | a0c4cb4a | bellard | { |
406 | d84763bc | blueswir1 | DT0 = int32_to_float64(src, &env->fp_status); |
407 | a0c4cb4a | bellard | } |
408 | 9c2b428e | blueswir1 | |
409 | c5d04e99 | blueswir1 | void helper_fitoq(int32_t src)
|
410 | 4e14008f | blueswir1 | { |
411 | c5d04e99 | blueswir1 | QT0 = int32_to_float128(src, &env->fp_status); |
412 | 4e14008f | blueswir1 | } |
413 | 4e14008f | blueswir1 | |
414 | 1e64e78d | blueswir1 | #ifdef TARGET_SPARC64
|
415 | d84763bc | blueswir1 | float32 helper_fxtos(void)
|
416 | 1e64e78d | blueswir1 | { |
417 | d84763bc | blueswir1 | return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
|
418 | 1e64e78d | blueswir1 | } |
419 | 1e64e78d | blueswir1 | |
420 | 44e7757c | blueswir1 | F_HELPER(xto, d) |
421 | 1e64e78d | blueswir1 | { |
422 | 1e64e78d | blueswir1 | DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
423 | 1e64e78d | blueswir1 | } |
424 | 64a88d5d | blueswir1 | |
425 | 4e14008f | blueswir1 | F_HELPER(xto, q) |
426 | 4e14008f | blueswir1 | { |
427 | 4e14008f | blueswir1 | QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status); |
428 | 4e14008f | blueswir1 | } |
429 | 4e14008f | blueswir1 | #endif
|
430 | 44e7757c | blueswir1 | #undef F_HELPER
|
431 | 44e7757c | blueswir1 | |
432 | 44e7757c | blueswir1 | /* floating point conversion */
|
433 | d84763bc | blueswir1 | float32 helper_fdtos(void)
|
434 | 44e7757c | blueswir1 | { |
435 | d84763bc | blueswir1 | return float64_to_float32(DT1, &env->fp_status);
|
436 | 44e7757c | blueswir1 | } |
437 | 44e7757c | blueswir1 | |
438 | d84763bc | blueswir1 | void helper_fstod(float32 src)
|
439 | 44e7757c | blueswir1 | { |
440 | d84763bc | blueswir1 | DT0 = float32_to_float64(src, &env->fp_status); |
441 | 44e7757c | blueswir1 | } |
442 | 9c2b428e | blueswir1 | |
443 | c5d04e99 | blueswir1 | float32 helper_fqtos(void)
|
444 | 4e14008f | blueswir1 | { |
445 | c5d04e99 | blueswir1 | return float128_to_float32(QT1, &env->fp_status);
|
446 | 4e14008f | blueswir1 | } |
447 | 4e14008f | blueswir1 | |
448 | c5d04e99 | blueswir1 | void helper_fstoq(float32 src)
|
449 | 4e14008f | blueswir1 | { |
450 | c5d04e99 | blueswir1 | QT0 = float32_to_float128(src, &env->fp_status); |
451 | 4e14008f | blueswir1 | } |
452 | 4e14008f | blueswir1 | |
453 | 4e14008f | blueswir1 | void helper_fqtod(void) |
454 | 4e14008f | blueswir1 | { |
455 | 4e14008f | blueswir1 | DT0 = float128_to_float64(QT1, &env->fp_status); |
456 | 4e14008f | blueswir1 | } |
457 | 4e14008f | blueswir1 | |
458 | 4e14008f | blueswir1 | void helper_fdtoq(void) |
459 | 4e14008f | blueswir1 | { |
460 | 4e14008f | blueswir1 | QT0 = float64_to_float128(DT1, &env->fp_status); |
461 | 4e14008f | blueswir1 | } |
462 | 4e14008f | blueswir1 | |
463 | 44e7757c | blueswir1 | /* Float to integer conversion. */
|
464 | 714547bb | blueswir1 | int32_t helper_fstoi(float32 src) |
465 | 44e7757c | blueswir1 | { |
466 | 714547bb | blueswir1 | return float32_to_int32_round_to_zero(src, &env->fp_status);
|
467 | 44e7757c | blueswir1 | } |
468 | 44e7757c | blueswir1 | |
469 | d84763bc | blueswir1 | int32_t helper_fdtoi(void)
|
470 | 44e7757c | blueswir1 | { |
471 | d84763bc | blueswir1 | return float64_to_int32_round_to_zero(DT1, &env->fp_status);
|
472 | 44e7757c | blueswir1 | } |
473 | 44e7757c | blueswir1 | |
474 | c5d04e99 | blueswir1 | int32_t helper_fqtoi(void)
|
475 | 4e14008f | blueswir1 | { |
476 | c5d04e99 | blueswir1 | return float128_to_int32_round_to_zero(QT1, &env->fp_status);
|
477 | 4e14008f | blueswir1 | } |
478 | 4e14008f | blueswir1 | |
479 | 44e7757c | blueswir1 | #ifdef TARGET_SPARC64
|
480 | d84763bc | blueswir1 | void helper_fstox(float32 src)
|
481 | 44e7757c | blueswir1 | { |
482 | d84763bc | blueswir1 | *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status); |
483 | 44e7757c | blueswir1 | } |
484 | 44e7757c | blueswir1 | |
485 | 44e7757c | blueswir1 | void helper_fdtox(void) |
486 | 44e7757c | blueswir1 | { |
487 | 44e7757c | blueswir1 | *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status); |
488 | 44e7757c | blueswir1 | } |
489 | 44e7757c | blueswir1 | |
490 | 4e14008f | blueswir1 | void helper_fqtox(void) |
491 | 4e14008f | blueswir1 | { |
492 | 4e14008f | blueswir1 | *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status); |
493 | 4e14008f | blueswir1 | } |
494 | 4e14008f | blueswir1 | |
495 | 44e7757c | blueswir1 | void helper_faligndata(void) |
496 | 44e7757c | blueswir1 | { |
497 | 44e7757c | blueswir1 | uint64_t tmp; |
498 | 44e7757c | blueswir1 | |
499 | 44e7757c | blueswir1 | tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8); |
500 | 06057e6f | blueswir1 | /* on many architectures a shift of 64 does nothing */
|
501 | 06057e6f | blueswir1 | if ((env->gsr & 7) != 0) { |
502 | 06057e6f | blueswir1 | tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8); |
503 | 06057e6f | blueswir1 | } |
504 | 44e7757c | blueswir1 | *((uint64_t *)&DT0) = tmp; |
505 | 44e7757c | blueswir1 | } |
506 | 44e7757c | blueswir1 | |
507 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
|
508 | 44e7757c | blueswir1 | #define VIS_B64(n) b[7 - (n)] |
509 | 44e7757c | blueswir1 | #define VIS_W64(n) w[3 - (n)] |
510 | 44e7757c | blueswir1 | #define VIS_SW64(n) sw[3 - (n)] |
511 | 44e7757c | blueswir1 | #define VIS_L64(n) l[1 - (n)] |
512 | 44e7757c | blueswir1 | #define VIS_B32(n) b[3 - (n)] |
513 | 44e7757c | blueswir1 | #define VIS_W32(n) w[1 - (n)] |
514 | 44e7757c | blueswir1 | #else
|
515 | 44e7757c | blueswir1 | #define VIS_B64(n) b[n]
|
516 | 44e7757c | blueswir1 | #define VIS_W64(n) w[n]
|
517 | 44e7757c | blueswir1 | #define VIS_SW64(n) sw[n]
|
518 | 44e7757c | blueswir1 | #define VIS_L64(n) l[n]
|
519 | 44e7757c | blueswir1 | #define VIS_B32(n) b[n]
|
520 | 44e7757c | blueswir1 | #define VIS_W32(n) w[n]
|
521 | 44e7757c | blueswir1 | #endif
|
522 | 44e7757c | blueswir1 | |
523 | 44e7757c | blueswir1 | typedef union { |
524 | 44e7757c | blueswir1 | uint8_t b[8];
|
525 | 44e7757c | blueswir1 | uint16_t w[4];
|
526 | 44e7757c | blueswir1 | int16_t sw[4];
|
527 | 44e7757c | blueswir1 | uint32_t l[2];
|
528 | 44e7757c | blueswir1 | float64 d; |
529 | 44e7757c | blueswir1 | } vis64; |
530 | 44e7757c | blueswir1 | |
531 | 44e7757c | blueswir1 | typedef union { |
532 | 44e7757c | blueswir1 | uint8_t b[4];
|
533 | 44e7757c | blueswir1 | uint16_t w[2];
|
534 | 44e7757c | blueswir1 | uint32_t l; |
535 | 44e7757c | blueswir1 | float32 f; |
536 | 44e7757c | blueswir1 | } vis32; |
537 | 44e7757c | blueswir1 | |
538 | 44e7757c | blueswir1 | void helper_fpmerge(void) |
539 | 44e7757c | blueswir1 | { |
540 | 44e7757c | blueswir1 | vis64 s, d; |
541 | 44e7757c | blueswir1 | |
542 | 44e7757c | blueswir1 | s.d = DT0; |
543 | 44e7757c | blueswir1 | d.d = DT1; |
544 | 44e7757c | blueswir1 | |
545 | 44e7757c | blueswir1 | // Reverse calculation order to handle overlap
|
546 | 44e7757c | blueswir1 | d.VIS_B64(7) = s.VIS_B64(3); |
547 | 44e7757c | blueswir1 | d.VIS_B64(6) = d.VIS_B64(3); |
548 | 44e7757c | blueswir1 | d.VIS_B64(5) = s.VIS_B64(2); |
549 | 44e7757c | blueswir1 | d.VIS_B64(4) = d.VIS_B64(2); |
550 | 44e7757c | blueswir1 | d.VIS_B64(3) = s.VIS_B64(1); |
551 | 44e7757c | blueswir1 | d.VIS_B64(2) = d.VIS_B64(1); |
552 | 44e7757c | blueswir1 | d.VIS_B64(1) = s.VIS_B64(0); |
553 | 44e7757c | blueswir1 | //d.VIS_B64(0) = d.VIS_B64(0);
|
554 | 44e7757c | blueswir1 | |
555 | 44e7757c | blueswir1 | DT0 = d.d; |
556 | 44e7757c | blueswir1 | } |
557 | 44e7757c | blueswir1 | |
558 | 44e7757c | blueswir1 | void helper_fmul8x16(void) |
559 | 44e7757c | blueswir1 | { |
560 | 44e7757c | blueswir1 | vis64 s, d; |
561 | 44e7757c | blueswir1 | uint32_t tmp; |
562 | 44e7757c | blueswir1 | |
563 | 44e7757c | blueswir1 | s.d = DT0; |
564 | 44e7757c | blueswir1 | d.d = DT1; |
565 | 44e7757c | blueswir1 | |
566 | 44e7757c | blueswir1 | #define PMUL(r) \
|
567 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ |
568 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
569 | 44e7757c | blueswir1 | tmp += 0x100; \
|
570 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
571 | 44e7757c | blueswir1 | |
572 | 44e7757c | blueswir1 | PMUL(0);
|
573 | 44e7757c | blueswir1 | PMUL(1);
|
574 | 44e7757c | blueswir1 | PMUL(2);
|
575 | 44e7757c | blueswir1 | PMUL(3);
|
576 | 44e7757c | blueswir1 | #undef PMUL
|
577 | 44e7757c | blueswir1 | |
578 | 44e7757c | blueswir1 | DT0 = d.d; |
579 | 44e7757c | blueswir1 | } |
580 | 44e7757c | blueswir1 | |
581 | 44e7757c | blueswir1 | void helper_fmul8x16al(void) |
582 | 44e7757c | blueswir1 | { |
583 | 44e7757c | blueswir1 | vis64 s, d; |
584 | 44e7757c | blueswir1 | uint32_t tmp; |
585 | 44e7757c | blueswir1 | |
586 | 44e7757c | blueswir1 | s.d = DT0; |
587 | 44e7757c | blueswir1 | d.d = DT1; |
588 | 44e7757c | blueswir1 | |
589 | 44e7757c | blueswir1 | #define PMUL(r) \
|
590 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
|
591 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
592 | 44e7757c | blueswir1 | tmp += 0x100; \
|
593 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
594 | 44e7757c | blueswir1 | |
595 | 44e7757c | blueswir1 | PMUL(0);
|
596 | 44e7757c | blueswir1 | PMUL(1);
|
597 | 44e7757c | blueswir1 | PMUL(2);
|
598 | 44e7757c | blueswir1 | PMUL(3);
|
599 | 44e7757c | blueswir1 | #undef PMUL
|
600 | 44e7757c | blueswir1 | |
601 | 44e7757c | blueswir1 | DT0 = d.d; |
602 | 44e7757c | blueswir1 | } |
603 | 44e7757c | blueswir1 | |
604 | 44e7757c | blueswir1 | void helper_fmul8x16au(void) |
605 | 44e7757c | blueswir1 | { |
606 | 44e7757c | blueswir1 | vis64 s, d; |
607 | 44e7757c | blueswir1 | uint32_t tmp; |
608 | 44e7757c | blueswir1 | |
609 | 44e7757c | blueswir1 | s.d = DT0; |
610 | 44e7757c | blueswir1 | d.d = DT1; |
611 | 44e7757c | blueswir1 | |
612 | 44e7757c | blueswir1 | #define PMUL(r) \
|
613 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
|
614 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
615 | 44e7757c | blueswir1 | tmp += 0x100; \
|
616 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
617 | 44e7757c | blueswir1 | |
618 | 44e7757c | blueswir1 | PMUL(0);
|
619 | 44e7757c | blueswir1 | PMUL(1);
|
620 | 44e7757c | blueswir1 | PMUL(2);
|
621 | 44e7757c | blueswir1 | PMUL(3);
|
622 | 44e7757c | blueswir1 | #undef PMUL
|
623 | 44e7757c | blueswir1 | |
624 | 44e7757c | blueswir1 | DT0 = d.d; |
625 | 44e7757c | blueswir1 | } |
626 | 44e7757c | blueswir1 | |
627 | 44e7757c | blueswir1 | void helper_fmul8sux16(void) |
628 | 44e7757c | blueswir1 | { |
629 | 44e7757c | blueswir1 | vis64 s, d; |
630 | 44e7757c | blueswir1 | uint32_t tmp; |
631 | 44e7757c | blueswir1 | |
632 | 44e7757c | blueswir1 | s.d = DT0; |
633 | 44e7757c | blueswir1 | d.d = DT1; |
634 | 44e7757c | blueswir1 | |
635 | 44e7757c | blueswir1 | #define PMUL(r) \
|
636 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
637 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
638 | 44e7757c | blueswir1 | tmp += 0x100; \
|
639 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
640 | 44e7757c | blueswir1 | |
641 | 44e7757c | blueswir1 | PMUL(0);
|
642 | 44e7757c | blueswir1 | PMUL(1);
|
643 | 44e7757c | blueswir1 | PMUL(2);
|
644 | 44e7757c | blueswir1 | PMUL(3);
|
645 | 44e7757c | blueswir1 | #undef PMUL
|
646 | 44e7757c | blueswir1 | |
647 | 44e7757c | blueswir1 | DT0 = d.d; |
648 | 44e7757c | blueswir1 | } |
649 | 44e7757c | blueswir1 | |
650 | 44e7757c | blueswir1 | void helper_fmul8ulx16(void) |
651 | 44e7757c | blueswir1 | { |
652 | 44e7757c | blueswir1 | vis64 s, d; |
653 | 44e7757c | blueswir1 | uint32_t tmp; |
654 | 44e7757c | blueswir1 | |
655 | 44e7757c | blueswir1 | s.d = DT0; |
656 | 44e7757c | blueswir1 | d.d = DT1; |
657 | 44e7757c | blueswir1 | |
658 | 44e7757c | blueswir1 | #define PMUL(r) \
|
659 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
660 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
661 | 44e7757c | blueswir1 | tmp += 0x100; \
|
662 | 44e7757c | blueswir1 | d.VIS_W64(r) = tmp >> 8;
|
663 | 44e7757c | blueswir1 | |
664 | 44e7757c | blueswir1 | PMUL(0);
|
665 | 44e7757c | blueswir1 | PMUL(1);
|
666 | 44e7757c | blueswir1 | PMUL(2);
|
667 | 44e7757c | blueswir1 | PMUL(3);
|
668 | 44e7757c | blueswir1 | #undef PMUL
|
669 | 44e7757c | blueswir1 | |
670 | 44e7757c | blueswir1 | DT0 = d.d; |
671 | 44e7757c | blueswir1 | } |
672 | 44e7757c | blueswir1 | |
673 | 44e7757c | blueswir1 | void helper_fmuld8sux16(void) |
674 | 44e7757c | blueswir1 | { |
675 | 44e7757c | blueswir1 | vis64 s, d; |
676 | 44e7757c | blueswir1 | uint32_t tmp; |
677 | 44e7757c | blueswir1 | |
678 | 44e7757c | blueswir1 | s.d = DT0; |
679 | 44e7757c | blueswir1 | d.d = DT1; |
680 | 44e7757c | blueswir1 | |
681 | 44e7757c | blueswir1 | #define PMUL(r) \
|
682 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
|
683 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
684 | 44e7757c | blueswir1 | tmp += 0x100; \
|
685 | 44e7757c | blueswir1 | d.VIS_L64(r) = tmp; |
686 | 44e7757c | blueswir1 | |
687 | 44e7757c | blueswir1 | // Reverse calculation order to handle overlap
|
688 | 44e7757c | blueswir1 | PMUL(1);
|
689 | 44e7757c | blueswir1 | PMUL(0);
|
690 | 44e7757c | blueswir1 | #undef PMUL
|
691 | 44e7757c | blueswir1 | |
692 | 44e7757c | blueswir1 | DT0 = d.d; |
693 | 44e7757c | blueswir1 | } |
694 | 44e7757c | blueswir1 | |
695 | 44e7757c | blueswir1 | void helper_fmuld8ulx16(void) |
696 | 44e7757c | blueswir1 | { |
697 | 44e7757c | blueswir1 | vis64 s, d; |
698 | 44e7757c | blueswir1 | uint32_t tmp; |
699 | 44e7757c | blueswir1 | |
700 | 44e7757c | blueswir1 | s.d = DT0; |
701 | 44e7757c | blueswir1 | d.d = DT1; |
702 | 44e7757c | blueswir1 | |
703 | 44e7757c | blueswir1 | #define PMUL(r) \
|
704 | 44e7757c | blueswir1 | tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
|
705 | 44e7757c | blueswir1 | if ((tmp & 0xff) > 0x7f) \ |
706 | 44e7757c | blueswir1 | tmp += 0x100; \
|
707 | 44e7757c | blueswir1 | d.VIS_L64(r) = tmp; |
708 | 44e7757c | blueswir1 | |
709 | 44e7757c | blueswir1 | // Reverse calculation order to handle overlap
|
710 | 44e7757c | blueswir1 | PMUL(1);
|
711 | 44e7757c | blueswir1 | PMUL(0);
|
712 | 44e7757c | blueswir1 | #undef PMUL
|
713 | 44e7757c | blueswir1 | |
714 | 44e7757c | blueswir1 | DT0 = d.d; |
715 | 44e7757c | blueswir1 | } |
716 | 44e7757c | blueswir1 | |
717 | 44e7757c | blueswir1 | void helper_fexpand(void) |
718 | 44e7757c | blueswir1 | { |
719 | 44e7757c | blueswir1 | vis32 s; |
720 | 44e7757c | blueswir1 | vis64 d; |
721 | 44e7757c | blueswir1 | |
722 | 44e7757c | blueswir1 | s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
|
723 | 44e7757c | blueswir1 | d.d = DT1; |
724 | c55bda30 | blueswir1 | d.VIS_W64(0) = s.VIS_B32(0) << 4; |
725 | c55bda30 | blueswir1 | d.VIS_W64(1) = s.VIS_B32(1) << 4; |
726 | c55bda30 | blueswir1 | d.VIS_W64(2) = s.VIS_B32(2) << 4; |
727 | c55bda30 | blueswir1 | d.VIS_W64(3) = s.VIS_B32(3) << 4; |
728 | 44e7757c | blueswir1 | |
729 | 44e7757c | blueswir1 | DT0 = d.d; |
730 | 44e7757c | blueswir1 | } |
731 | 44e7757c | blueswir1 | |
732 | 44e7757c | blueswir1 | #define VIS_HELPER(name, F) \
|
733 | 44e7757c | blueswir1 | void name##16(void) \ |
734 | 44e7757c | blueswir1 | { \ |
735 | 44e7757c | blueswir1 | vis64 s, d; \ |
736 | 44e7757c | blueswir1 | \ |
737 | 44e7757c | blueswir1 | s.d = DT0; \ |
738 | 44e7757c | blueswir1 | d.d = DT1; \ |
739 | 44e7757c | blueswir1 | \ |
740 | 44e7757c | blueswir1 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ |
741 | 44e7757c | blueswir1 | d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ |
742 | 44e7757c | blueswir1 | d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ |
743 | 44e7757c | blueswir1 | d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ |
744 | 44e7757c | blueswir1 | \ |
745 | 44e7757c | blueswir1 | DT0 = d.d; \ |
746 | 44e7757c | blueswir1 | } \ |
747 | 44e7757c | blueswir1 | \ |
748 | 1d01299d | blueswir1 | uint32_t name##16s(uint32_t src1, uint32_t src2) \ |
749 | 44e7757c | blueswir1 | { \ |
750 | 44e7757c | blueswir1 | vis32 s, d; \ |
751 | 44e7757c | blueswir1 | \ |
752 | 1d01299d | blueswir1 | s.l = src1; \ |
753 | 1d01299d | blueswir1 | d.l = src2; \ |
754 | 44e7757c | blueswir1 | \ |
755 | 44e7757c | blueswir1 | d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ |
756 | 44e7757c | blueswir1 | d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ |
757 | 44e7757c | blueswir1 | \ |
758 | 1d01299d | blueswir1 | return d.l; \
|
759 | 44e7757c | blueswir1 | } \ |
760 | 44e7757c | blueswir1 | \ |
761 | 44e7757c | blueswir1 | void name##32(void) \ |
762 | 44e7757c | blueswir1 | { \ |
763 | 44e7757c | blueswir1 | vis64 s, d; \ |
764 | 44e7757c | blueswir1 | \ |
765 | 44e7757c | blueswir1 | s.d = DT0; \ |
766 | 44e7757c | blueswir1 | d.d = DT1; \ |
767 | 44e7757c | blueswir1 | \ |
768 | 44e7757c | blueswir1 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ |
769 | 44e7757c | blueswir1 | d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ |
770 | 44e7757c | blueswir1 | \ |
771 | 44e7757c | blueswir1 | DT0 = d.d; \ |
772 | 44e7757c | blueswir1 | } \ |
773 | 44e7757c | blueswir1 | \ |
774 | 1d01299d | blueswir1 | uint32_t name##32s(uint32_t src1, uint32_t src2) \ |
775 | 44e7757c | blueswir1 | { \ |
776 | 44e7757c | blueswir1 | vis32 s, d; \ |
777 | 44e7757c | blueswir1 | \ |
778 | 1d01299d | blueswir1 | s.l = src1; \ |
779 | 1d01299d | blueswir1 | d.l = src2; \ |
780 | 44e7757c | blueswir1 | \ |
781 | 44e7757c | blueswir1 | d.l = F(d.l, s.l); \ |
782 | 44e7757c | blueswir1 | \ |
783 | 1d01299d | blueswir1 | return d.l; \
|
784 | 44e7757c | blueswir1 | } |
785 | 44e7757c | blueswir1 | |
786 | 44e7757c | blueswir1 | #define FADD(a, b) ((a) + (b))
|
787 | 44e7757c | blueswir1 | #define FSUB(a, b) ((a) - (b))
|
788 | 44e7757c | blueswir1 | VIS_HELPER(helper_fpadd, FADD) |
789 | 44e7757c | blueswir1 | VIS_HELPER(helper_fpsub, FSUB) |
790 | 44e7757c | blueswir1 | |
791 | 44e7757c | blueswir1 | #define VIS_CMPHELPER(name, F) \
|
792 | 44e7757c | blueswir1 | void name##16(void) \ |
793 | 44e7757c | blueswir1 | { \ |
794 | 44e7757c | blueswir1 | vis64 s, d; \ |
795 | 44e7757c | blueswir1 | \ |
796 | 44e7757c | blueswir1 | s.d = DT0; \ |
797 | 44e7757c | blueswir1 | d.d = DT1; \ |
798 | 44e7757c | blueswir1 | \ |
799 | 44e7757c | blueswir1 | d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \ |
800 | 44e7757c | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \ |
801 | 44e7757c | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \ |
802 | 44e7757c | blueswir1 | d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \ |
803 | 44e7757c | blueswir1 | \ |
804 | 44e7757c | blueswir1 | DT0 = d.d; \ |
805 | 44e7757c | blueswir1 | } \ |
806 | 44e7757c | blueswir1 | \ |
807 | 44e7757c | blueswir1 | void name##32(void) \ |
808 | 44e7757c | blueswir1 | { \ |
809 | 44e7757c | blueswir1 | vis64 s, d; \ |
810 | 44e7757c | blueswir1 | \ |
811 | 44e7757c | blueswir1 | s.d = DT0; \ |
812 | 44e7757c | blueswir1 | d.d = DT1; \ |
813 | 44e7757c | blueswir1 | \ |
814 | 44e7757c | blueswir1 | d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \ |
815 | 44e7757c | blueswir1 | d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \ |
816 | 44e7757c | blueswir1 | \ |
817 | 44e7757c | blueswir1 | DT0 = d.d; \ |
818 | 44e7757c | blueswir1 | } |
819 | 44e7757c | blueswir1 | |
820 | 44e7757c | blueswir1 | #define FCMPGT(a, b) ((a) > (b))
|
821 | 44e7757c | blueswir1 | #define FCMPEQ(a, b) ((a) == (b))
|
822 | 44e7757c | blueswir1 | #define FCMPLE(a, b) ((a) <= (b))
|
823 | 44e7757c | blueswir1 | #define FCMPNE(a, b) ((a) != (b))
|
824 | 44e7757c | blueswir1 | |
825 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmpgt, FCMPGT) |
826 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmpeq, FCMPEQ) |
827 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmple, FCMPLE) |
828 | 44e7757c | blueswir1 | VIS_CMPHELPER(helper_fcmpne, FCMPNE) |
829 | 44e7757c | blueswir1 | #endif
|
830 | 44e7757c | blueswir1 | |
831 | 44e7757c | blueswir1 | void helper_check_ieee_exceptions(void) |
832 | 44e7757c | blueswir1 | { |
833 | 44e7757c | blueswir1 | target_ulong status; |
834 | 44e7757c | blueswir1 | |
835 | 44e7757c | blueswir1 | status = get_float_exception_flags(&env->fp_status); |
836 | 44e7757c | blueswir1 | if (status) {
|
837 | 44e7757c | blueswir1 | /* Copy IEEE 754 flags into FSR */
|
838 | 44e7757c | blueswir1 | if (status & float_flag_invalid)
|
839 | 44e7757c | blueswir1 | env->fsr |= FSR_NVC; |
840 | 44e7757c | blueswir1 | if (status & float_flag_overflow)
|
841 | 44e7757c | blueswir1 | env->fsr |= FSR_OFC; |
842 | 44e7757c | blueswir1 | if (status & float_flag_underflow)
|
843 | 44e7757c | blueswir1 | env->fsr |= FSR_UFC; |
844 | 44e7757c | blueswir1 | if (status & float_flag_divbyzero)
|
845 | 44e7757c | blueswir1 | env->fsr |= FSR_DZC; |
846 | 44e7757c | blueswir1 | if (status & float_flag_inexact)
|
847 | 44e7757c | blueswir1 | env->fsr |= FSR_NXC; |
848 | 44e7757c | blueswir1 | |
849 | 44e7757c | blueswir1 | if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { |
850 | 44e7757c | blueswir1 | /* Unmasked exception, generate a trap */
|
851 | 44e7757c | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; |
852 | 44e7757c | blueswir1 | raise_exception(TT_FP_EXCP); |
853 | 44e7757c | blueswir1 | } else {
|
854 | 44e7757c | blueswir1 | /* Accumulate exceptions */
|
855 | 44e7757c | blueswir1 | env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
|
856 | 44e7757c | blueswir1 | } |
857 | 44e7757c | blueswir1 | } |
858 | 44e7757c | blueswir1 | } |
859 | 44e7757c | blueswir1 | |
860 | 44e7757c | blueswir1 | void helper_clear_float_exceptions(void) |
861 | 44e7757c | blueswir1 | { |
862 | 44e7757c | blueswir1 | set_float_exception_flags(0, &env->fp_status);
|
863 | 44e7757c | blueswir1 | } |
864 | 44e7757c | blueswir1 | |
865 | 714547bb | blueswir1 | float32 helper_fabss(float32 src) |
866 | e8af50a3 | bellard | { |
867 | 714547bb | blueswir1 | return float32_abs(src);
|
868 | e8af50a3 | bellard | } |
869 | e8af50a3 | bellard | |
870 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
871 | 7e8c2b6c | blueswir1 | void helper_fabsd(void) |
872 | 3475187d | bellard | { |
873 | 3475187d | bellard | DT0 = float64_abs(DT1); |
874 | 3475187d | bellard | } |
875 | 4e14008f | blueswir1 | |
876 | 4e14008f | blueswir1 | void helper_fabsq(void) |
877 | 4e14008f | blueswir1 | { |
878 | 4e14008f | blueswir1 | QT0 = float128_abs(QT1); |
879 | 4e14008f | blueswir1 | } |
880 | 4e14008f | blueswir1 | #endif
|
881 | 3475187d | bellard | |
882 | 714547bb | blueswir1 | float32 helper_fsqrts(float32 src) |
883 | e8af50a3 | bellard | { |
884 | 714547bb | blueswir1 | return float32_sqrt(src, &env->fp_status);
|
885 | e8af50a3 | bellard | } |
886 | e8af50a3 | bellard | |
887 | 7e8c2b6c | blueswir1 | void helper_fsqrtd(void) |
888 | e8af50a3 | bellard | { |
889 | 7a0e1f41 | bellard | DT0 = float64_sqrt(DT1, &env->fp_status); |
890 | e8af50a3 | bellard | } |
891 | e8af50a3 | bellard | |
892 | 4e14008f | blueswir1 | void helper_fsqrtq(void) |
893 | 4e14008f | blueswir1 | { |
894 | 4e14008f | blueswir1 | QT0 = float128_sqrt(QT1, &env->fp_status); |
895 | 4e14008f | blueswir1 | } |
896 | 4e14008f | blueswir1 | |
897 | 1b5f56b1 | Blue Swirl | #define GEN_FCMP(name, size, reg1, reg2, FS, E) \
|
898 | 7e8c2b6c | blueswir1 | void glue(helper_, name) (void) \ |
899 | 65ce8c2f | bellard | { \ |
900 | 1b5f56b1 | Blue Swirl | env->fsr &= FSR_FTT_NMASK; \ |
901 | 1b5f56b1 | Blue Swirl | if (E && (glue(size, _is_any_nan)(reg1) || \
|
902 | 1b5f56b1 | Blue Swirl | glue(size, _is_any_nan)(reg2)) && \ |
903 | 1b5f56b1 | Blue Swirl | (env->fsr & FSR_NVM)) { \ |
904 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_NVC; \ |
905 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
906 | 1b5f56b1 | Blue Swirl | raise_exception(TT_FP_EXCP); \ |
907 | 1b5f56b1 | Blue Swirl | } \ |
908 | 65ce8c2f | bellard | switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
|
909 | 65ce8c2f | bellard | case float_relation_unordered: \
|
910 | 1b5f56b1 | Blue Swirl | if ((env->fsr & FSR_NVM)) { \
|
911 | 417454b0 | blueswir1 | env->fsr |= FSR_NVC; \ |
912 | 417454b0 | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
913 | 65ce8c2f | bellard | raise_exception(TT_FP_EXCP); \ |
914 | 65ce8c2f | bellard | } else { \
|
915 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
916 | 1b5f56b1 | Blue Swirl | env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ |
917 | 65ce8c2f | bellard | env->fsr |= FSR_NVA; \ |
918 | 65ce8c2f | bellard | } \ |
919 | 65ce8c2f | bellard | break; \
|
920 | 65ce8c2f | bellard | case float_relation_less: \
|
921 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
922 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_FCC0 << FS; \ |
923 | 65ce8c2f | bellard | break; \
|
924 | 65ce8c2f | bellard | case float_relation_greater: \
|
925 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
926 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_FCC1 << FS; \ |
927 | 65ce8c2f | bellard | break; \
|
928 | 65ce8c2f | bellard | default: \
|
929 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
930 | 65ce8c2f | bellard | break; \
|
931 | 65ce8c2f | bellard | } \ |
932 | e8af50a3 | bellard | } |
933 | 1b5f56b1 | Blue Swirl | #define GEN_FCMPS(name, size, FS, E) \
|
934 | 714547bb | blueswir1 | void glue(helper_, name)(float32 src1, float32 src2) \
|
935 | 714547bb | blueswir1 | { \ |
936 | 1b5f56b1 | Blue Swirl | env->fsr &= FSR_FTT_NMASK; \ |
937 | 1b5f56b1 | Blue Swirl | if (E && (glue(size, _is_any_nan)(src1) || \
|
938 | 1b5f56b1 | Blue Swirl | glue(size, _is_any_nan)(src2)) && \ |
939 | 1b5f56b1 | Blue Swirl | (env->fsr & FSR_NVM)) { \ |
940 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_NVC; \ |
941 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
942 | 1b5f56b1 | Blue Swirl | raise_exception(TT_FP_EXCP); \ |
943 | 1b5f56b1 | Blue Swirl | } \ |
944 | 714547bb | blueswir1 | switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
|
945 | 714547bb | blueswir1 | case float_relation_unordered: \
|
946 | 1b5f56b1 | Blue Swirl | if ((env->fsr & FSR_NVM)) { \
|
947 | 714547bb | blueswir1 | env->fsr |= FSR_NVC; \ |
948 | 714547bb | blueswir1 | env->fsr |= FSR_FTT_IEEE_EXCP; \ |
949 | 714547bb | blueswir1 | raise_exception(TT_FP_EXCP); \ |
950 | 714547bb | blueswir1 | } else { \
|
951 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
952 | 1b5f56b1 | Blue Swirl | env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \ |
953 | 714547bb | blueswir1 | env->fsr |= FSR_NVA; \ |
954 | 714547bb | blueswir1 | } \ |
955 | 714547bb | blueswir1 | break; \
|
956 | 714547bb | blueswir1 | case float_relation_less: \
|
957 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
958 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_FCC0 << FS; \ |
959 | 714547bb | blueswir1 | break; \
|
960 | 714547bb | blueswir1 | case float_relation_greater: \
|
961 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
962 | 1b5f56b1 | Blue Swirl | env->fsr |= FSR_FCC1 << FS; \ |
963 | 714547bb | blueswir1 | break; \
|
964 | 714547bb | blueswir1 | default: \
|
965 | 1b5f56b1 | Blue Swirl | env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
966 | 714547bb | blueswir1 | break; \
|
967 | 714547bb | blueswir1 | } \ |
968 | 714547bb | blueswir1 | } |
969 | e8af50a3 | bellard | |
970 | 714547bb | blueswir1 | GEN_FCMPS(fcmps, float32, 0, 0); |
971 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
972 | 417454b0 | blueswir1 | |
973 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes, float32, 0, 1); |
974 | 417454b0 | blueswir1 | GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
975 | 3475187d | bellard | |
976 | 4e14008f | blueswir1 | GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); |
977 | 4e14008f | blueswir1 | GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); |
978 | 4e14008f | blueswir1 | |
979 | 8393617c | Blue Swirl | static uint32_t compute_all_flags(void) |
980 | 8393617c | Blue Swirl | { |
981 | 8393617c | Blue Swirl | return env->psr & PSR_ICC;
|
982 | 8393617c | Blue Swirl | } |
983 | 8393617c | Blue Swirl | |
984 | 8393617c | Blue Swirl | static uint32_t compute_C_flags(void) |
985 | 8393617c | Blue Swirl | { |
986 | 8393617c | Blue Swirl | return env->psr & PSR_CARRY;
|
987 | 8393617c | Blue Swirl | } |
988 | 8393617c | Blue Swirl | |
989 | 5a4bb580 | Richard Henderson | static inline uint32_t get_NZ_icc(int32_t dst) |
990 | bdf9f35d | Blue Swirl | { |
991 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
992 | bdf9f35d | Blue Swirl | |
993 | 5a4bb580 | Richard Henderson | if (dst == 0) { |
994 | 5a4bb580 | Richard Henderson | ret = PSR_ZERO; |
995 | 5a4bb580 | Richard Henderson | } else if (dst < 0) { |
996 | 5a4bb580 | Richard Henderson | ret = PSR_NEG; |
997 | 5a4bb580 | Richard Henderson | } |
998 | bdf9f35d | Blue Swirl | return ret;
|
999 | bdf9f35d | Blue Swirl | } |
1000 | bdf9f35d | Blue Swirl | |
1001 | 8393617c | Blue Swirl | #ifdef TARGET_SPARC64
|
1002 | 8393617c | Blue Swirl | static uint32_t compute_all_flags_xcc(void) |
1003 | 8393617c | Blue Swirl | { |
1004 | 8393617c | Blue Swirl | return env->xcc & PSR_ICC;
|
1005 | 8393617c | Blue Swirl | } |
1006 | 8393617c | Blue Swirl | |
1007 | 8393617c | Blue Swirl | static uint32_t compute_C_flags_xcc(void) |
1008 | 8393617c | Blue Swirl | { |
1009 | 8393617c | Blue Swirl | return env->xcc & PSR_CARRY;
|
1010 | 8393617c | Blue Swirl | } |
1011 | 8393617c | Blue Swirl | |
1012 | 5a4bb580 | Richard Henderson | static inline uint32_t get_NZ_xcc(target_long dst) |
1013 | bdf9f35d | Blue Swirl | { |
1014 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1015 | bdf9f35d | Blue Swirl | |
1016 | 5a4bb580 | Richard Henderson | if (!dst) {
|
1017 | 5a4bb580 | Richard Henderson | ret = PSR_ZERO; |
1018 | 5a4bb580 | Richard Henderson | } else if (dst < 0) { |
1019 | 5a4bb580 | Richard Henderson | ret = PSR_NEG; |
1020 | 5a4bb580 | Richard Henderson | } |
1021 | bdf9f35d | Blue Swirl | return ret;
|
1022 | bdf9f35d | Blue Swirl | } |
1023 | bdf9f35d | Blue Swirl | #endif
|
1024 | bdf9f35d | Blue Swirl | |
1025 | 6c78ea32 | Blue Swirl | static inline uint32_t get_V_div_icc(target_ulong src2) |
1026 | 6c78ea32 | Blue Swirl | { |
1027 | 6c78ea32 | Blue Swirl | uint32_t ret = 0;
|
1028 | 6c78ea32 | Blue Swirl | |
1029 | 5a4bb580 | Richard Henderson | if (src2 != 0) { |
1030 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1031 | 5a4bb580 | Richard Henderson | } |
1032 | 6c78ea32 | Blue Swirl | return ret;
|
1033 | 6c78ea32 | Blue Swirl | } |
1034 | 6c78ea32 | Blue Swirl | |
1035 | 6c78ea32 | Blue Swirl | static uint32_t compute_all_div(void) |
1036 | 6c78ea32 | Blue Swirl | { |
1037 | 6c78ea32 | Blue Swirl | uint32_t ret; |
1038 | 6c78ea32 | Blue Swirl | |
1039 | 6c78ea32 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1040 | 6c78ea32 | Blue Swirl | ret |= get_V_div_icc(CC_SRC2); |
1041 | 6c78ea32 | Blue Swirl | return ret;
|
1042 | 6c78ea32 | Blue Swirl | } |
1043 | 6c78ea32 | Blue Swirl | |
1044 | 6c78ea32 | Blue Swirl | static uint32_t compute_C_div(void) |
1045 | 6c78ea32 | Blue Swirl | { |
1046 | 6c78ea32 | Blue Swirl | return 0; |
1047 | 6c78ea32 | Blue Swirl | } |
1048 | 6c78ea32 | Blue Swirl | |
1049 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_add_icc(uint32_t dst, uint32_t src1) |
1050 | bdf9f35d | Blue Swirl | { |
1051 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1052 | bdf9f35d | Blue Swirl | |
1053 | 5a4bb580 | Richard Henderson | if (dst < src1) {
|
1054 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1055 | 5a4bb580 | Richard Henderson | } |
1056 | bdf9f35d | Blue Swirl | return ret;
|
1057 | bdf9f35d | Blue Swirl | } |
1058 | bdf9f35d | Blue Swirl | |
1059 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_addx_icc(uint32_t dst, uint32_t src1, |
1060 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1061 | bdf9f35d | Blue Swirl | { |
1062 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1063 | bdf9f35d | Blue Swirl | |
1064 | 5a4bb580 | Richard Henderson | if (((src1 & src2) | (~dst & (src1 | src2))) & (1U << 31)) { |
1065 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1066 | 5a4bb580 | Richard Henderson | } |
1067 | 5a4bb580 | Richard Henderson | return ret;
|
1068 | 5a4bb580 | Richard Henderson | } |
1069 | 5a4bb580 | Richard Henderson | |
1070 | 5a4bb580 | Richard Henderson | static inline uint32_t get_V_add_icc(uint32_t dst, uint32_t src1, |
1071 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1072 | 5a4bb580 | Richard Henderson | { |
1073 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1074 | 5a4bb580 | Richard Henderson | |
1075 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1U << 31)) { |
1076 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1077 | 5a4bb580 | Richard Henderson | } |
1078 | bdf9f35d | Blue Swirl | return ret;
|
1079 | bdf9f35d | Blue Swirl | } |
1080 | bdf9f35d | Blue Swirl | |
1081 | bdf9f35d | Blue Swirl | #ifdef TARGET_SPARC64
|
1082 | bdf9f35d | Blue Swirl | static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1) |
1083 | bdf9f35d | Blue Swirl | { |
1084 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1085 | bdf9f35d | Blue Swirl | |
1086 | 5a4bb580 | Richard Henderson | if (dst < src1) {
|
1087 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1088 | 5a4bb580 | Richard Henderson | } |
1089 | 5a4bb580 | Richard Henderson | return ret;
|
1090 | 5a4bb580 | Richard Henderson | } |
1091 | 5a4bb580 | Richard Henderson | |
1092 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_addx_xcc(target_ulong dst, target_ulong src1, |
1093 | 5a4bb580 | Richard Henderson | target_ulong src2) |
1094 | 5a4bb580 | Richard Henderson | { |
1095 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1096 | 5a4bb580 | Richard Henderson | |
1097 | 5a4bb580 | Richard Henderson | if (((src1 & src2) | (~dst & (src1 | src2))) & (1ULL << 63)) { |
1098 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1099 | 5a4bb580 | Richard Henderson | } |
1100 | bdf9f35d | Blue Swirl | return ret;
|
1101 | bdf9f35d | Blue Swirl | } |
1102 | bdf9f35d | Blue Swirl | |
1103 | bdf9f35d | Blue Swirl | static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1, |
1104 | bdf9f35d | Blue Swirl | target_ulong src2) |
1105 | bdf9f35d | Blue Swirl | { |
1106 | bdf9f35d | Blue Swirl | uint32_t ret = 0;
|
1107 | bdf9f35d | Blue Swirl | |
1108 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63)) { |
1109 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1110 | 5a4bb580 | Richard Henderson | } |
1111 | bdf9f35d | Blue Swirl | return ret;
|
1112 | bdf9f35d | Blue Swirl | } |
1113 | bdf9f35d | Blue Swirl | |
1114 | bdf9f35d | Blue Swirl | static uint32_t compute_all_add_xcc(void) |
1115 | bdf9f35d | Blue Swirl | { |
1116 | bdf9f35d | Blue Swirl | uint32_t ret; |
1117 | bdf9f35d | Blue Swirl | |
1118 | bdf9f35d | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1119 | bdf9f35d | Blue Swirl | ret |= get_C_add_xcc(CC_DST, CC_SRC); |
1120 | bdf9f35d | Blue Swirl | ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1121 | bdf9f35d | Blue Swirl | return ret;
|
1122 | bdf9f35d | Blue Swirl | } |
1123 | bdf9f35d | Blue Swirl | |
1124 | bdf9f35d | Blue Swirl | static uint32_t compute_C_add_xcc(void) |
1125 | bdf9f35d | Blue Swirl | { |
1126 | bdf9f35d | Blue Swirl | return get_C_add_xcc(CC_DST, CC_SRC);
|
1127 | bdf9f35d | Blue Swirl | } |
1128 | 8393617c | Blue Swirl | #endif
|
1129 | 8393617c | Blue Swirl | |
1130 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_all_add(void) |
1131 | 789c91ef | Blue Swirl | { |
1132 | 789c91ef | Blue Swirl | uint32_t ret; |
1133 | 789c91ef | Blue Swirl | |
1134 | 789c91ef | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1135 | 5a4bb580 | Richard Henderson | ret |= get_C_add_icc(CC_DST, CC_SRC); |
1136 | 789c91ef | Blue Swirl | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1137 | 789c91ef | Blue Swirl | return ret;
|
1138 | 789c91ef | Blue Swirl | } |
1139 | 789c91ef | Blue Swirl | |
1140 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_C_add(void) |
1141 | 789c91ef | Blue Swirl | { |
1142 | 5a4bb580 | Richard Henderson | return get_C_add_icc(CC_DST, CC_SRC);
|
1143 | 789c91ef | Blue Swirl | } |
1144 | 789c91ef | Blue Swirl | |
1145 | 789c91ef | Blue Swirl | #ifdef TARGET_SPARC64
|
1146 | 789c91ef | Blue Swirl | static uint32_t compute_all_addx_xcc(void) |
1147 | 789c91ef | Blue Swirl | { |
1148 | 789c91ef | Blue Swirl | uint32_t ret; |
1149 | 789c91ef | Blue Swirl | |
1150 | 789c91ef | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1151 | 5a4bb580 | Richard Henderson | ret |= get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1152 | 789c91ef | Blue Swirl | ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2); |
1153 | 789c91ef | Blue Swirl | return ret;
|
1154 | 789c91ef | Blue Swirl | } |
1155 | 789c91ef | Blue Swirl | |
1156 | 789c91ef | Blue Swirl | static uint32_t compute_C_addx_xcc(void) |
1157 | 789c91ef | Blue Swirl | { |
1158 | 789c91ef | Blue Swirl | uint32_t ret; |
1159 | 789c91ef | Blue Swirl | |
1160 | 5a4bb580 | Richard Henderson | ret = get_C_addx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1161 | 789c91ef | Blue Swirl | return ret;
|
1162 | 789c91ef | Blue Swirl | } |
1163 | 789c91ef | Blue Swirl | #endif
|
1164 | 789c91ef | Blue Swirl | |
1165 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_addx(void) |
1166 | 5a4bb580 | Richard Henderson | { |
1167 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1168 | 5a4bb580 | Richard Henderson | |
1169 | 5a4bb580 | Richard Henderson | ret = get_NZ_icc(CC_DST); |
1170 | 5a4bb580 | Richard Henderson | ret |= get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); |
1171 | 5a4bb580 | Richard Henderson | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1172 | 5a4bb580 | Richard Henderson | return ret;
|
1173 | 5a4bb580 | Richard Henderson | } |
1174 | 5a4bb580 | Richard Henderson | |
1175 | 5a4bb580 | Richard Henderson | static uint32_t compute_C_addx(void) |
1176 | 5a4bb580 | Richard Henderson | { |
1177 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1178 | 5a4bb580 | Richard Henderson | |
1179 | 5a4bb580 | Richard Henderson | ret = get_C_addx_icc(CC_DST, CC_SRC, CC_SRC2); |
1180 | 5a4bb580 | Richard Henderson | return ret;
|
1181 | 5a4bb580 | Richard Henderson | } |
1182 | 5a4bb580 | Richard Henderson | |
1183 | 3b2d1e92 | Blue Swirl | static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2) |
1184 | 3b2d1e92 | Blue Swirl | { |
1185 | 3b2d1e92 | Blue Swirl | uint32_t ret = 0;
|
1186 | 3b2d1e92 | Blue Swirl | |
1187 | 5a4bb580 | Richard Henderson | if ((src1 | src2) & 0x3) { |
1188 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1189 | 5a4bb580 | Richard Henderson | } |
1190 | 3b2d1e92 | Blue Swirl | return ret;
|
1191 | 3b2d1e92 | Blue Swirl | } |
1192 | 3b2d1e92 | Blue Swirl | |
1193 | 3b2d1e92 | Blue Swirl | static uint32_t compute_all_tadd(void) |
1194 | 3b2d1e92 | Blue Swirl | { |
1195 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1196 | 3b2d1e92 | Blue Swirl | |
1197 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1198 | 5a4bb580 | Richard Henderson | ret |= get_C_add_icc(CC_DST, CC_SRC); |
1199 | 3b2d1e92 | Blue Swirl | ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2); |
1200 | 3b2d1e92 | Blue Swirl | ret |= get_V_tag_icc(CC_SRC, CC_SRC2); |
1201 | 3b2d1e92 | Blue Swirl | return ret;
|
1202 | 3b2d1e92 | Blue Swirl | } |
1203 | 3b2d1e92 | Blue Swirl | |
1204 | 3b2d1e92 | Blue Swirl | static uint32_t compute_all_taddtv(void) |
1205 | 3b2d1e92 | Blue Swirl | { |
1206 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1207 | 3b2d1e92 | Blue Swirl | |
1208 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1209 | 5a4bb580 | Richard Henderson | ret |= get_C_add_icc(CC_DST, CC_SRC); |
1210 | 3b2d1e92 | Blue Swirl | return ret;
|
1211 | 3b2d1e92 | Blue Swirl | } |
1212 | 3b2d1e92 | Blue Swirl | |
1213 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_sub_icc(uint32_t src1, uint32_t src2) |
1214 | 3b2d1e92 | Blue Swirl | { |
1215 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1216 | 5a4bb580 | Richard Henderson | |
1217 | 5a4bb580 | Richard Henderson | if (src1 < src2) {
|
1218 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1219 | 5a4bb580 | Richard Henderson | } |
1220 | 5a4bb580 | Richard Henderson | return ret;
|
1221 | 3b2d1e92 | Blue Swirl | } |
1222 | 3b2d1e92 | Blue Swirl | |
1223 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_subx_icc(uint32_t dst, uint32_t src1, |
1224 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1225 | d4b0d468 | Blue Swirl | { |
1226 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1227 | d4b0d468 | Blue Swirl | |
1228 | 5a4bb580 | Richard Henderson | if (((~src1 & src2) | (dst & (~src1 | src2))) & (1U << 31)) { |
1229 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1230 | 5a4bb580 | Richard Henderson | } |
1231 | d4b0d468 | Blue Swirl | return ret;
|
1232 | d4b0d468 | Blue Swirl | } |
1233 | d4b0d468 | Blue Swirl | |
1234 | 5a4bb580 | Richard Henderson | static inline uint32_t get_V_sub_icc(uint32_t dst, uint32_t src1, |
1235 | 5a4bb580 | Richard Henderson | uint32_t src2) |
1236 | d4b0d468 | Blue Swirl | { |
1237 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1238 | d4b0d468 | Blue Swirl | |
1239 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2) & (src1 ^ dst)) & (1U << 31)) { |
1240 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1241 | 5a4bb580 | Richard Henderson | } |
1242 | d4b0d468 | Blue Swirl | return ret;
|
1243 | d4b0d468 | Blue Swirl | } |
1244 | d4b0d468 | Blue Swirl | |
1245 | d4b0d468 | Blue Swirl | |
1246 | d4b0d468 | Blue Swirl | #ifdef TARGET_SPARC64
|
1247 | d4b0d468 | Blue Swirl | static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2) |
1248 | d4b0d468 | Blue Swirl | { |
1249 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1250 | d4b0d468 | Blue Swirl | |
1251 | 5a4bb580 | Richard Henderson | if (src1 < src2) {
|
1252 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1253 | 5a4bb580 | Richard Henderson | } |
1254 | 5a4bb580 | Richard Henderson | return ret;
|
1255 | 5a4bb580 | Richard Henderson | } |
1256 | 5a4bb580 | Richard Henderson | |
1257 | 5a4bb580 | Richard Henderson | static inline uint32_t get_C_subx_xcc(target_ulong dst, target_ulong src1, |
1258 | 5a4bb580 | Richard Henderson | target_ulong src2) |
1259 | 5a4bb580 | Richard Henderson | { |
1260 | 5a4bb580 | Richard Henderson | uint32_t ret = 0;
|
1261 | 5a4bb580 | Richard Henderson | |
1262 | 5a4bb580 | Richard Henderson | if (((~src1 & src2) | (dst & (~src1 | src2))) & (1ULL << 63)) { |
1263 | 5a4bb580 | Richard Henderson | ret = PSR_CARRY; |
1264 | 5a4bb580 | Richard Henderson | } |
1265 | d4b0d468 | Blue Swirl | return ret;
|
1266 | d4b0d468 | Blue Swirl | } |
1267 | d4b0d468 | Blue Swirl | |
1268 | d4b0d468 | Blue Swirl | static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1, |
1269 | d4b0d468 | Blue Swirl | target_ulong src2) |
1270 | d4b0d468 | Blue Swirl | { |
1271 | d4b0d468 | Blue Swirl | uint32_t ret = 0;
|
1272 | d4b0d468 | Blue Swirl | |
1273 | 5a4bb580 | Richard Henderson | if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63)) { |
1274 | 5a4bb580 | Richard Henderson | ret = PSR_OVF; |
1275 | 5a4bb580 | Richard Henderson | } |
1276 | d4b0d468 | Blue Swirl | return ret;
|
1277 | d4b0d468 | Blue Swirl | } |
1278 | d4b0d468 | Blue Swirl | |
1279 | d4b0d468 | Blue Swirl | static uint32_t compute_all_sub_xcc(void) |
1280 | d4b0d468 | Blue Swirl | { |
1281 | d4b0d468 | Blue Swirl | uint32_t ret; |
1282 | d4b0d468 | Blue Swirl | |
1283 | d4b0d468 | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1284 | d4b0d468 | Blue Swirl | ret |= get_C_sub_xcc(CC_SRC, CC_SRC2); |
1285 | d4b0d468 | Blue Swirl | ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1286 | d4b0d468 | Blue Swirl | return ret;
|
1287 | d4b0d468 | Blue Swirl | } |
1288 | d4b0d468 | Blue Swirl | |
1289 | d4b0d468 | Blue Swirl | static uint32_t compute_C_sub_xcc(void) |
1290 | d4b0d468 | Blue Swirl | { |
1291 | d4b0d468 | Blue Swirl | return get_C_sub_xcc(CC_SRC, CC_SRC2);
|
1292 | d4b0d468 | Blue Swirl | } |
1293 | d4b0d468 | Blue Swirl | #endif
|
1294 | d4b0d468 | Blue Swirl | |
1295 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_all_sub(void) |
1296 | 2ca1d92b | Blue Swirl | { |
1297 | 2ca1d92b | Blue Swirl | uint32_t ret; |
1298 | 2ca1d92b | Blue Swirl | |
1299 | 2ca1d92b | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1300 | 5a4bb580 | Richard Henderson | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1301 | 2ca1d92b | Blue Swirl | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1302 | 2ca1d92b | Blue Swirl | return ret;
|
1303 | 2ca1d92b | Blue Swirl | } |
1304 | 2ca1d92b | Blue Swirl | |
1305 | 3e6ba503 | Artyom Tarasenko | static uint32_t compute_C_sub(void) |
1306 | 2ca1d92b | Blue Swirl | { |
1307 | 5a4bb580 | Richard Henderson | return get_C_sub_icc(CC_SRC, CC_SRC2);
|
1308 | 2ca1d92b | Blue Swirl | } |
1309 | 2ca1d92b | Blue Swirl | |
1310 | 2ca1d92b | Blue Swirl | #ifdef TARGET_SPARC64
|
1311 | 2ca1d92b | Blue Swirl | static uint32_t compute_all_subx_xcc(void) |
1312 | 2ca1d92b | Blue Swirl | { |
1313 | 2ca1d92b | Blue Swirl | uint32_t ret; |
1314 | 2ca1d92b | Blue Swirl | |
1315 | 2ca1d92b | Blue Swirl | ret = get_NZ_xcc(CC_DST); |
1316 | 5a4bb580 | Richard Henderson | ret |= get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1317 | 2ca1d92b | Blue Swirl | ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); |
1318 | 2ca1d92b | Blue Swirl | return ret;
|
1319 | 2ca1d92b | Blue Swirl | } |
1320 | 2ca1d92b | Blue Swirl | |
1321 | 2ca1d92b | Blue Swirl | static uint32_t compute_C_subx_xcc(void) |
1322 | 2ca1d92b | Blue Swirl | { |
1323 | 2ca1d92b | Blue Swirl | uint32_t ret; |
1324 | 2ca1d92b | Blue Swirl | |
1325 | 5a4bb580 | Richard Henderson | ret = get_C_subx_xcc(CC_DST, CC_SRC, CC_SRC2); |
1326 | 2ca1d92b | Blue Swirl | return ret;
|
1327 | 2ca1d92b | Blue Swirl | } |
1328 | 2ca1d92b | Blue Swirl | #endif
|
1329 | 2ca1d92b | Blue Swirl | |
1330 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_subx(void) |
1331 | 3b2d1e92 | Blue Swirl | { |
1332 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1333 | 3b2d1e92 | Blue Swirl | |
1334 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1335 | 5a4bb580 | Richard Henderson | ret |= get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
1336 | 3b2d1e92 | Blue Swirl | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1337 | 3b2d1e92 | Blue Swirl | return ret;
|
1338 | 3b2d1e92 | Blue Swirl | } |
1339 | 3b2d1e92 | Blue Swirl | |
1340 | 5a4bb580 | Richard Henderson | static uint32_t compute_C_subx(void) |
1341 | 3b2d1e92 | Blue Swirl | { |
1342 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1343 | 5a4bb580 | Richard Henderson | |
1344 | 5a4bb580 | Richard Henderson | ret = get_C_subx_icc(CC_DST, CC_SRC, CC_SRC2); |
1345 | 5a4bb580 | Richard Henderson | return ret;
|
1346 | 3b2d1e92 | Blue Swirl | } |
1347 | 3b2d1e92 | Blue Swirl | |
1348 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_tsub(void) |
1349 | 3b2d1e92 | Blue Swirl | { |
1350 | 3b2d1e92 | Blue Swirl | uint32_t ret; |
1351 | 3b2d1e92 | Blue Swirl | |
1352 | 3b2d1e92 | Blue Swirl | ret = get_NZ_icc(CC_DST); |
1353 | 5a4bb580 | Richard Henderson | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1354 | 5a4bb580 | Richard Henderson | ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); |
1355 | 5a4bb580 | Richard Henderson | ret |= get_V_tag_icc(CC_SRC, CC_SRC2); |
1356 | 3b2d1e92 | Blue Swirl | return ret;
|
1357 | 3b2d1e92 | Blue Swirl | } |
1358 | 3b2d1e92 | Blue Swirl | |
1359 | 5a4bb580 | Richard Henderson | static uint32_t compute_all_tsubtv(void) |
1360 | 3b2d1e92 | Blue Swirl | { |
1361 | 5a4bb580 | Richard Henderson | uint32_t ret; |
1362 | 5a4bb580 | Richard Henderson | |
1363 | 5a4bb580 | Richard Henderson | ret = get_NZ_icc(CC_DST); |
1364 | 5a4bb580 | Richard Henderson | ret |= get_C_sub_icc(CC_SRC, CC_SRC2); |
1365 | 5a4bb580 | Richard Henderson | return ret;
|
1366 | 3b2d1e92 | Blue Swirl | } |
1367 | 3b2d1e92 | Blue Swirl | |
1368 | 38482a77 | Blue Swirl | static uint32_t compute_all_logic(void) |
1369 | 38482a77 | Blue Swirl | { |
1370 | 38482a77 | Blue Swirl | return get_NZ_icc(CC_DST);
|
1371 | 38482a77 | Blue Swirl | } |
1372 | 38482a77 | Blue Swirl | |
1373 | 38482a77 | Blue Swirl | static uint32_t compute_C_logic(void) |
1374 | 38482a77 | Blue Swirl | { |
1375 | 38482a77 | Blue Swirl | return 0; |
1376 | 38482a77 | Blue Swirl | } |
1377 | 38482a77 | Blue Swirl | |
1378 | 38482a77 | Blue Swirl | #ifdef TARGET_SPARC64
|
1379 | 38482a77 | Blue Swirl | static uint32_t compute_all_logic_xcc(void) |
1380 | 38482a77 | Blue Swirl | { |
1381 | 38482a77 | Blue Swirl | return get_NZ_xcc(CC_DST);
|
1382 | 38482a77 | Blue Swirl | } |
1383 | 38482a77 | Blue Swirl | #endif
|
1384 | 38482a77 | Blue Swirl | |
1385 | 8393617c | Blue Swirl | typedef struct CCTable { |
1386 | 8393617c | Blue Swirl | uint32_t (*compute_all)(void); /* return all the flags */ |
1387 | 8393617c | Blue Swirl | uint32_t (*compute_c)(void); /* return the C flag */ |
1388 | 8393617c | Blue Swirl | } CCTable; |
1389 | 8393617c | Blue Swirl | |
1390 | 8393617c | Blue Swirl | static const CCTable icc_table[CC_OP_NB] = { |
1391 | 8393617c | Blue Swirl | /* CC_OP_DYNAMIC should never happen */
|
1392 | 8393617c | Blue Swirl | [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, |
1393 | 6c78ea32 | Blue Swirl | [CC_OP_DIV] = { compute_all_div, compute_C_div }, |
1394 | bdf9f35d | Blue Swirl | [CC_OP_ADD] = { compute_all_add, compute_C_add }, |
1395 | 5a4bb580 | Richard Henderson | [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, |
1396 | 5a4bb580 | Richard Henderson | [CC_OP_TADD] = { compute_all_tadd, compute_C_add }, |
1397 | 5a4bb580 | Richard Henderson | [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add }, |
1398 | d4b0d468 | Blue Swirl | [CC_OP_SUB] = { compute_all_sub, compute_C_sub }, |
1399 | 5a4bb580 | Richard Henderson | [CC_OP_SUBX] = { compute_all_subx, compute_C_subx }, |
1400 | 5a4bb580 | Richard Henderson | [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub }, |
1401 | 5a4bb580 | Richard Henderson | [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub }, |
1402 | 38482a77 | Blue Swirl | [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, |
1403 | 8393617c | Blue Swirl | }; |
1404 | 8393617c | Blue Swirl | |
1405 | 8393617c | Blue Swirl | #ifdef TARGET_SPARC64
|
1406 | 8393617c | Blue Swirl | static const CCTable xcc_table[CC_OP_NB] = { |
1407 | 8393617c | Blue Swirl | /* CC_OP_DYNAMIC should never happen */
|
1408 | 8393617c | Blue Swirl | [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, |
1409 | 6c78ea32 | Blue Swirl | [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic }, |
1410 | bdf9f35d | Blue Swirl | [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1411 | 789c91ef | Blue Swirl | [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, |
1412 | 3b2d1e92 | Blue Swirl | [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, |
1413 | 3b2d1e92 | Blue Swirl | [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc }, |
1414 | d4b0d468 | Blue Swirl | [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1415 | 2ca1d92b | Blue Swirl | [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc }, |
1416 | 3b2d1e92 | Blue Swirl | [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1417 | 3b2d1e92 | Blue Swirl | [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc }, |
1418 | 38482a77 | Blue Swirl | [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, |
1419 | 8393617c | Blue Swirl | }; |
1420 | 8393617c | Blue Swirl | #endif
|
1421 | 8393617c | Blue Swirl | |
1422 | 8393617c | Blue Swirl | void helper_compute_psr(void) |
1423 | 8393617c | Blue Swirl | { |
1424 | 8393617c | Blue Swirl | uint32_t new_psr; |
1425 | 8393617c | Blue Swirl | |
1426 | 8393617c | Blue Swirl | new_psr = icc_table[CC_OP].compute_all(); |
1427 | 8393617c | Blue Swirl | env->psr = new_psr; |
1428 | 8393617c | Blue Swirl | #ifdef TARGET_SPARC64
|
1429 | 8393617c | Blue Swirl | new_psr = xcc_table[CC_OP].compute_all(); |
1430 | 8393617c | Blue Swirl | env->xcc = new_psr; |
1431 | 8393617c | Blue Swirl | #endif
|
1432 | 8393617c | Blue Swirl | CC_OP = CC_OP_FLAGS; |
1433 | 8393617c | Blue Swirl | } |
1434 | 8393617c | Blue Swirl | |
1435 | 70c48285 | Richard Henderson | uint32_t helper_compute_C_icc(void)
|
1436 | 8393617c | Blue Swirl | { |
1437 | 8393617c | Blue Swirl | uint32_t ret; |
1438 | 8393617c | Blue Swirl | |
1439 | 8393617c | Blue Swirl | ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT; |
1440 | 8393617c | Blue Swirl | return ret;
|
1441 | 8393617c | Blue Swirl | } |
1442 | 8393617c | Blue Swirl | |
1443 | 5a834bb4 | Blue Swirl | static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
1444 | 5a834bb4 | Blue Swirl | { |
1445 | 5a834bb4 | Blue Swirl | dst[0] = src[0]; |
1446 | 5a834bb4 | Blue Swirl | dst[1] = src[1]; |
1447 | 5a834bb4 | Blue Swirl | dst[2] = src[2]; |
1448 | 5a834bb4 | Blue Swirl | dst[3] = src[3]; |
1449 | 5a834bb4 | Blue Swirl | dst[4] = src[4]; |
1450 | 5a834bb4 | Blue Swirl | dst[5] = src[5]; |
1451 | 5a834bb4 | Blue Swirl | dst[6] = src[6]; |
1452 | 5a834bb4 | Blue Swirl | dst[7] = src[7]; |
1453 | 5a834bb4 | Blue Swirl | } |
1454 | 5a834bb4 | Blue Swirl | |
1455 | 5a834bb4 | Blue Swirl | static void set_cwp(int new_cwp) |
1456 | 5a834bb4 | Blue Swirl | { |
1457 | 5a834bb4 | Blue Swirl | /* put the modified wrap registers at their proper location */
|
1458 | 5a834bb4 | Blue Swirl | if (env->cwp == env->nwindows - 1) { |
1459 | 5a834bb4 | Blue Swirl | memcpy32(env->regbase, env->regbase + env->nwindows * 16);
|
1460 | 5a834bb4 | Blue Swirl | } |
1461 | 5a834bb4 | Blue Swirl | env->cwp = new_cwp; |
1462 | 5a834bb4 | Blue Swirl | |
1463 | 5a834bb4 | Blue Swirl | /* put the wrap registers at their temporary location */
|
1464 | 5a834bb4 | Blue Swirl | if (new_cwp == env->nwindows - 1) { |
1465 | 5a834bb4 | Blue Swirl | memcpy32(env->regbase + env->nwindows * 16, env->regbase);
|
1466 | 5a834bb4 | Blue Swirl | } |
1467 | 5a834bb4 | Blue Swirl | env->regwptr = env->regbase + (new_cwp * 16);
|
1468 | 5a834bb4 | Blue Swirl | } |
1469 | 5a834bb4 | Blue Swirl | |
1470 | 5a834bb4 | Blue Swirl | void cpu_set_cwp(CPUState *env1, int new_cwp) |
1471 | 5a834bb4 | Blue Swirl | { |
1472 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1473 | 5a834bb4 | Blue Swirl | |
1474 | 5a834bb4 | Blue Swirl | saved_env = env; |
1475 | 5a834bb4 | Blue Swirl | env = env1; |
1476 | 5a834bb4 | Blue Swirl | set_cwp(new_cwp); |
1477 | 5a834bb4 | Blue Swirl | env = saved_env; |
1478 | 5a834bb4 | Blue Swirl | } |
1479 | 5a834bb4 | Blue Swirl | |
1480 | 5a834bb4 | Blue Swirl | static target_ulong get_psr(void) |
1481 | 5a834bb4 | Blue Swirl | { |
1482 | 5a834bb4 | Blue Swirl | helper_compute_psr(); |
1483 | 5a834bb4 | Blue Swirl | |
1484 | 5a834bb4 | Blue Swirl | #if !defined (TARGET_SPARC64)
|
1485 | 5a834bb4 | Blue Swirl | return env->version | (env->psr & PSR_ICC) |
|
1486 | 5a834bb4 | Blue Swirl | (env->psref? PSR_EF : 0) |
|
1487 | 5a834bb4 | Blue Swirl | (env->psrpil << 8) |
|
1488 | 5a834bb4 | Blue Swirl | (env->psrs? PSR_S : 0) |
|
1489 | 5a834bb4 | Blue Swirl | (env->psrps? PSR_PS : 0) |
|
1490 | 5a834bb4 | Blue Swirl | (env->psret? PSR_ET : 0) | env->cwp;
|
1491 | 5a834bb4 | Blue Swirl | #else
|
1492 | 2aae2b8e | Igor V. Kovalenko | return env->psr & PSR_ICC;
|
1493 | 5a834bb4 | Blue Swirl | #endif
|
1494 | 5a834bb4 | Blue Swirl | } |
1495 | 5a834bb4 | Blue Swirl | |
1496 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_psr(CPUState *env1) |
1497 | 5a834bb4 | Blue Swirl | { |
1498 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1499 | 5a834bb4 | Blue Swirl | target_ulong ret; |
1500 | 5a834bb4 | Blue Swirl | |
1501 | 5a834bb4 | Blue Swirl | saved_env = env; |
1502 | 5a834bb4 | Blue Swirl | env = env1; |
1503 | 5a834bb4 | Blue Swirl | ret = get_psr(); |
1504 | 5a834bb4 | Blue Swirl | env = saved_env; |
1505 | 5a834bb4 | Blue Swirl | return ret;
|
1506 | 5a834bb4 | Blue Swirl | } |
1507 | 5a834bb4 | Blue Swirl | |
1508 | 5a834bb4 | Blue Swirl | static void put_psr(target_ulong val) |
1509 | 5a834bb4 | Blue Swirl | { |
1510 | 5a834bb4 | Blue Swirl | env->psr = val & PSR_ICC; |
1511 | 2aae2b8e | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
1512 | 5a834bb4 | Blue Swirl | env->psref = (val & PSR_EF)? 1 : 0; |
1513 | 5a834bb4 | Blue Swirl | env->psrpil = (val & PSR_PIL) >> 8;
|
1514 | 2aae2b8e | Igor V. Kovalenko | #endif
|
1515 | 5a834bb4 | Blue Swirl | #if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
|
1516 | 5a834bb4 | Blue Swirl | cpu_check_irqs(env); |
1517 | 5a834bb4 | Blue Swirl | #endif
|
1518 | 2aae2b8e | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
1519 | 5a834bb4 | Blue Swirl | env->psrs = (val & PSR_S)? 1 : 0; |
1520 | 5a834bb4 | Blue Swirl | env->psrps = (val & PSR_PS)? 1 : 0; |
1521 | 5a834bb4 | Blue Swirl | env->psret = (val & PSR_ET)? 1 : 0; |
1522 | 5a834bb4 | Blue Swirl | set_cwp(val & PSR_CWP); |
1523 | 2aae2b8e | Igor V. Kovalenko | #endif
|
1524 | 5a834bb4 | Blue Swirl | env->cc_op = CC_OP_FLAGS; |
1525 | 5a834bb4 | Blue Swirl | } |
1526 | 5a834bb4 | Blue Swirl | |
1527 | 5a834bb4 | Blue Swirl | void cpu_put_psr(CPUState *env1, target_ulong val)
|
1528 | 5a834bb4 | Blue Swirl | { |
1529 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1530 | 5a834bb4 | Blue Swirl | |
1531 | 5a834bb4 | Blue Swirl | saved_env = env; |
1532 | 5a834bb4 | Blue Swirl | env = env1; |
1533 | 5a834bb4 | Blue Swirl | put_psr(val); |
1534 | 5a834bb4 | Blue Swirl | env = saved_env; |
1535 | 5a834bb4 | Blue Swirl | } |
1536 | 5a834bb4 | Blue Swirl | |
1537 | 5a834bb4 | Blue Swirl | static int cwp_inc(int cwp) |
1538 | 5a834bb4 | Blue Swirl | { |
1539 | 5a834bb4 | Blue Swirl | if (unlikely(cwp >= env->nwindows)) {
|
1540 | 5a834bb4 | Blue Swirl | cwp -= env->nwindows; |
1541 | 5a834bb4 | Blue Swirl | } |
1542 | 5a834bb4 | Blue Swirl | return cwp;
|
1543 | 5a834bb4 | Blue Swirl | } |
1544 | 5a834bb4 | Blue Swirl | |
1545 | 5a834bb4 | Blue Swirl | int cpu_cwp_inc(CPUState *env1, int cwp) |
1546 | 5a834bb4 | Blue Swirl | { |
1547 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1548 | 5a834bb4 | Blue Swirl | target_ulong ret; |
1549 | 5a834bb4 | Blue Swirl | |
1550 | 5a834bb4 | Blue Swirl | saved_env = env; |
1551 | 5a834bb4 | Blue Swirl | env = env1; |
1552 | 5a834bb4 | Blue Swirl | ret = cwp_inc(cwp); |
1553 | 5a834bb4 | Blue Swirl | env = saved_env; |
1554 | 5a834bb4 | Blue Swirl | return ret;
|
1555 | 5a834bb4 | Blue Swirl | } |
1556 | 5a834bb4 | Blue Swirl | |
1557 | 5a834bb4 | Blue Swirl | static int cwp_dec(int cwp) |
1558 | 5a834bb4 | Blue Swirl | { |
1559 | 5a834bb4 | Blue Swirl | if (unlikely(cwp < 0)) { |
1560 | 5a834bb4 | Blue Swirl | cwp += env->nwindows; |
1561 | 5a834bb4 | Blue Swirl | } |
1562 | 5a834bb4 | Blue Swirl | return cwp;
|
1563 | 5a834bb4 | Blue Swirl | } |
1564 | 5a834bb4 | Blue Swirl | |
1565 | 5a834bb4 | Blue Swirl | int cpu_cwp_dec(CPUState *env1, int cwp) |
1566 | 5a834bb4 | Blue Swirl | { |
1567 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
1568 | 5a834bb4 | Blue Swirl | target_ulong ret; |
1569 | 5a834bb4 | Blue Swirl | |
1570 | 5a834bb4 | Blue Swirl | saved_env = env; |
1571 | 5a834bb4 | Blue Swirl | env = env1; |
1572 | 5a834bb4 | Blue Swirl | ret = cwp_dec(cwp); |
1573 | 5a834bb4 | Blue Swirl | env = saved_env; |
1574 | 5a834bb4 | Blue Swirl | return ret;
|
1575 | 5a834bb4 | Blue Swirl | } |
1576 | 5a834bb4 | Blue Swirl | |
1577 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1578 | 714547bb | blueswir1 | GEN_FCMPS(fcmps_fcc1, float32, 22, 0); |
1579 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
1580 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); |
1581 | 417454b0 | blueswir1 | |
1582 | 714547bb | blueswir1 | GEN_FCMPS(fcmps_fcc2, float32, 24, 0); |
1583 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
1584 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); |
1585 | 417454b0 | blueswir1 | |
1586 | 714547bb | blueswir1 | GEN_FCMPS(fcmps_fcc3, float32, 26, 0); |
1587 | 417454b0 | blueswir1 | GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
1588 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); |
1589 | 417454b0 | blueswir1 | |
1590 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes_fcc1, float32, 22, 1); |
1591 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
1592 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); |
1593 | 3475187d | bellard | |
1594 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes_fcc2, float32, 24, 1); |
1595 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
1596 | 64a88d5d | blueswir1 | GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); |
1597 | 3475187d | bellard | |
1598 | 714547bb | blueswir1 | GEN_FCMPS(fcmpes_fcc3, float32, 26, 1); |
1599 | 417454b0 | blueswir1 | GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
1600 | 4e14008f | blueswir1 | GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
1601 | 4e14008f | blueswir1 | #endif
|
1602 | 714547bb | blueswir1 | #undef GEN_FCMPS
|
1603 | 3475187d | bellard | |
1604 | 77f193da | blueswir1 | #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
|
1605 | 77f193da | blueswir1 | defined(DEBUG_MXCC) |
1606 | 952a328f | blueswir1 | static void dump_mxcc(CPUState *env) |
1607 | 952a328f | blueswir1 | { |
1608 | 0bf9e31a | Blue Swirl | printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1609 | 0bf9e31a | Blue Swirl | "\n",
|
1610 | 77f193da | blueswir1 | env->mxccdata[0], env->mxccdata[1], |
1611 | 77f193da | blueswir1 | env->mxccdata[2], env->mxccdata[3]); |
1612 | 0bf9e31a | Blue Swirl | printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1613 | 0bf9e31a | Blue Swirl | "\n"
|
1614 | 0bf9e31a | Blue Swirl | " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 |
1615 | 0bf9e31a | Blue Swirl | "\n",
|
1616 | 77f193da | blueswir1 | env->mxccregs[0], env->mxccregs[1], |
1617 | 77f193da | blueswir1 | env->mxccregs[2], env->mxccregs[3], |
1618 | 77f193da | blueswir1 | env->mxccregs[4], env->mxccregs[5], |
1619 | 77f193da | blueswir1 | env->mxccregs[6], env->mxccregs[7]); |
1620 | 952a328f | blueswir1 | } |
1621 | 952a328f | blueswir1 | #endif
|
1622 | 952a328f | blueswir1 | |
1623 | 1a2fb1c0 | blueswir1 | #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
|
1624 | 1a2fb1c0 | blueswir1 | && defined(DEBUG_ASI) |
1625 | 1a2fb1c0 | blueswir1 | static void dump_asi(const char *txt, target_ulong addr, int asi, int size, |
1626 | 1a2fb1c0 | blueswir1 | uint64_t r1) |
1627 | 8543e2cf | blueswir1 | { |
1628 | 8543e2cf | blueswir1 | switch (size)
|
1629 | 8543e2cf | blueswir1 | { |
1630 | 8543e2cf | blueswir1 | case 1: |
1631 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
1632 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xff);
|
1633 | 8543e2cf | blueswir1 | break;
|
1634 | 8543e2cf | blueswir1 | case 2: |
1635 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
1636 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xffff);
|
1637 | 8543e2cf | blueswir1 | break;
|
1638 | 8543e2cf | blueswir1 | case 4: |
1639 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
1640 | 1a2fb1c0 | blueswir1 | addr, asi, r1 & 0xffffffff);
|
1641 | 8543e2cf | blueswir1 | break;
|
1642 | 8543e2cf | blueswir1 | case 8: |
1643 | 1a2fb1c0 | blueswir1 | DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
1644 | 1a2fb1c0 | blueswir1 | addr, asi, r1); |
1645 | 8543e2cf | blueswir1 | break;
|
1646 | 8543e2cf | blueswir1 | } |
1647 | 8543e2cf | blueswir1 | } |
1648 | 8543e2cf | blueswir1 | #endif
|
1649 | 8543e2cf | blueswir1 | |
1650 | 1a2fb1c0 | blueswir1 | #ifndef TARGET_SPARC64
|
1651 | 1a2fb1c0 | blueswir1 | #ifndef CONFIG_USER_ONLY
|
1652 | b04d9890 | Fabien Chouteau | |
1653 | b04d9890 | Fabien Chouteau | |
1654 | b04d9890 | Fabien Chouteau | /* Leon3 cache control */
|
1655 | b04d9890 | Fabien Chouteau | |
1656 | 60f356e8 | Fabien Chouteau | static void leon3_cache_control_int(void) |
1657 | b04d9890 | Fabien Chouteau | { |
1658 | b04d9890 | Fabien Chouteau | uint32_t state = 0;
|
1659 | b04d9890 | Fabien Chouteau | |
1660 | b04d9890 | Fabien Chouteau | if (env->cache_control & CACHE_CTRL_IF) {
|
1661 | b04d9890 | Fabien Chouteau | /* Instruction cache state */
|
1662 | b04d9890 | Fabien Chouteau | state = env->cache_control & CACHE_STATE_MASK; |
1663 | b04d9890 | Fabien Chouteau | if (state == CACHE_ENABLED) {
|
1664 | b04d9890 | Fabien Chouteau | state = CACHE_FROZEN; |
1665 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
|
1666 | b04d9890 | Fabien Chouteau | } |
1667 | b04d9890 | Fabien Chouteau | |
1668 | b04d9890 | Fabien Chouteau | env->cache_control &= ~CACHE_STATE_MASK; |
1669 | b04d9890 | Fabien Chouteau | env->cache_control |= state; |
1670 | b04d9890 | Fabien Chouteau | } |
1671 | b04d9890 | Fabien Chouteau | |
1672 | b04d9890 | Fabien Chouteau | if (env->cache_control & CACHE_CTRL_DF) {
|
1673 | b04d9890 | Fabien Chouteau | /* Data cache state */
|
1674 | b04d9890 | Fabien Chouteau | state = (env->cache_control >> 2) & CACHE_STATE_MASK;
|
1675 | b04d9890 | Fabien Chouteau | if (state == CACHE_ENABLED) {
|
1676 | b04d9890 | Fabien Chouteau | state = CACHE_FROZEN; |
1677 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
|
1678 | b04d9890 | Fabien Chouteau | } |
1679 | b04d9890 | Fabien Chouteau | |
1680 | b04d9890 | Fabien Chouteau | env->cache_control &= ~(CACHE_STATE_MASK << 2);
|
1681 | b04d9890 | Fabien Chouteau | env->cache_control |= (state << 2);
|
1682 | b04d9890 | Fabien Chouteau | } |
1683 | b04d9890 | Fabien Chouteau | } |
1684 | b04d9890 | Fabien Chouteau | |
1685 | b04d9890 | Fabien Chouteau | static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size) |
1686 | b04d9890 | Fabien Chouteau | { |
1687 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", |
1688 | b04d9890 | Fabien Chouteau | addr, val, size); |
1689 | b04d9890 | Fabien Chouteau | |
1690 | b04d9890 | Fabien Chouteau | if (size != 4) { |
1691 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("32bits only\n");
|
1692 | b04d9890 | Fabien Chouteau | return;
|
1693 | b04d9890 | Fabien Chouteau | } |
1694 | b04d9890 | Fabien Chouteau | |
1695 | b04d9890 | Fabien Chouteau | switch (addr) {
|
1696 | b04d9890 | Fabien Chouteau | case 0x00: /* Cache control */ |
1697 | b04d9890 | Fabien Chouteau | |
1698 | b04d9890 | Fabien Chouteau | /* These values must always be read as zeros */
|
1699 | b04d9890 | Fabien Chouteau | val &= ~CACHE_CTRL_FD; |
1700 | b04d9890 | Fabien Chouteau | val &= ~CACHE_CTRL_FI; |
1701 | b04d9890 | Fabien Chouteau | val &= ~CACHE_CTRL_IB; |
1702 | b04d9890 | Fabien Chouteau | val &= ~CACHE_CTRL_IP; |
1703 | b04d9890 | Fabien Chouteau | val &= ~CACHE_CTRL_DP; |
1704 | b04d9890 | Fabien Chouteau | |
1705 | b04d9890 | Fabien Chouteau | env->cache_control = val; |
1706 | b04d9890 | Fabien Chouteau | break;
|
1707 | b04d9890 | Fabien Chouteau | case 0x04: /* Instruction cache configuration */ |
1708 | b04d9890 | Fabien Chouteau | case 0x08: /* Data cache configuration */ |
1709 | b04d9890 | Fabien Chouteau | /* Read Only */
|
1710 | b04d9890 | Fabien Chouteau | break;
|
1711 | b04d9890 | Fabien Chouteau | default:
|
1712 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
|
1713 | b04d9890 | Fabien Chouteau | break;
|
1714 | b04d9890 | Fabien Chouteau | }; |
1715 | b04d9890 | Fabien Chouteau | } |
1716 | b04d9890 | Fabien Chouteau | |
1717 | b04d9890 | Fabien Chouteau | static uint64_t leon3_cache_control_ld(target_ulong addr, int size) |
1718 | b04d9890 | Fabien Chouteau | { |
1719 | b04d9890 | Fabien Chouteau | uint64_t ret = 0;
|
1720 | b04d9890 | Fabien Chouteau | |
1721 | b04d9890 | Fabien Chouteau | if (size != 4) { |
1722 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("32bits only\n");
|
1723 | b04d9890 | Fabien Chouteau | return 0; |
1724 | b04d9890 | Fabien Chouteau | } |
1725 | b04d9890 | Fabien Chouteau | |
1726 | b04d9890 | Fabien Chouteau | switch (addr) {
|
1727 | b04d9890 | Fabien Chouteau | case 0x00: /* Cache control */ |
1728 | b04d9890 | Fabien Chouteau | ret = env->cache_control; |
1729 | b04d9890 | Fabien Chouteau | break;
|
1730 | b04d9890 | Fabien Chouteau | |
1731 | b04d9890 | Fabien Chouteau | /* Configuration registers are read and only always keep those
|
1732 | b04d9890 | Fabien Chouteau | predefined values */
|
1733 | b04d9890 | Fabien Chouteau | |
1734 | b04d9890 | Fabien Chouteau | case 0x04: /* Instruction cache configuration */ |
1735 | b04d9890 | Fabien Chouteau | ret = 0x10220000;
|
1736 | b04d9890 | Fabien Chouteau | break;
|
1737 | b04d9890 | Fabien Chouteau | case 0x08: /* Data cache configuration */ |
1738 | b04d9890 | Fabien Chouteau | ret = 0x18220000;
|
1739 | b04d9890 | Fabien Chouteau | break;
|
1740 | b04d9890 | Fabien Chouteau | default:
|
1741 | b04d9890 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
|
1742 | b04d9890 | Fabien Chouteau | break;
|
1743 | b04d9890 | Fabien Chouteau | }; |
1744 | 60f356e8 | Fabien Chouteau | DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n", |
1745 | b04d9890 | Fabien Chouteau | addr, ret, size); |
1746 | b04d9890 | Fabien Chouteau | return ret;
|
1747 | b04d9890 | Fabien Chouteau | } |
1748 | b04d9890 | Fabien Chouteau | |
1749 | 60f356e8 | Fabien Chouteau | void leon3_irq_manager(void *irq_manager, int intno) |
1750 | 60f356e8 | Fabien Chouteau | { |
1751 | 60f356e8 | Fabien Chouteau | leon3_irq_ack(irq_manager, intno); |
1752 | 60f356e8 | Fabien Chouteau | leon3_cache_control_int(); |
1753 | 60f356e8 | Fabien Chouteau | } |
1754 | 60f356e8 | Fabien Chouteau | |
1755 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
1756 | e8af50a3 | bellard | { |
1757 | 1a2fb1c0 | blueswir1 | uint64_t ret = 0;
|
1758 | 8543e2cf | blueswir1 | #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
|
1759 | 1a2fb1c0 | blueswir1 | uint32_t last_addr = addr; |
1760 | 952a328f | blueswir1 | #endif
|
1761 | e80cfcfc | bellard | |
1762 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
1763 | e80cfcfc | bellard | switch (asi) {
|
1764 | b04d9890 | Fabien Chouteau | case 2: /* SuperSparc MXCC registers and Leon3 cache control */ |
1765 | 1a2fb1c0 | blueswir1 | switch (addr) {
|
1766 | b04d9890 | Fabien Chouteau | case 0x00: /* Leon3 Cache Control */ |
1767 | b04d9890 | Fabien Chouteau | case 0x08: /* Leon3 Instruction Cache config */ |
1768 | b04d9890 | Fabien Chouteau | case 0x0C: /* Leon3 Date Cache config */ |
1769 | 60f356e8 | Fabien Chouteau | if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
|
1770 | 60f356e8 | Fabien Chouteau | ret = leon3_cache_control_ld(addr, size); |
1771 | 60f356e8 | Fabien Chouteau | } |
1772 | b04d9890 | Fabien Chouteau | break;
|
1773 | 952a328f | blueswir1 | case 0x01c00a00: /* MXCC control register */ |
1774 | 1a2fb1c0 | blueswir1 | if (size == 8) |
1775 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[3];
|
1776 | 1a2fb1c0 | blueswir1 | else
|
1777 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1778 | 77f193da | blueswir1 | size); |
1779 | 952a328f | blueswir1 | break;
|
1780 | 952a328f | blueswir1 | case 0x01c00a04: /* MXCC control register */ |
1781 | 952a328f | blueswir1 | if (size == 4) |
1782 | 952a328f | blueswir1 | ret = env->mxccregs[3];
|
1783 | 952a328f | blueswir1 | else
|
1784 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1785 | 77f193da | blueswir1 | size); |
1786 | 952a328f | blueswir1 | break;
|
1787 | 295db113 | blueswir1 | case 0x01c00c00: /* Module reset register */ |
1788 | 295db113 | blueswir1 | if (size == 8) { |
1789 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[5];
|
1790 | 295db113 | blueswir1 | // should we do something here?
|
1791 | 295db113 | blueswir1 | } else
|
1792 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1793 | 77f193da | blueswir1 | size); |
1794 | 295db113 | blueswir1 | break;
|
1795 | 952a328f | blueswir1 | case 0x01c00f00: /* MBus port address register */ |
1796 | 1a2fb1c0 | blueswir1 | if (size == 8) |
1797 | 1a2fb1c0 | blueswir1 | ret = env->mxccregs[7];
|
1798 | 1a2fb1c0 | blueswir1 | else
|
1799 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
1800 | 77f193da | blueswir1 | size); |
1801 | 952a328f | blueswir1 | break;
|
1802 | 952a328f | blueswir1 | default:
|
1803 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
1804 | 77f193da | blueswir1 | size); |
1805 | 952a328f | blueswir1 | break;
|
1806 | 952a328f | blueswir1 | } |
1807 | 77f193da | blueswir1 | DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
|
1808 | 9827e450 | blueswir1 | "addr = %08x -> ret = %" PRIx64 "," |
1809 | 1a2fb1c0 | blueswir1 | "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
1810 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
1811 | 952a328f | blueswir1 | dump_mxcc(env); |
1812 | 952a328f | blueswir1 | #endif
|
1813 | 6c36d3fa | blueswir1 | break;
|
1814 | e8af50a3 | bellard | case 3: /* MMU probe */ |
1815 | 0f8a249a | blueswir1 | { |
1816 | 0f8a249a | blueswir1 | int mmulev;
|
1817 | 0f8a249a | blueswir1 | |
1818 | 1a2fb1c0 | blueswir1 | mmulev = (addr >> 8) & 15; |
1819 | 0f8a249a | blueswir1 | if (mmulev > 4) |
1820 | 0f8a249a | blueswir1 | ret = 0;
|
1821 | 1a2fb1c0 | blueswir1 | else
|
1822 | 1a2fb1c0 | blueswir1 | ret = mmu_probe(env, addr, mmulev); |
1823 | 1a2fb1c0 | blueswir1 | DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", |
1824 | 1a2fb1c0 | blueswir1 | addr, mmulev, ret); |
1825 | 0f8a249a | blueswir1 | } |
1826 | 0f8a249a | blueswir1 | break;
|
1827 | e8af50a3 | bellard | case 4: /* read MMU regs */ |
1828 | 0f8a249a | blueswir1 | { |
1829 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 8) & 0x1f; |
1830 | 3b46e624 | ths | |
1831 | 0f8a249a | blueswir1 | ret = env->mmuregs[reg]; |
1832 | 0f8a249a | blueswir1 | if (reg == 3) /* Fault status cleared on read */ |
1833 | 3dd9a152 | blueswir1 | env->mmuregs[3] = 0; |
1834 | 3dd9a152 | blueswir1 | else if (reg == 0x13) /* Fault status read */ |
1835 | 3dd9a152 | blueswir1 | ret = env->mmuregs[3];
|
1836 | 3dd9a152 | blueswir1 | else if (reg == 0x14) /* Fault address read */ |
1837 | 3dd9a152 | blueswir1 | ret = env->mmuregs[4];
|
1838 | 1a2fb1c0 | blueswir1 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
1839 | 0f8a249a | blueswir1 | } |
1840 | 0f8a249a | blueswir1 | break;
|
1841 | 045380be | blueswir1 | case 5: // Turbosparc ITLB Diagnostic |
1842 | 045380be | blueswir1 | case 6: // Turbosparc DTLB Diagnostic |
1843 | 045380be | blueswir1 | case 7: // Turbosparc IOTLB Diagnostic |
1844 | 045380be | blueswir1 | break;
|
1845 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access */ |
1846 | 6c36d3fa | blueswir1 | switch(size) {
|
1847 | 6c36d3fa | blueswir1 | case 1: |
1848 | 1a2fb1c0 | blueswir1 | ret = ldub_code(addr); |
1849 | 6c36d3fa | blueswir1 | break;
|
1850 | 6c36d3fa | blueswir1 | case 2: |
1851 | a4e7dd52 | blueswir1 | ret = lduw_code(addr); |
1852 | 6c36d3fa | blueswir1 | break;
|
1853 | 6c36d3fa | blueswir1 | default:
|
1854 | 6c36d3fa | blueswir1 | case 4: |
1855 | a4e7dd52 | blueswir1 | ret = ldl_code(addr); |
1856 | 6c36d3fa | blueswir1 | break;
|
1857 | 6c36d3fa | blueswir1 | case 8: |
1858 | a4e7dd52 | blueswir1 | ret = ldq_code(addr); |
1859 | 6c36d3fa | blueswir1 | break;
|
1860 | 6c36d3fa | blueswir1 | } |
1861 | 6c36d3fa | blueswir1 | break;
|
1862 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
1863 | 81ad8ba2 | blueswir1 | switch(size) {
|
1864 | 81ad8ba2 | blueswir1 | case 1: |
1865 | 1a2fb1c0 | blueswir1 | ret = ldub_user(addr); |
1866 | 81ad8ba2 | blueswir1 | break;
|
1867 | 81ad8ba2 | blueswir1 | case 2: |
1868 | a4e7dd52 | blueswir1 | ret = lduw_user(addr); |
1869 | 81ad8ba2 | blueswir1 | break;
|
1870 | 81ad8ba2 | blueswir1 | default:
|
1871 | 81ad8ba2 | blueswir1 | case 4: |
1872 | a4e7dd52 | blueswir1 | ret = ldl_user(addr); |
1873 | 81ad8ba2 | blueswir1 | break;
|
1874 | 81ad8ba2 | blueswir1 | case 8: |
1875 | a4e7dd52 | blueswir1 | ret = ldq_user(addr); |
1876 | 81ad8ba2 | blueswir1 | break;
|
1877 | 81ad8ba2 | blueswir1 | } |
1878 | 81ad8ba2 | blueswir1 | break;
|
1879 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
1880 | 81ad8ba2 | blueswir1 | switch(size) {
|
1881 | 81ad8ba2 | blueswir1 | case 1: |
1882 | 1a2fb1c0 | blueswir1 | ret = ldub_kernel(addr); |
1883 | 81ad8ba2 | blueswir1 | break;
|
1884 | 81ad8ba2 | blueswir1 | case 2: |
1885 | a4e7dd52 | blueswir1 | ret = lduw_kernel(addr); |
1886 | 81ad8ba2 | blueswir1 | break;
|
1887 | 81ad8ba2 | blueswir1 | default:
|
1888 | 81ad8ba2 | blueswir1 | case 4: |
1889 | a4e7dd52 | blueswir1 | ret = ldl_kernel(addr); |
1890 | 81ad8ba2 | blueswir1 | break;
|
1891 | 81ad8ba2 | blueswir1 | case 8: |
1892 | a4e7dd52 | blueswir1 | ret = ldq_kernel(addr); |
1893 | 81ad8ba2 | blueswir1 | break;
|
1894 | 81ad8ba2 | blueswir1 | } |
1895 | 81ad8ba2 | blueswir1 | break;
|
1896 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
1897 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
1898 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
1899 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
1900 | 6c36d3fa | blueswir1 | break;
|
1901 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
1902 | 02aab46a | bellard | switch(size) {
|
1903 | 02aab46a | bellard | case 1: |
1904 | 1a2fb1c0 | blueswir1 | ret = ldub_phys(addr); |
1905 | 02aab46a | bellard | break;
|
1906 | 02aab46a | bellard | case 2: |
1907 | a4e7dd52 | blueswir1 | ret = lduw_phys(addr); |
1908 | 02aab46a | bellard | break;
|
1909 | 02aab46a | bellard | default:
|
1910 | 02aab46a | bellard | case 4: |
1911 | a4e7dd52 | blueswir1 | ret = ldl_phys(addr); |
1912 | 02aab46a | bellard | break;
|
1913 | 9e61bde5 | bellard | case 8: |
1914 | a4e7dd52 | blueswir1 | ret = ldq_phys(addr); |
1915 | 0f8a249a | blueswir1 | break;
|
1916 | 02aab46a | bellard | } |
1917 | 0f8a249a | blueswir1 | break;
|
1918 | 7d85892b | blueswir1 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
1919 | 5dcb6b91 | blueswir1 | switch(size) {
|
1920 | 5dcb6b91 | blueswir1 | case 1: |
1921 | c227f099 | Anthony Liguori | ret = ldub_phys((target_phys_addr_t)addr |
1922 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1923 | 5dcb6b91 | blueswir1 | break;
|
1924 | 5dcb6b91 | blueswir1 | case 2: |
1925 | c227f099 | Anthony Liguori | ret = lduw_phys((target_phys_addr_t)addr |
1926 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1927 | 5dcb6b91 | blueswir1 | break;
|
1928 | 5dcb6b91 | blueswir1 | default:
|
1929 | 5dcb6b91 | blueswir1 | case 4: |
1930 | c227f099 | Anthony Liguori | ret = ldl_phys((target_phys_addr_t)addr |
1931 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1932 | 5dcb6b91 | blueswir1 | break;
|
1933 | 5dcb6b91 | blueswir1 | case 8: |
1934 | c227f099 | Anthony Liguori | ret = ldq_phys((target_phys_addr_t)addr |
1935 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32)); |
1936 | 0f8a249a | blueswir1 | break;
|
1937 | 5dcb6b91 | blueswir1 | } |
1938 | 0f8a249a | blueswir1 | break;
|
1939 | 045380be | blueswir1 | case 0x30: // Turbosparc secondary cache diagnostic |
1940 | 045380be | blueswir1 | case 0x31: // Turbosparc RAM snoop |
1941 | 045380be | blueswir1 | case 0x32: // Turbosparc page table descriptor diagnostic |
1942 | 666c87aa | blueswir1 | case 0x39: /* data cache diagnostic register */ |
1943 | 666c87aa | blueswir1 | ret = 0;
|
1944 | 666c87aa | blueswir1 | break;
|
1945 | 4017190e | blueswir1 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ |
1946 | 4017190e | blueswir1 | { |
1947 | 4017190e | blueswir1 | int reg = (addr >> 8) & 3; |
1948 | 4017190e | blueswir1 | |
1949 | 4017190e | blueswir1 | switch(reg) {
|
1950 | 4017190e | blueswir1 | case 0: /* Breakpoint Value (Addr) */ |
1951 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1952 | 4017190e | blueswir1 | break;
|
1953 | 4017190e | blueswir1 | case 1: /* Breakpoint Mask */ |
1954 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1955 | 4017190e | blueswir1 | break;
|
1956 | 4017190e | blueswir1 | case 2: /* Breakpoint Control */ |
1957 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1958 | 4017190e | blueswir1 | break;
|
1959 | 4017190e | blueswir1 | case 3: /* Breakpoint Status */ |
1960 | 4017190e | blueswir1 | ret = env->mmubpregs[reg]; |
1961 | 4017190e | blueswir1 | env->mmubpregs[reg] = 0ULL;
|
1962 | 4017190e | blueswir1 | break;
|
1963 | 4017190e | blueswir1 | } |
1964 | 0bf9e31a | Blue Swirl | DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg, |
1965 | 0bf9e31a | Blue Swirl | ret); |
1966 | 4017190e | blueswir1 | } |
1967 | 4017190e | blueswir1 | break;
|
1968 | 4d2c2b77 | Blue Swirl | case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
1969 | 4d2c2b77 | Blue Swirl | ret = env->mmubpctrv; |
1970 | 4d2c2b77 | Blue Swirl | break;
|
1971 | 4d2c2b77 | Blue Swirl | case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
1972 | 4d2c2b77 | Blue Swirl | ret = env->mmubpctrc; |
1973 | 4d2c2b77 | Blue Swirl | break;
|
1974 | 4d2c2b77 | Blue Swirl | case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
1975 | 4d2c2b77 | Blue Swirl | ret = env->mmubpctrs; |
1976 | 4d2c2b77 | Blue Swirl | break;
|
1977 | 4d2c2b77 | Blue Swirl | case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
1978 | 4d2c2b77 | Blue Swirl | ret = env->mmubpaction; |
1979 | 4d2c2b77 | Blue Swirl | break;
|
1980 | 045380be | blueswir1 | case 8: /* User code access, XXX */ |
1981 | e8af50a3 | bellard | default:
|
1982 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 0, asi, size); |
1983 | 0f8a249a | blueswir1 | ret = 0;
|
1984 | 0f8a249a | blueswir1 | break;
|
1985 | e8af50a3 | bellard | } |
1986 | 81ad8ba2 | blueswir1 | if (sign) {
|
1987 | 81ad8ba2 | blueswir1 | switch(size) {
|
1988 | 81ad8ba2 | blueswir1 | case 1: |
1989 | 1a2fb1c0 | blueswir1 | ret = (int8_t) ret; |
1990 | e32664fb | blueswir1 | break;
|
1991 | 81ad8ba2 | blueswir1 | case 2: |
1992 | 1a2fb1c0 | blueswir1 | ret = (int16_t) ret; |
1993 | 1a2fb1c0 | blueswir1 | break;
|
1994 | 1a2fb1c0 | blueswir1 | case 4: |
1995 | 1a2fb1c0 | blueswir1 | ret = (int32_t) ret; |
1996 | e32664fb | blueswir1 | break;
|
1997 | 81ad8ba2 | blueswir1 | default:
|
1998 | 81ad8ba2 | blueswir1 | break;
|
1999 | 81ad8ba2 | blueswir1 | } |
2000 | 81ad8ba2 | blueswir1 | } |
2001 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
2002 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2003 | 8543e2cf | blueswir1 | #endif
|
2004 | 1a2fb1c0 | blueswir1 | return ret;
|
2005 | e8af50a3 | bellard | } |
2006 | e8af50a3 | bellard | |
2007 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
2008 | e8af50a3 | bellard | { |
2009 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2010 | e8af50a3 | bellard | switch(asi) {
|
2011 | b04d9890 | Fabien Chouteau | case 2: /* SuperSparc MXCC registers and Leon3 cache control */ |
2012 | 1a2fb1c0 | blueswir1 | switch (addr) {
|
2013 | b04d9890 | Fabien Chouteau | case 0x00: /* Leon3 Cache Control */ |
2014 | b04d9890 | Fabien Chouteau | case 0x08: /* Leon3 Instruction Cache config */ |
2015 | b04d9890 | Fabien Chouteau | case 0x0C: /* Leon3 Date Cache config */ |
2016 | 60f356e8 | Fabien Chouteau | if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
|
2017 | 60f356e8 | Fabien Chouteau | leon3_cache_control_st(addr, val, size); |
2018 | 60f356e8 | Fabien Chouteau | } |
2019 | b04d9890 | Fabien Chouteau | break;
|
2020 | b04d9890 | Fabien Chouteau | |
2021 | 952a328f | blueswir1 | case 0x01c00000: /* MXCC stream data register 0 */ |
2022 | 952a328f | blueswir1 | if (size == 8) |
2023 | 1a2fb1c0 | blueswir1 | env->mxccdata[0] = val;
|
2024 | 952a328f | blueswir1 | else
|
2025 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2026 | 77f193da | blueswir1 | size); |
2027 | 952a328f | blueswir1 | break;
|
2028 | 952a328f | blueswir1 | case 0x01c00008: /* MXCC stream data register 1 */ |
2029 | 952a328f | blueswir1 | if (size == 8) |
2030 | 1a2fb1c0 | blueswir1 | env->mxccdata[1] = val;
|
2031 | 952a328f | blueswir1 | else
|
2032 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2033 | 77f193da | blueswir1 | size); |
2034 | 952a328f | blueswir1 | break;
|
2035 | 952a328f | blueswir1 | case 0x01c00010: /* MXCC stream data register 2 */ |
2036 | 952a328f | blueswir1 | if (size == 8) |
2037 | 1a2fb1c0 | blueswir1 | env->mxccdata[2] = val;
|
2038 | 952a328f | blueswir1 | else
|
2039 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2040 | 77f193da | blueswir1 | size); |
2041 | 952a328f | blueswir1 | break;
|
2042 | 952a328f | blueswir1 | case 0x01c00018: /* MXCC stream data register 3 */ |
2043 | 952a328f | blueswir1 | if (size == 8) |
2044 | 1a2fb1c0 | blueswir1 | env->mxccdata[3] = val;
|
2045 | 952a328f | blueswir1 | else
|
2046 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2047 | 77f193da | blueswir1 | size); |
2048 | 952a328f | blueswir1 | break;
|
2049 | 952a328f | blueswir1 | case 0x01c00100: /* MXCC stream source */ |
2050 | 952a328f | blueswir1 | if (size == 8) |
2051 | 1a2fb1c0 | blueswir1 | env->mxccregs[0] = val;
|
2052 | 952a328f | blueswir1 | else
|
2053 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2054 | 77f193da | blueswir1 | size); |
2055 | 77f193da | blueswir1 | env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2056 | 77f193da | blueswir1 | 0);
|
2057 | 77f193da | blueswir1 | env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2058 | 77f193da | blueswir1 | 8);
|
2059 | 77f193da | blueswir1 | env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2060 | 77f193da | blueswir1 | 16);
|
2061 | 77f193da | blueswir1 | env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + |
2062 | 77f193da | blueswir1 | 24);
|
2063 | 952a328f | blueswir1 | break;
|
2064 | 952a328f | blueswir1 | case 0x01c00200: /* MXCC stream destination */ |
2065 | 952a328f | blueswir1 | if (size == 8) |
2066 | 1a2fb1c0 | blueswir1 | env->mxccregs[1] = val;
|
2067 | 952a328f | blueswir1 | else
|
2068 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2069 | 77f193da | blueswir1 | size); |
2070 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, |
2071 | 77f193da | blueswir1 | env->mxccdata[0]);
|
2072 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, |
2073 | 77f193da | blueswir1 | env->mxccdata[1]);
|
2074 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, |
2075 | 77f193da | blueswir1 | env->mxccdata[2]);
|
2076 | 77f193da | blueswir1 | stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, |
2077 | 77f193da | blueswir1 | env->mxccdata[3]);
|
2078 | 952a328f | blueswir1 | break;
|
2079 | 952a328f | blueswir1 | case 0x01c00a00: /* MXCC control register */ |
2080 | 952a328f | blueswir1 | if (size == 8) |
2081 | 1a2fb1c0 | blueswir1 | env->mxccregs[3] = val;
|
2082 | 952a328f | blueswir1 | else
|
2083 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2084 | 77f193da | blueswir1 | size); |
2085 | 952a328f | blueswir1 | break;
|
2086 | 952a328f | blueswir1 | case 0x01c00a04: /* MXCC control register */ |
2087 | 952a328f | blueswir1 | if (size == 4) |
2088 | 9f4576f0 | blueswir1 | env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) |
2089 | 77f193da | blueswir1 | | val; |
2090 | 952a328f | blueswir1 | else
|
2091 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2092 | 77f193da | blueswir1 | size); |
2093 | 952a328f | blueswir1 | break;
|
2094 | 952a328f | blueswir1 | case 0x01c00e00: /* MXCC error register */ |
2095 | bbf7d96b | blueswir1 | // writing a 1 bit clears the error
|
2096 | 952a328f | blueswir1 | if (size == 8) |
2097 | 1a2fb1c0 | blueswir1 | env->mxccregs[6] &= ~val;
|
2098 | 952a328f | blueswir1 | else
|
2099 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2100 | 77f193da | blueswir1 | size); |
2101 | 952a328f | blueswir1 | break;
|
2102 | 952a328f | blueswir1 | case 0x01c00f00: /* MBus port address register */ |
2103 | 952a328f | blueswir1 | if (size == 8) |
2104 | 1a2fb1c0 | blueswir1 | env->mxccregs[7] = val;
|
2105 | 952a328f | blueswir1 | else
|
2106 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
|
2107 | 77f193da | blueswir1 | size); |
2108 | 952a328f | blueswir1 | break;
|
2109 | 952a328f | blueswir1 | default:
|
2110 | 77f193da | blueswir1 | DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
|
2111 | 77f193da | blueswir1 | size); |
2112 | 952a328f | blueswir1 | break;
|
2113 | 952a328f | blueswir1 | } |
2114 | 9827e450 | blueswir1 | DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", |
2115 | 9827e450 | blueswir1 | asi, size, addr, val); |
2116 | 952a328f | blueswir1 | #ifdef DEBUG_MXCC
|
2117 | 952a328f | blueswir1 | dump_mxcc(env); |
2118 | 952a328f | blueswir1 | #endif
|
2119 | 6c36d3fa | blueswir1 | break;
|
2120 | e8af50a3 | bellard | case 3: /* MMU flush */ |
2121 | 0f8a249a | blueswir1 | { |
2122 | 0f8a249a | blueswir1 | int mmulev;
|
2123 | e80cfcfc | bellard | |
2124 | 1a2fb1c0 | blueswir1 | mmulev = (addr >> 8) & 15; |
2125 | 952a328f | blueswir1 | DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
2126 | 0f8a249a | blueswir1 | switch (mmulev) {
|
2127 | 0f8a249a | blueswir1 | case 0: // flush page |
2128 | 1a2fb1c0 | blueswir1 | tlb_flush_page(env, addr & 0xfffff000);
|
2129 | 0f8a249a | blueswir1 | break;
|
2130 | 0f8a249a | blueswir1 | case 1: // flush segment (256k) |
2131 | 0f8a249a | blueswir1 | case 2: // flush region (16M) |
2132 | 0f8a249a | blueswir1 | case 3: // flush context (4G) |
2133 | 0f8a249a | blueswir1 | case 4: // flush entire |
2134 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
2135 | 0f8a249a | blueswir1 | break;
|
2136 | 0f8a249a | blueswir1 | default:
|
2137 | 0f8a249a | blueswir1 | break;
|
2138 | 0f8a249a | blueswir1 | } |
2139 | 55754d9e | bellard | #ifdef DEBUG_MMU
|
2140 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env); |
2141 | 55754d9e | bellard | #endif
|
2142 | 0f8a249a | blueswir1 | } |
2143 | 8543e2cf | blueswir1 | break;
|
2144 | e8af50a3 | bellard | case 4: /* write MMU regs */ |
2145 | 0f8a249a | blueswir1 | { |
2146 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 8) & 0x1f; |
2147 | 0f8a249a | blueswir1 | uint32_t oldreg; |
2148 | 3b46e624 | ths | |
2149 | 0f8a249a | blueswir1 | oldreg = env->mmuregs[reg]; |
2150 | 55754d9e | bellard | switch(reg) {
|
2151 | 3deaeab7 | blueswir1 | case 0: // Control Register |
2152 | 3dd9a152 | blueswir1 | env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
2153 | 1a2fb1c0 | blueswir1 | (val & 0x00ffffff);
|
2154 | 0f8a249a | blueswir1 | // Mappings generated during no-fault mode or MMU
|
2155 | 0f8a249a | blueswir1 | // disabled mode are invalid in normal mode
|
2156 | 5578ceab | blueswir1 | if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
|
2157 | 5578ceab | blueswir1 | (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) |
2158 | 55754d9e | bellard | tlb_flush(env, 1);
|
2159 | 55754d9e | bellard | break;
|
2160 | 3deaeab7 | blueswir1 | case 1: // Context Table Pointer Register |
2161 | 5578ceab | blueswir1 | env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; |
2162 | 3deaeab7 | blueswir1 | break;
|
2163 | 3deaeab7 | blueswir1 | case 2: // Context Register |
2164 | 5578ceab | blueswir1 | env->mmuregs[reg] = val & env->def->mmu_cxr_mask; |
2165 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
2166 | 55754d9e | bellard | /* we flush when the MMU context changes because
|
2167 | 55754d9e | bellard | QEMU has no MMU context support */
|
2168 | 55754d9e | bellard | tlb_flush(env, 1);
|
2169 | 55754d9e | bellard | } |
2170 | 55754d9e | bellard | break;
|
2171 | 3deaeab7 | blueswir1 | case 3: // Synchronous Fault Status Register with Clear |
2172 | 3deaeab7 | blueswir1 | case 4: // Synchronous Fault Address Register |
2173 | 3deaeab7 | blueswir1 | break;
|
2174 | 3deaeab7 | blueswir1 | case 0x10: // TLB Replacement Control Register |
2175 | 5578ceab | blueswir1 | env->mmuregs[reg] = val & env->def->mmu_trcr_mask; |
2176 | 55754d9e | bellard | break;
|
2177 | 3deaeab7 | blueswir1 | case 0x13: // Synchronous Fault Status Register with Read and Clear |
2178 | 5578ceab | blueswir1 | env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
|
2179 | 3dd9a152 | blueswir1 | break;
|
2180 | 3deaeab7 | blueswir1 | case 0x14: // Synchronous Fault Address Register |
2181 | 1a2fb1c0 | blueswir1 | env->mmuregs[4] = val;
|
2182 | 3dd9a152 | blueswir1 | break;
|
2183 | 55754d9e | bellard | default:
|
2184 | 1a2fb1c0 | blueswir1 | env->mmuregs[reg] = val; |
2185 | 55754d9e | bellard | break;
|
2186 | 55754d9e | bellard | } |
2187 | 55754d9e | bellard | if (oldreg != env->mmuregs[reg]) {
|
2188 | 77f193da | blueswir1 | DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
|
2189 | 77f193da | blueswir1 | reg, oldreg, env->mmuregs[reg]); |
2190 | 55754d9e | bellard | } |
2191 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
2192 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env); |
2193 | 55754d9e | bellard | #endif
|
2194 | 0f8a249a | blueswir1 | } |
2195 | 8543e2cf | blueswir1 | break;
|
2196 | 045380be | blueswir1 | case 5: // Turbosparc ITLB Diagnostic |
2197 | 045380be | blueswir1 | case 6: // Turbosparc DTLB Diagnostic |
2198 | 045380be | blueswir1 | case 7: // Turbosparc IOTLB Diagnostic |
2199 | 045380be | blueswir1 | break;
|
2200 | 81ad8ba2 | blueswir1 | case 0xa: /* User data access */ |
2201 | 81ad8ba2 | blueswir1 | switch(size) {
|
2202 | 81ad8ba2 | blueswir1 | case 1: |
2203 | 1a2fb1c0 | blueswir1 | stb_user(addr, val); |
2204 | 81ad8ba2 | blueswir1 | break;
|
2205 | 81ad8ba2 | blueswir1 | case 2: |
2206 | a4e7dd52 | blueswir1 | stw_user(addr, val); |
2207 | 81ad8ba2 | blueswir1 | break;
|
2208 | 81ad8ba2 | blueswir1 | default:
|
2209 | 81ad8ba2 | blueswir1 | case 4: |
2210 | a4e7dd52 | blueswir1 | stl_user(addr, val); |
2211 | 81ad8ba2 | blueswir1 | break;
|
2212 | 81ad8ba2 | blueswir1 | case 8: |
2213 | a4e7dd52 | blueswir1 | stq_user(addr, val); |
2214 | 81ad8ba2 | blueswir1 | break;
|
2215 | 81ad8ba2 | blueswir1 | } |
2216 | 81ad8ba2 | blueswir1 | break;
|
2217 | 81ad8ba2 | blueswir1 | case 0xb: /* Supervisor data access */ |
2218 | 81ad8ba2 | blueswir1 | switch(size) {
|
2219 | 81ad8ba2 | blueswir1 | case 1: |
2220 | 1a2fb1c0 | blueswir1 | stb_kernel(addr, val); |
2221 | 81ad8ba2 | blueswir1 | break;
|
2222 | 81ad8ba2 | blueswir1 | case 2: |
2223 | a4e7dd52 | blueswir1 | stw_kernel(addr, val); |
2224 | 81ad8ba2 | blueswir1 | break;
|
2225 | 81ad8ba2 | blueswir1 | default:
|
2226 | 81ad8ba2 | blueswir1 | case 4: |
2227 | a4e7dd52 | blueswir1 | stl_kernel(addr, val); |
2228 | 81ad8ba2 | blueswir1 | break;
|
2229 | 81ad8ba2 | blueswir1 | case 8: |
2230 | a4e7dd52 | blueswir1 | stq_kernel(addr, val); |
2231 | 81ad8ba2 | blueswir1 | break;
|
2232 | 81ad8ba2 | blueswir1 | } |
2233 | 81ad8ba2 | blueswir1 | break;
|
2234 | 6c36d3fa | blueswir1 | case 0xc: /* I-cache tag */ |
2235 | 6c36d3fa | blueswir1 | case 0xd: /* I-cache data */ |
2236 | 6c36d3fa | blueswir1 | case 0xe: /* D-cache tag */ |
2237 | 6c36d3fa | blueswir1 | case 0xf: /* D-cache data */ |
2238 | 6c36d3fa | blueswir1 | case 0x10: /* I/D-cache flush page */ |
2239 | 6c36d3fa | blueswir1 | case 0x11: /* I/D-cache flush segment */ |
2240 | 6c36d3fa | blueswir1 | case 0x12: /* I/D-cache flush region */ |
2241 | 6c36d3fa | blueswir1 | case 0x13: /* I/D-cache flush context */ |
2242 | 6c36d3fa | blueswir1 | case 0x14: /* I/D-cache flush user */ |
2243 | 6c36d3fa | blueswir1 | break;
|
2244 | e80cfcfc | bellard | case 0x17: /* Block copy, sta access */ |
2245 | 0f8a249a | blueswir1 | { |
2246 | 1a2fb1c0 | blueswir1 | // val = src
|
2247 | 1a2fb1c0 | blueswir1 | // addr = dst
|
2248 | 0f8a249a | blueswir1 | // copy 32 bytes
|
2249 | 6c36d3fa | blueswir1 | unsigned int i; |
2250 | 1a2fb1c0 | blueswir1 | uint32_t src = val & ~3, dst = addr & ~3, temp; |
2251 | 3b46e624 | ths | |
2252 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
2253 | 6c36d3fa | blueswir1 | temp = ldl_kernel(src); |
2254 | 6c36d3fa | blueswir1 | stl_kernel(dst, temp); |
2255 | 6c36d3fa | blueswir1 | } |
2256 | 0f8a249a | blueswir1 | } |
2257 | 8543e2cf | blueswir1 | break;
|
2258 | e80cfcfc | bellard | case 0x1f: /* Block fill, stda access */ |
2259 | 0f8a249a | blueswir1 | { |
2260 | 1a2fb1c0 | blueswir1 | // addr = dst
|
2261 | 1a2fb1c0 | blueswir1 | // fill 32 bytes with val
|
2262 | 6c36d3fa | blueswir1 | unsigned int i; |
2263 | 1a2fb1c0 | blueswir1 | uint32_t dst = addr & 7;
|
2264 | 6c36d3fa | blueswir1 | |
2265 | 6c36d3fa | blueswir1 | for (i = 0; i < 32; i += 8, dst += 8) |
2266 | 6c36d3fa | blueswir1 | stq_kernel(dst, val); |
2267 | 0f8a249a | blueswir1 | } |
2268 | 8543e2cf | blueswir1 | break;
|
2269 | 6c36d3fa | blueswir1 | case 0x20: /* MMU passthrough */ |
2270 | 0f8a249a | blueswir1 | { |
2271 | 02aab46a | bellard | switch(size) {
|
2272 | 02aab46a | bellard | case 1: |
2273 | 1a2fb1c0 | blueswir1 | stb_phys(addr, val); |
2274 | 02aab46a | bellard | break;
|
2275 | 02aab46a | bellard | case 2: |
2276 | a4e7dd52 | blueswir1 | stw_phys(addr, val); |
2277 | 02aab46a | bellard | break;
|
2278 | 02aab46a | bellard | case 4: |
2279 | 02aab46a | bellard | default:
|
2280 | a4e7dd52 | blueswir1 | stl_phys(addr, val); |
2281 | 02aab46a | bellard | break;
|
2282 | 9e61bde5 | bellard | case 8: |
2283 | a4e7dd52 | blueswir1 | stq_phys(addr, val); |
2284 | 9e61bde5 | bellard | break;
|
2285 | 02aab46a | bellard | } |
2286 | 0f8a249a | blueswir1 | } |
2287 | 8543e2cf | blueswir1 | break;
|
2288 | 045380be | blueswir1 | case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
2289 | 0f8a249a | blueswir1 | { |
2290 | 5dcb6b91 | blueswir1 | switch(size) {
|
2291 | 5dcb6b91 | blueswir1 | case 1: |
2292 | c227f099 | Anthony Liguori | stb_phys((target_phys_addr_t)addr |
2293 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2294 | 5dcb6b91 | blueswir1 | break;
|
2295 | 5dcb6b91 | blueswir1 | case 2: |
2296 | c227f099 | Anthony Liguori | stw_phys((target_phys_addr_t)addr |
2297 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2298 | 5dcb6b91 | blueswir1 | break;
|
2299 | 5dcb6b91 | blueswir1 | case 4: |
2300 | 5dcb6b91 | blueswir1 | default:
|
2301 | c227f099 | Anthony Liguori | stl_phys((target_phys_addr_t)addr |
2302 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2303 | 5dcb6b91 | blueswir1 | break;
|
2304 | 5dcb6b91 | blueswir1 | case 8: |
2305 | c227f099 | Anthony Liguori | stq_phys((target_phys_addr_t)addr |
2306 | c227f099 | Anthony Liguori | | ((target_phys_addr_t)(asi & 0xf) << 32), val); |
2307 | 5dcb6b91 | blueswir1 | break;
|
2308 | 5dcb6b91 | blueswir1 | } |
2309 | 0f8a249a | blueswir1 | } |
2310 | 8543e2cf | blueswir1 | break;
|
2311 | 045380be | blueswir1 | case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
2312 | 045380be | blueswir1 | case 0x31: // store buffer data, Ross RT620 I-cache flush or |
2313 | 045380be | blueswir1 | // Turbosparc snoop RAM
|
2314 | 77f193da | blueswir1 | case 0x32: // store buffer control or Turbosparc page table |
2315 | 77f193da | blueswir1 | // descriptor diagnostic
|
2316 | 6c36d3fa | blueswir1 | case 0x36: /* I-cache flash clear */ |
2317 | 6c36d3fa | blueswir1 | case 0x37: /* D-cache flash clear */ |
2318 | 6c36d3fa | blueswir1 | break;
|
2319 | 4017190e | blueswir1 | case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ |
2320 | 4017190e | blueswir1 | { |
2321 | 4017190e | blueswir1 | int reg = (addr >> 8) & 3; |
2322 | 4017190e | blueswir1 | |
2323 | 4017190e | blueswir1 | switch(reg) {
|
2324 | 4017190e | blueswir1 | case 0: /* Breakpoint Value (Addr) */ |
2325 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
2326 | 4017190e | blueswir1 | break;
|
2327 | 4017190e | blueswir1 | case 1: /* Breakpoint Mask */ |
2328 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0xfffffffffULL);
|
2329 | 4017190e | blueswir1 | break;
|
2330 | 4017190e | blueswir1 | case 2: /* Breakpoint Control */ |
2331 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0x7fULL);
|
2332 | 4017190e | blueswir1 | break;
|
2333 | 4017190e | blueswir1 | case 3: /* Breakpoint Status */ |
2334 | 4017190e | blueswir1 | env->mmubpregs[reg] = (val & 0xfULL);
|
2335 | 4017190e | blueswir1 | break;
|
2336 | 4017190e | blueswir1 | } |
2337 | 0bf9e31a | Blue Swirl | DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
|
2338 | 4017190e | blueswir1 | env->mmuregs[reg]); |
2339 | 4017190e | blueswir1 | } |
2340 | 4017190e | blueswir1 | break;
|
2341 | 4d2c2b77 | Blue Swirl | case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */ |
2342 | 4d2c2b77 | Blue Swirl | env->mmubpctrv = val & 0xffffffff;
|
2343 | 4d2c2b77 | Blue Swirl | break;
|
2344 | 4d2c2b77 | Blue Swirl | case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */ |
2345 | 4d2c2b77 | Blue Swirl | env->mmubpctrc = val & 0x3;
|
2346 | 4d2c2b77 | Blue Swirl | break;
|
2347 | 4d2c2b77 | Blue Swirl | case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */ |
2348 | 4d2c2b77 | Blue Swirl | env->mmubpctrs = val & 0x3;
|
2349 | 4d2c2b77 | Blue Swirl | break;
|
2350 | 4d2c2b77 | Blue Swirl | case 0x4c: /* SuperSPARC MMU Breakpoint Action */ |
2351 | 4d2c2b77 | Blue Swirl | env->mmubpaction = val & 0x1fff;
|
2352 | 4d2c2b77 | Blue Swirl | break;
|
2353 | 045380be | blueswir1 | case 8: /* User code access, XXX */ |
2354 | 6c36d3fa | blueswir1 | case 9: /* Supervisor code access, XXX */ |
2355 | e8af50a3 | bellard | default:
|
2356 | e18231a3 | blueswir1 | do_unassigned_access(addr, 1, 0, asi, size); |
2357 | 8543e2cf | blueswir1 | break;
|
2358 | e8af50a3 | bellard | } |
2359 | 8543e2cf | blueswir1 | #ifdef DEBUG_ASI
|
2360 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
2361 | 8543e2cf | blueswir1 | #endif
|
2362 | e8af50a3 | bellard | } |
2363 | e8af50a3 | bellard | |
2364 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
2365 | 81ad8ba2 | blueswir1 | #else /* TARGET_SPARC64 */ |
2366 | 81ad8ba2 | blueswir1 | |
2367 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
|
2368 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
2369 | 81ad8ba2 | blueswir1 | { |
2370 | 81ad8ba2 | blueswir1 | uint64_t ret = 0;
|
2371 | 1a2fb1c0 | blueswir1 | #if defined(DEBUG_ASI)
|
2372 | 1a2fb1c0 | blueswir1 | target_ulong last_addr = addr; |
2373 | 1a2fb1c0 | blueswir1 | #endif
|
2374 | 81ad8ba2 | blueswir1 | |
2375 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
2376 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
2377 | 81ad8ba2 | blueswir1 | |
2378 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2379 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2380 | c2bc0e38 | blueswir1 | |
2381 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2382 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault |
2383 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
2384 | e83ce550 | blueswir1 | if (page_check_range(addr, size, PAGE_READ) == -1) { |
2385 | e83ce550 | blueswir1 | #ifdef DEBUG_ASI
|
2386 | e83ce550 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2387 | e83ce550 | blueswir1 | #endif
|
2388 | e83ce550 | blueswir1 | return 0; |
2389 | e83ce550 | blueswir1 | } |
2390 | e83ce550 | blueswir1 | // Fall through
|
2391 | e83ce550 | blueswir1 | case 0x80: // Primary |
2392 | e83ce550 | blueswir1 | case 0x88: // Primary LE |
2393 | 81ad8ba2 | blueswir1 | { |
2394 | 81ad8ba2 | blueswir1 | switch(size) {
|
2395 | 81ad8ba2 | blueswir1 | case 1: |
2396 | 1a2fb1c0 | blueswir1 | ret = ldub_raw(addr); |
2397 | 81ad8ba2 | blueswir1 | break;
|
2398 | 81ad8ba2 | blueswir1 | case 2: |
2399 | a4e7dd52 | blueswir1 | ret = lduw_raw(addr); |
2400 | 81ad8ba2 | blueswir1 | break;
|
2401 | 81ad8ba2 | blueswir1 | case 4: |
2402 | a4e7dd52 | blueswir1 | ret = ldl_raw(addr); |
2403 | 81ad8ba2 | blueswir1 | break;
|
2404 | 81ad8ba2 | blueswir1 | default:
|
2405 | 81ad8ba2 | blueswir1 | case 8: |
2406 | a4e7dd52 | blueswir1 | ret = ldq_raw(addr); |
2407 | 81ad8ba2 | blueswir1 | break;
|
2408 | 81ad8ba2 | blueswir1 | } |
2409 | 81ad8ba2 | blueswir1 | } |
2410 | 81ad8ba2 | blueswir1 | break;
|
2411 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault |
2412 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
2413 | e83ce550 | blueswir1 | if (page_check_range(addr, size, PAGE_READ) == -1) { |
2414 | e83ce550 | blueswir1 | #ifdef DEBUG_ASI
|
2415 | e83ce550 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2416 | e83ce550 | blueswir1 | #endif
|
2417 | e83ce550 | blueswir1 | return 0; |
2418 | e83ce550 | blueswir1 | } |
2419 | e83ce550 | blueswir1 | // Fall through
|
2420 | e83ce550 | blueswir1 | case 0x81: // Secondary |
2421 | e83ce550 | blueswir1 | case 0x89: // Secondary LE |
2422 | 81ad8ba2 | blueswir1 | // XXX
|
2423 | 81ad8ba2 | blueswir1 | break;
|
2424 | 81ad8ba2 | blueswir1 | default:
|
2425 | 81ad8ba2 | blueswir1 | break;
|
2426 | 81ad8ba2 | blueswir1 | } |
2427 | 81ad8ba2 | blueswir1 | |
2428 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
2429 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2430 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2431 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2432 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
2433 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
2434 | 81ad8ba2 | blueswir1 | switch(size) {
|
2435 | 81ad8ba2 | blueswir1 | case 2: |
2436 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
2437 | e32664fb | blueswir1 | break;
|
2438 | 81ad8ba2 | blueswir1 | case 4: |
2439 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
2440 | e32664fb | blueswir1 | break;
|
2441 | 81ad8ba2 | blueswir1 | case 8: |
2442 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
2443 | e32664fb | blueswir1 | break;
|
2444 | 81ad8ba2 | blueswir1 | default:
|
2445 | 81ad8ba2 | blueswir1 | break;
|
2446 | 81ad8ba2 | blueswir1 | } |
2447 | 81ad8ba2 | blueswir1 | default:
|
2448 | 81ad8ba2 | blueswir1 | break;
|
2449 | 81ad8ba2 | blueswir1 | } |
2450 | 81ad8ba2 | blueswir1 | |
2451 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
2452 | 81ad8ba2 | blueswir1 | if (sign) {
|
2453 | 81ad8ba2 | blueswir1 | switch(size) {
|
2454 | 81ad8ba2 | blueswir1 | case 1: |
2455 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
2456 | e32664fb | blueswir1 | break;
|
2457 | 81ad8ba2 | blueswir1 | case 2: |
2458 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
2459 | e32664fb | blueswir1 | break;
|
2460 | 81ad8ba2 | blueswir1 | case 4: |
2461 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
2462 | e32664fb | blueswir1 | break;
|
2463 | 81ad8ba2 | blueswir1 | default:
|
2464 | 81ad8ba2 | blueswir1 | break;
|
2465 | 81ad8ba2 | blueswir1 | } |
2466 | 81ad8ba2 | blueswir1 | } |
2467 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2468 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2469 | 1a2fb1c0 | blueswir1 | #endif
|
2470 | 1a2fb1c0 | blueswir1 | return ret;
|
2471 | 81ad8ba2 | blueswir1 | } |
2472 | 81ad8ba2 | blueswir1 | |
2473 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
2474 | 81ad8ba2 | blueswir1 | { |
2475 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2476 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
2477 | 1a2fb1c0 | blueswir1 | #endif
|
2478 | 81ad8ba2 | blueswir1 | if (asi < 0x80) |
2479 | 81ad8ba2 | blueswir1 | raise_exception(TT_PRIV_ACT); |
2480 | 81ad8ba2 | blueswir1 | |
2481 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2482 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2483 | c2bc0e38 | blueswir1 | |
2484 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
2485 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2486 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2487 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2488 | 81ad8ba2 | blueswir1 | switch(size) {
|
2489 | 81ad8ba2 | blueswir1 | case 2: |
2490 | 5b0f0bec | Igor Kovalenko | val = bswap16(val); |
2491 | e32664fb | blueswir1 | break;
|
2492 | 81ad8ba2 | blueswir1 | case 4: |
2493 | 5b0f0bec | Igor Kovalenko | val = bswap32(val); |
2494 | e32664fb | blueswir1 | break;
|
2495 | 81ad8ba2 | blueswir1 | case 8: |
2496 | 5b0f0bec | Igor Kovalenko | val = bswap64(val); |
2497 | e32664fb | blueswir1 | break;
|
2498 | 81ad8ba2 | blueswir1 | default:
|
2499 | 81ad8ba2 | blueswir1 | break;
|
2500 | 81ad8ba2 | blueswir1 | } |
2501 | 81ad8ba2 | blueswir1 | default:
|
2502 | 81ad8ba2 | blueswir1 | break;
|
2503 | 81ad8ba2 | blueswir1 | } |
2504 | 81ad8ba2 | blueswir1 | |
2505 | 81ad8ba2 | blueswir1 | switch(asi) {
|
2506 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
2507 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2508 | 81ad8ba2 | blueswir1 | { |
2509 | 81ad8ba2 | blueswir1 | switch(size) {
|
2510 | 81ad8ba2 | blueswir1 | case 1: |
2511 | 1a2fb1c0 | blueswir1 | stb_raw(addr, val); |
2512 | 81ad8ba2 | blueswir1 | break;
|
2513 | 81ad8ba2 | blueswir1 | case 2: |
2514 | a4e7dd52 | blueswir1 | stw_raw(addr, val); |
2515 | 81ad8ba2 | blueswir1 | break;
|
2516 | 81ad8ba2 | blueswir1 | case 4: |
2517 | a4e7dd52 | blueswir1 | stl_raw(addr, val); |
2518 | 81ad8ba2 | blueswir1 | break;
|
2519 | 81ad8ba2 | blueswir1 | case 8: |
2520 | 81ad8ba2 | blueswir1 | default:
|
2521 | a4e7dd52 | blueswir1 | stq_raw(addr, val); |
2522 | 81ad8ba2 | blueswir1 | break;
|
2523 | 81ad8ba2 | blueswir1 | } |
2524 | 81ad8ba2 | blueswir1 | } |
2525 | 81ad8ba2 | blueswir1 | break;
|
2526 | 81ad8ba2 | blueswir1 | case 0x81: // Secondary |
2527 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2528 | 81ad8ba2 | blueswir1 | // XXX
|
2529 | 81ad8ba2 | blueswir1 | return;
|
2530 | 81ad8ba2 | blueswir1 | |
2531 | 81ad8ba2 | blueswir1 | case 0x82: // Primary no-fault, RO |
2532 | 81ad8ba2 | blueswir1 | case 0x83: // Secondary no-fault, RO |
2533 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE, RO |
2534 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE, RO |
2535 | 81ad8ba2 | blueswir1 | default:
|
2536 | e18231a3 | blueswir1 | do_unassigned_access(addr, 1, 0, 1, size); |
2537 | 81ad8ba2 | blueswir1 | return;
|
2538 | 81ad8ba2 | blueswir1 | } |
2539 | 81ad8ba2 | blueswir1 | } |
2540 | 81ad8ba2 | blueswir1 | |
2541 | 81ad8ba2 | blueswir1 | #else /* CONFIG_USER_ONLY */ |
2542 | 3475187d | bellard | |
2543 | 1a2fb1c0 | blueswir1 | uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
2544 | 3475187d | bellard | { |
2545 | 83469015 | bellard | uint64_t ret = 0;
|
2546 | 1a2fb1c0 | blueswir1 | #if defined(DEBUG_ASI)
|
2547 | 1a2fb1c0 | blueswir1 | target_ulong last_addr = addr; |
2548 | 1a2fb1c0 | blueswir1 | #endif
|
2549 | 3475187d | bellard | |
2550 | 01b5d4e5 | Igor V. Kovalenko | asi &= 0xff;
|
2551 | 01b5d4e5 | Igor V. Kovalenko | |
2552 | 6f27aba6 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2553 | 2aae2b8e | Igor V. Kovalenko | || (cpu_has_hypervisor(env) |
2554 | 5578ceab | blueswir1 | && asi >= 0x30 && asi < 0x80 |
2555 | fb79ceb9 | blueswir1 | && !(env->hpstate & HS_PRIV))) |
2556 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
2557 | 3475187d | bellard | |
2558 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2559 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2560 | 1295001c | Igor V. Kovalenko | |
2561 | 3475187d | bellard | switch (asi) {
|
2562 | e83ce550 | blueswir1 | case 0x82: // Primary no-fault |
2563 | e83ce550 | blueswir1 | case 0x8a: // Primary no-fault LE |
2564 | 2065061e | Igor V. Kovalenko | case 0x83: // Secondary no-fault |
2565 | 2065061e | Igor V. Kovalenko | case 0x8b: // Secondary no-fault LE |
2566 | 2065061e | Igor V. Kovalenko | { |
2567 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2568 | 2065061e | Igor V. Kovalenko | int access_mmu_idx = ( asi & 1 ) ? MMU_KERNEL_IDX |
2569 | 2065061e | Igor V. Kovalenko | : MMU_KERNEL_SECONDARY_IDX; |
2570 | 2065061e | Igor V. Kovalenko | |
2571 | 2065061e | Igor V. Kovalenko | if (cpu_get_phys_page_nofault(env, addr, access_mmu_idx) == -1ULL) { |
2572 | e83ce550 | blueswir1 | #ifdef DEBUG_ASI
|
2573 | 2065061e | Igor V. Kovalenko | dump_asi("read ", last_addr, asi, size, ret);
|
2574 | e83ce550 | blueswir1 | #endif
|
2575 | 2065061e | Igor V. Kovalenko | return 0; |
2576 | 2065061e | Igor V. Kovalenko | } |
2577 | e83ce550 | blueswir1 | } |
2578 | e83ce550 | blueswir1 | // Fall through
|
2579 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
2580 | 2065061e | Igor V. Kovalenko | case 0x11: // As if user secondary |
2581 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2582 | 2065061e | Igor V. Kovalenko | case 0x19: // As if user secondary LE |
2583 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
2584 | 2065061e | Igor V. Kovalenko | case 0x81: // Secondary |
2585 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2586 | 2065061e | Igor V. Kovalenko | case 0x89: // Secondary LE |
2587 | c99657d3 | blueswir1 | case 0xe2: // UA2007 Primary block init |
2588 | c99657d3 | blueswir1 | case 0xe3: // UA2007 Secondary block init |
2589 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2590 | 2aae2b8e | Igor V. Kovalenko | if (cpu_hypervisor_mode(env)) {
|
2591 | 6f27aba6 | blueswir1 | switch(size) {
|
2592 | 6f27aba6 | blueswir1 | case 1: |
2593 | 1a2fb1c0 | blueswir1 | ret = ldub_hypv(addr); |
2594 | 6f27aba6 | blueswir1 | break;
|
2595 | 6f27aba6 | blueswir1 | case 2: |
2596 | a4e7dd52 | blueswir1 | ret = lduw_hypv(addr); |
2597 | 6f27aba6 | blueswir1 | break;
|
2598 | 6f27aba6 | blueswir1 | case 4: |
2599 | a4e7dd52 | blueswir1 | ret = ldl_hypv(addr); |
2600 | 6f27aba6 | blueswir1 | break;
|
2601 | 6f27aba6 | blueswir1 | default:
|
2602 | 6f27aba6 | blueswir1 | case 8: |
2603 | a4e7dd52 | blueswir1 | ret = ldq_hypv(addr); |
2604 | 6f27aba6 | blueswir1 | break;
|
2605 | 6f27aba6 | blueswir1 | } |
2606 | 6f27aba6 | blueswir1 | } else {
|
2607 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2608 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2609 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2610 | 2065061e | Igor V. Kovalenko | case 1: |
2611 | 2065061e | Igor V. Kovalenko | ret = ldub_kernel_secondary(addr); |
2612 | 2065061e | Igor V. Kovalenko | break;
|
2613 | 2065061e | Igor V. Kovalenko | case 2: |
2614 | 2065061e | Igor V. Kovalenko | ret = lduw_kernel_secondary(addr); |
2615 | 2065061e | Igor V. Kovalenko | break;
|
2616 | 2065061e | Igor V. Kovalenko | case 4: |
2617 | 2065061e | Igor V. Kovalenko | ret = ldl_kernel_secondary(addr); |
2618 | 2065061e | Igor V. Kovalenko | break;
|
2619 | 2065061e | Igor V. Kovalenko | default:
|
2620 | 2065061e | Igor V. Kovalenko | case 8: |
2621 | 2065061e | Igor V. Kovalenko | ret = ldq_kernel_secondary(addr); |
2622 | 2065061e | Igor V. Kovalenko | break;
|
2623 | 2065061e | Igor V. Kovalenko | } |
2624 | 2065061e | Igor V. Kovalenko | } else {
|
2625 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2626 | 2065061e | Igor V. Kovalenko | case 1: |
2627 | 2065061e | Igor V. Kovalenko | ret = ldub_kernel(addr); |
2628 | 2065061e | Igor V. Kovalenko | break;
|
2629 | 2065061e | Igor V. Kovalenko | case 2: |
2630 | 2065061e | Igor V. Kovalenko | ret = lduw_kernel(addr); |
2631 | 2065061e | Igor V. Kovalenko | break;
|
2632 | 2065061e | Igor V. Kovalenko | case 4: |
2633 | 2065061e | Igor V. Kovalenko | ret = ldl_kernel(addr); |
2634 | 2065061e | Igor V. Kovalenko | break;
|
2635 | 2065061e | Igor V. Kovalenko | default:
|
2636 | 2065061e | Igor V. Kovalenko | case 8: |
2637 | 2065061e | Igor V. Kovalenko | ret = ldq_kernel(addr); |
2638 | 2065061e | Igor V. Kovalenko | break;
|
2639 | 2065061e | Igor V. Kovalenko | } |
2640 | 2065061e | Igor V. Kovalenko | } |
2641 | 2065061e | Igor V. Kovalenko | } |
2642 | 2065061e | Igor V. Kovalenko | } else {
|
2643 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2644 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2645 | 6f27aba6 | blueswir1 | switch(size) {
|
2646 | 6f27aba6 | blueswir1 | case 1: |
2647 | 2065061e | Igor V. Kovalenko | ret = ldub_user_secondary(addr); |
2648 | 6f27aba6 | blueswir1 | break;
|
2649 | 6f27aba6 | blueswir1 | case 2: |
2650 | 2065061e | Igor V. Kovalenko | ret = lduw_user_secondary(addr); |
2651 | 6f27aba6 | blueswir1 | break;
|
2652 | 6f27aba6 | blueswir1 | case 4: |
2653 | 2065061e | Igor V. Kovalenko | ret = ldl_user_secondary(addr); |
2654 | 6f27aba6 | blueswir1 | break;
|
2655 | 6f27aba6 | blueswir1 | default:
|
2656 | 6f27aba6 | blueswir1 | case 8: |
2657 | 2065061e | Igor V. Kovalenko | ret = ldq_user_secondary(addr); |
2658 | 2065061e | Igor V. Kovalenko | break;
|
2659 | 2065061e | Igor V. Kovalenko | } |
2660 | 2065061e | Igor V. Kovalenko | } else {
|
2661 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2662 | 2065061e | Igor V. Kovalenko | case 1: |
2663 | 2065061e | Igor V. Kovalenko | ret = ldub_user(addr); |
2664 | 2065061e | Igor V. Kovalenko | break;
|
2665 | 2065061e | Igor V. Kovalenko | case 2: |
2666 | 2065061e | Igor V. Kovalenko | ret = lduw_user(addr); |
2667 | 2065061e | Igor V. Kovalenko | break;
|
2668 | 2065061e | Igor V. Kovalenko | case 4: |
2669 | 2065061e | Igor V. Kovalenko | ret = ldl_user(addr); |
2670 | 2065061e | Igor V. Kovalenko | break;
|
2671 | 2065061e | Igor V. Kovalenko | default:
|
2672 | 2065061e | Igor V. Kovalenko | case 8: |
2673 | 2065061e | Igor V. Kovalenko | ret = ldq_user(addr); |
2674 | 6f27aba6 | blueswir1 | break;
|
2675 | 6f27aba6 | blueswir1 | } |
2676 | 81ad8ba2 | blueswir1 | } |
2677 | 81ad8ba2 | blueswir1 | } |
2678 | 81ad8ba2 | blueswir1 | break;
|
2679 | 3475187d | bellard | case 0x14: // Bypass |
2680 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
2681 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2682 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2683 | 0f8a249a | blueswir1 | { |
2684 | 02aab46a | bellard | switch(size) {
|
2685 | 02aab46a | bellard | case 1: |
2686 | 1a2fb1c0 | blueswir1 | ret = ldub_phys(addr); |
2687 | 02aab46a | bellard | break;
|
2688 | 02aab46a | bellard | case 2: |
2689 | a4e7dd52 | blueswir1 | ret = lduw_phys(addr); |
2690 | 02aab46a | bellard | break;
|
2691 | 02aab46a | bellard | case 4: |
2692 | a4e7dd52 | blueswir1 | ret = ldl_phys(addr); |
2693 | 02aab46a | bellard | break;
|
2694 | 02aab46a | bellard | default:
|
2695 | 02aab46a | bellard | case 8: |
2696 | a4e7dd52 | blueswir1 | ret = ldq_phys(addr); |
2697 | 02aab46a | bellard | break;
|
2698 | 02aab46a | bellard | } |
2699 | 0f8a249a | blueswir1 | break;
|
2700 | 0f8a249a | blueswir1 | } |
2701 | db166940 | blueswir1 | case 0x24: // Nucleus quad LDD 128 bit atomic |
2702 | db166940 | blueswir1 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
2703 | db166940 | blueswir1 | // Only ldda allowed
|
2704 | db166940 | blueswir1 | raise_exception(TT_ILL_INSN); |
2705 | db166940 | blueswir1 | return 0; |
2706 | 83469015 | bellard | case 0x04: // Nucleus |
2707 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
2708 | 2065061e | Igor V. Kovalenko | { |
2709 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2710 | 2065061e | Igor V. Kovalenko | case 1: |
2711 | 2065061e | Igor V. Kovalenko | ret = ldub_nucleus(addr); |
2712 | 2065061e | Igor V. Kovalenko | break;
|
2713 | 2065061e | Igor V. Kovalenko | case 2: |
2714 | 2065061e | Igor V. Kovalenko | ret = lduw_nucleus(addr); |
2715 | 2065061e | Igor V. Kovalenko | break;
|
2716 | 2065061e | Igor V. Kovalenko | case 4: |
2717 | 2065061e | Igor V. Kovalenko | ret = ldl_nucleus(addr); |
2718 | 2065061e | Igor V. Kovalenko | break;
|
2719 | 2065061e | Igor V. Kovalenko | default:
|
2720 | 2065061e | Igor V. Kovalenko | case 8: |
2721 | 2065061e | Igor V. Kovalenko | ret = ldq_nucleus(addr); |
2722 | 2065061e | Igor V. Kovalenko | break;
|
2723 | 2065061e | Igor V. Kovalenko | } |
2724 | 2065061e | Igor V. Kovalenko | break;
|
2725 | 2065061e | Igor V. Kovalenko | } |
2726 | 83469015 | bellard | case 0x4a: // UPA config |
2727 | 0f8a249a | blueswir1 | // XXX
|
2728 | 0f8a249a | blueswir1 | break;
|
2729 | 3475187d | bellard | case 0x45: // LSU |
2730 | 0f8a249a | blueswir1 | ret = env->lsu; |
2731 | 0f8a249a | blueswir1 | break;
|
2732 | 3475187d | bellard | case 0x50: // I-MMU regs |
2733 | 0f8a249a | blueswir1 | { |
2734 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
2735 | 3475187d | bellard | |
2736 | 697a77e6 | Igor Kovalenko | if (reg == 0) { |
2737 | 697a77e6 | Igor Kovalenko | // I-TSB Tag Target register
|
2738 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tag_target(env->immu.tag_access); |
2739 | 697a77e6 | Igor Kovalenko | } else {
|
2740 | 697a77e6 | Igor Kovalenko | ret = env->immuregs[reg]; |
2741 | 697a77e6 | Igor Kovalenko | } |
2742 | 697a77e6 | Igor Kovalenko | |
2743 | 0f8a249a | blueswir1 | break;
|
2744 | 0f8a249a | blueswir1 | } |
2745 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer |
2746 | 697a77e6 | Igor Kovalenko | { |
2747 | 697a77e6 | Igor Kovalenko | // env->immuregs[5] holds I-MMU TSB register value
|
2748 | 697a77e6 | Igor Kovalenko | // env->immuregs[6] holds I-MMU Tag Access register value
|
2749 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
2750 | 697a77e6 | Igor Kovalenko | 8*1024); |
2751 | 697a77e6 | Igor Kovalenko | break;
|
2752 | 697a77e6 | Igor Kovalenko | } |
2753 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer |
2754 | 697a77e6 | Igor Kovalenko | { |
2755 | 697a77e6 | Igor Kovalenko | // env->immuregs[5] holds I-MMU TSB register value
|
2756 | 697a77e6 | Igor Kovalenko | // env->immuregs[6] holds I-MMU Tag Access register value
|
2757 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access, |
2758 | 697a77e6 | Igor Kovalenko | 64*1024); |
2759 | 697a77e6 | Igor Kovalenko | break;
|
2760 | 697a77e6 | Igor Kovalenko | } |
2761 | a5a52cf2 | blueswir1 | case 0x55: // I-MMU data access |
2762 | a5a52cf2 | blueswir1 | { |
2763 | a5a52cf2 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2764 | a5a52cf2 | blueswir1 | |
2765 | 6e8e7d4c | Igor Kovalenko | ret = env->itlb[reg].tte; |
2766 | a5a52cf2 | blueswir1 | break;
|
2767 | a5a52cf2 | blueswir1 | } |
2768 | 83469015 | bellard | case 0x56: // I-MMU tag read |
2769 | 0f8a249a | blueswir1 | { |
2770 | 43e9e742 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2771 | 0f8a249a | blueswir1 | |
2772 | 6e8e7d4c | Igor Kovalenko | ret = env->itlb[reg].tag; |
2773 | 0f8a249a | blueswir1 | break;
|
2774 | 0f8a249a | blueswir1 | } |
2775 | 3475187d | bellard | case 0x58: // D-MMU regs |
2776 | 0f8a249a | blueswir1 | { |
2777 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
2778 | 3475187d | bellard | |
2779 | 697a77e6 | Igor Kovalenko | if (reg == 0) { |
2780 | 697a77e6 | Igor Kovalenko | // D-TSB Tag Target register
|
2781 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tag_target(env->dmmu.tag_access); |
2782 | 697a77e6 | Igor Kovalenko | } else {
|
2783 | 697a77e6 | Igor Kovalenko | ret = env->dmmuregs[reg]; |
2784 | 697a77e6 | Igor Kovalenko | } |
2785 | 697a77e6 | Igor Kovalenko | break;
|
2786 | 697a77e6 | Igor Kovalenko | } |
2787 | 697a77e6 | Igor Kovalenko | case 0x59: // D-MMU 8k TSB pointer |
2788 | 697a77e6 | Igor Kovalenko | { |
2789 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[5] holds D-MMU TSB register value
|
2790 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[6] holds D-MMU Tag Access register value
|
2791 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
2792 | 697a77e6 | Igor Kovalenko | 8*1024); |
2793 | 697a77e6 | Igor Kovalenko | break;
|
2794 | 697a77e6 | Igor Kovalenko | } |
2795 | 697a77e6 | Igor Kovalenko | case 0x5a: // D-MMU 64k TSB pointer |
2796 | 697a77e6 | Igor Kovalenko | { |
2797 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[5] holds D-MMU TSB register value
|
2798 | 697a77e6 | Igor Kovalenko | // env->dmmuregs[6] holds D-MMU Tag Access register value
|
2799 | 6e8e7d4c | Igor Kovalenko | ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access, |
2800 | 697a77e6 | Igor Kovalenko | 64*1024); |
2801 | 0f8a249a | blueswir1 | break;
|
2802 | 0f8a249a | blueswir1 | } |
2803 | a5a52cf2 | blueswir1 | case 0x5d: // D-MMU data access |
2804 | a5a52cf2 | blueswir1 | { |
2805 | a5a52cf2 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2806 | a5a52cf2 | blueswir1 | |
2807 | 6e8e7d4c | Igor Kovalenko | ret = env->dtlb[reg].tte; |
2808 | a5a52cf2 | blueswir1 | break;
|
2809 | a5a52cf2 | blueswir1 | } |
2810 | 83469015 | bellard | case 0x5e: // D-MMU tag read |
2811 | 0f8a249a | blueswir1 | { |
2812 | 43e9e742 | blueswir1 | int reg = (addr >> 3) & 0x3f; |
2813 | 0f8a249a | blueswir1 | |
2814 | 6e8e7d4c | Igor Kovalenko | ret = env->dtlb[reg].tag; |
2815 | 0f8a249a | blueswir1 | break;
|
2816 | 0f8a249a | blueswir1 | } |
2817 | f7350b47 | blueswir1 | case 0x46: // D-cache data |
2818 | f7350b47 | blueswir1 | case 0x47: // D-cache tag access |
2819 | a5a52cf2 | blueswir1 | case 0x4b: // E-cache error enable |
2820 | a5a52cf2 | blueswir1 | case 0x4c: // E-cache asynchronous fault status |
2821 | a5a52cf2 | blueswir1 | case 0x4d: // E-cache asynchronous fault address |
2822 | f7350b47 | blueswir1 | case 0x4e: // E-cache tag data |
2823 | f7350b47 | blueswir1 | case 0x66: // I-cache instruction access |
2824 | f7350b47 | blueswir1 | case 0x67: // I-cache tag access |
2825 | f7350b47 | blueswir1 | case 0x6e: // I-cache predecode |
2826 | f7350b47 | blueswir1 | case 0x6f: // I-cache LRU etc. |
2827 | f7350b47 | blueswir1 | case 0x76: // E-cache tag |
2828 | f7350b47 | blueswir1 | case 0x7e: // E-cache tag |
2829 | f7350b47 | blueswir1 | break;
|
2830 | 3475187d | bellard | case 0x5b: // D-MMU data pointer |
2831 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
2832 | 83469015 | bellard | case 0x49: // Interrupt data receive |
2833 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
2834 | 0f8a249a | blueswir1 | // XXX
|
2835 | 0f8a249a | blueswir1 | break;
|
2836 | 3475187d | bellard | case 0x54: // I-MMU data in, WO |
2837 | 3475187d | bellard | case 0x57: // I-MMU demap, WO |
2838 | 3475187d | bellard | case 0x5c: // D-MMU data in, WO |
2839 | 3475187d | bellard | case 0x5f: // D-MMU demap, WO |
2840 | 83469015 | bellard | case 0x77: // Interrupt vector, WO |
2841 | 3475187d | bellard | default:
|
2842 | e18231a3 | blueswir1 | do_unassigned_access(addr, 0, 0, 1, size); |
2843 | 0f8a249a | blueswir1 | ret = 0;
|
2844 | 0f8a249a | blueswir1 | break;
|
2845 | 3475187d | bellard | } |
2846 | 81ad8ba2 | blueswir1 | |
2847 | 81ad8ba2 | blueswir1 | /* Convert from little endian */
|
2848 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2849 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
2850 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2851 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
2852 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2853 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2854 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2855 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2856 | 81ad8ba2 | blueswir1 | case 0x8a: // Primary no-fault LE |
2857 | 81ad8ba2 | blueswir1 | case 0x8b: // Secondary no-fault LE |
2858 | 81ad8ba2 | blueswir1 | switch(size) {
|
2859 | 81ad8ba2 | blueswir1 | case 2: |
2860 | 81ad8ba2 | blueswir1 | ret = bswap16(ret); |
2861 | e32664fb | blueswir1 | break;
|
2862 | 81ad8ba2 | blueswir1 | case 4: |
2863 | 81ad8ba2 | blueswir1 | ret = bswap32(ret); |
2864 | e32664fb | blueswir1 | break;
|
2865 | 81ad8ba2 | blueswir1 | case 8: |
2866 | 81ad8ba2 | blueswir1 | ret = bswap64(ret); |
2867 | e32664fb | blueswir1 | break;
|
2868 | 81ad8ba2 | blueswir1 | default:
|
2869 | 81ad8ba2 | blueswir1 | break;
|
2870 | 81ad8ba2 | blueswir1 | } |
2871 | 81ad8ba2 | blueswir1 | default:
|
2872 | 81ad8ba2 | blueswir1 | break;
|
2873 | 81ad8ba2 | blueswir1 | } |
2874 | 81ad8ba2 | blueswir1 | |
2875 | 81ad8ba2 | blueswir1 | /* Convert to signed number */
|
2876 | 81ad8ba2 | blueswir1 | if (sign) {
|
2877 | 81ad8ba2 | blueswir1 | switch(size) {
|
2878 | 81ad8ba2 | blueswir1 | case 1: |
2879 | 81ad8ba2 | blueswir1 | ret = (int8_t) ret; |
2880 | e32664fb | blueswir1 | break;
|
2881 | 81ad8ba2 | blueswir1 | case 2: |
2882 | 81ad8ba2 | blueswir1 | ret = (int16_t) ret; |
2883 | e32664fb | blueswir1 | break;
|
2884 | 81ad8ba2 | blueswir1 | case 4: |
2885 | 81ad8ba2 | blueswir1 | ret = (int32_t) ret; |
2886 | e32664fb | blueswir1 | break;
|
2887 | 81ad8ba2 | blueswir1 | default:
|
2888 | 81ad8ba2 | blueswir1 | break;
|
2889 | 81ad8ba2 | blueswir1 | } |
2890 | 81ad8ba2 | blueswir1 | } |
2891 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2892 | 1a2fb1c0 | blueswir1 | dump_asi("read ", last_addr, asi, size, ret);
|
2893 | 1a2fb1c0 | blueswir1 | #endif
|
2894 | 1a2fb1c0 | blueswir1 | return ret;
|
2895 | 3475187d | bellard | } |
2896 | 3475187d | bellard | |
2897 | 1a2fb1c0 | blueswir1 | void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
2898 | 3475187d | bellard | { |
2899 | 1a2fb1c0 | blueswir1 | #ifdef DEBUG_ASI
|
2900 | 1a2fb1c0 | blueswir1 | dump_asi("write", addr, asi, size, val);
|
2901 | 1a2fb1c0 | blueswir1 | #endif
|
2902 | 01b5d4e5 | Igor V. Kovalenko | |
2903 | 01b5d4e5 | Igor V. Kovalenko | asi &= 0xff;
|
2904 | 01b5d4e5 | Igor V. Kovalenko | |
2905 | 6f27aba6 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
2906 | 2aae2b8e | Igor V. Kovalenko | || (cpu_has_hypervisor(env) |
2907 | 5578ceab | blueswir1 | && asi >= 0x30 && asi < 0x80 |
2908 | fb79ceb9 | blueswir1 | && !(env->hpstate & HS_PRIV))) |
2909 | 0f8a249a | blueswir1 | raise_exception(TT_PRIV_ACT); |
2910 | 3475187d | bellard | |
2911 | c2bc0e38 | blueswir1 | helper_check_align(addr, size - 1);
|
2912 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
2913 | 1295001c | Igor V. Kovalenko | |
2914 | 81ad8ba2 | blueswir1 | /* Convert to little endian */
|
2915 | 81ad8ba2 | blueswir1 | switch (asi) {
|
2916 | 81ad8ba2 | blueswir1 | case 0x0c: // Nucleus Little Endian (LE) |
2917 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2918 | 81ad8ba2 | blueswir1 | case 0x19: // As if user secondary LE |
2919 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
2920 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
2921 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2922 | 81ad8ba2 | blueswir1 | case 0x89: // Secondary LE |
2923 | 81ad8ba2 | blueswir1 | switch(size) {
|
2924 | 81ad8ba2 | blueswir1 | case 2: |
2925 | 5b0f0bec | Igor Kovalenko | val = bswap16(val); |
2926 | e32664fb | blueswir1 | break;
|
2927 | 81ad8ba2 | blueswir1 | case 4: |
2928 | 5b0f0bec | Igor Kovalenko | val = bswap32(val); |
2929 | e32664fb | blueswir1 | break;
|
2930 | 81ad8ba2 | blueswir1 | case 8: |
2931 | 5b0f0bec | Igor Kovalenko | val = bswap64(val); |
2932 | e32664fb | blueswir1 | break;
|
2933 | 81ad8ba2 | blueswir1 | default:
|
2934 | 81ad8ba2 | blueswir1 | break;
|
2935 | 81ad8ba2 | blueswir1 | } |
2936 | 81ad8ba2 | blueswir1 | default:
|
2937 | 81ad8ba2 | blueswir1 | break;
|
2938 | 81ad8ba2 | blueswir1 | } |
2939 | 81ad8ba2 | blueswir1 | |
2940 | 3475187d | bellard | switch(asi) {
|
2941 | 81ad8ba2 | blueswir1 | case 0x10: // As if user primary |
2942 | 2065061e | Igor V. Kovalenko | case 0x11: // As if user secondary |
2943 | 81ad8ba2 | blueswir1 | case 0x18: // As if user primary LE |
2944 | 2065061e | Igor V. Kovalenko | case 0x19: // As if user secondary LE |
2945 | 81ad8ba2 | blueswir1 | case 0x80: // Primary |
2946 | 2065061e | Igor V. Kovalenko | case 0x81: // Secondary |
2947 | 81ad8ba2 | blueswir1 | case 0x88: // Primary LE |
2948 | 2065061e | Igor V. Kovalenko | case 0x89: // Secondary LE |
2949 | c99657d3 | blueswir1 | case 0xe2: // UA2007 Primary block init |
2950 | c99657d3 | blueswir1 | case 0xe3: // UA2007 Secondary block init |
2951 | 81ad8ba2 | blueswir1 | if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
2952 | 2aae2b8e | Igor V. Kovalenko | if (cpu_hypervisor_mode(env)) {
|
2953 | 6f27aba6 | blueswir1 | switch(size) {
|
2954 | 6f27aba6 | blueswir1 | case 1: |
2955 | 1a2fb1c0 | blueswir1 | stb_hypv(addr, val); |
2956 | 6f27aba6 | blueswir1 | break;
|
2957 | 6f27aba6 | blueswir1 | case 2: |
2958 | a4e7dd52 | blueswir1 | stw_hypv(addr, val); |
2959 | 6f27aba6 | blueswir1 | break;
|
2960 | 6f27aba6 | blueswir1 | case 4: |
2961 | a4e7dd52 | blueswir1 | stl_hypv(addr, val); |
2962 | 6f27aba6 | blueswir1 | break;
|
2963 | 6f27aba6 | blueswir1 | case 8: |
2964 | 6f27aba6 | blueswir1 | default:
|
2965 | a4e7dd52 | blueswir1 | stq_hypv(addr, val); |
2966 | 6f27aba6 | blueswir1 | break;
|
2967 | 6f27aba6 | blueswir1 | } |
2968 | 6f27aba6 | blueswir1 | } else {
|
2969 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
2970 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
2971 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2972 | 2065061e | Igor V. Kovalenko | case 1: |
2973 | 2065061e | Igor V. Kovalenko | stb_kernel_secondary(addr, val); |
2974 | 2065061e | Igor V. Kovalenko | break;
|
2975 | 2065061e | Igor V. Kovalenko | case 2: |
2976 | 2065061e | Igor V. Kovalenko | stw_kernel_secondary(addr, val); |
2977 | 2065061e | Igor V. Kovalenko | break;
|
2978 | 2065061e | Igor V. Kovalenko | case 4: |
2979 | 2065061e | Igor V. Kovalenko | stl_kernel_secondary(addr, val); |
2980 | 2065061e | Igor V. Kovalenko | break;
|
2981 | 2065061e | Igor V. Kovalenko | case 8: |
2982 | 2065061e | Igor V. Kovalenko | default:
|
2983 | 2065061e | Igor V. Kovalenko | stq_kernel_secondary(addr, val); |
2984 | 2065061e | Igor V. Kovalenko | break;
|
2985 | 2065061e | Igor V. Kovalenko | } |
2986 | 2065061e | Igor V. Kovalenko | } else {
|
2987 | 2065061e | Igor V. Kovalenko | switch(size) {
|
2988 | 2065061e | Igor V. Kovalenko | case 1: |
2989 | 2065061e | Igor V. Kovalenko | stb_kernel(addr, val); |
2990 | 2065061e | Igor V. Kovalenko | break;
|
2991 | 2065061e | Igor V. Kovalenko | case 2: |
2992 | 2065061e | Igor V. Kovalenko | stw_kernel(addr, val); |
2993 | 2065061e | Igor V. Kovalenko | break;
|
2994 | 2065061e | Igor V. Kovalenko | case 4: |
2995 | 2065061e | Igor V. Kovalenko | stl_kernel(addr, val); |
2996 | 2065061e | Igor V. Kovalenko | break;
|
2997 | 2065061e | Igor V. Kovalenko | case 8: |
2998 | 2065061e | Igor V. Kovalenko | default:
|
2999 | 2065061e | Igor V. Kovalenko | stq_kernel(addr, val); |
3000 | 2065061e | Igor V. Kovalenko | break;
|
3001 | 2065061e | Igor V. Kovalenko | } |
3002 | 2065061e | Igor V. Kovalenko | } |
3003 | 2065061e | Igor V. Kovalenko | } |
3004 | 2065061e | Igor V. Kovalenko | } else {
|
3005 | 2065061e | Igor V. Kovalenko | /* secondary space access has lowest asi bit equal to 1 */
|
3006 | 2065061e | Igor V. Kovalenko | if (asi & 1) { |
3007 | 6f27aba6 | blueswir1 | switch(size) {
|
3008 | 6f27aba6 | blueswir1 | case 1: |
3009 | 2065061e | Igor V. Kovalenko | stb_user_secondary(addr, val); |
3010 | 6f27aba6 | blueswir1 | break;
|
3011 | 6f27aba6 | blueswir1 | case 2: |
3012 | 2065061e | Igor V. Kovalenko | stw_user_secondary(addr, val); |
3013 | 6f27aba6 | blueswir1 | break;
|
3014 | 6f27aba6 | blueswir1 | case 4: |
3015 | 2065061e | Igor V. Kovalenko | stl_user_secondary(addr, val); |
3016 | 6f27aba6 | blueswir1 | break;
|
3017 | 6f27aba6 | blueswir1 | case 8: |
3018 | 6f27aba6 | blueswir1 | default:
|
3019 | 2065061e | Igor V. Kovalenko | stq_user_secondary(addr, val); |
3020 | 2065061e | Igor V. Kovalenko | break;
|
3021 | 2065061e | Igor V. Kovalenko | } |
3022 | 2065061e | Igor V. Kovalenko | } else {
|
3023 | 2065061e | Igor V. Kovalenko | switch(size) {
|
3024 | 2065061e | Igor V. Kovalenko | case 1: |
3025 | 2065061e | Igor V. Kovalenko | stb_user(addr, val); |
3026 | 2065061e | Igor V. Kovalenko | break;
|
3027 | 2065061e | Igor V. Kovalenko | case 2: |
3028 | 2065061e | Igor V. Kovalenko | stw_user(addr, val); |
3029 | 2065061e | Igor V. Kovalenko | break;
|
3030 | 2065061e | Igor V. Kovalenko | case 4: |
3031 | 2065061e | Igor V. Kovalenko | stl_user(addr, val); |
3032 | 2065061e | Igor V. Kovalenko | break;
|
3033 | 2065061e | Igor V. Kovalenko | case 8: |
3034 | 2065061e | Igor V. Kovalenko | default:
|
3035 | 2065061e | Igor V. Kovalenko | stq_user(addr, val); |
3036 | 6f27aba6 | blueswir1 | break;
|
3037 | 6f27aba6 | blueswir1 | } |
3038 | 81ad8ba2 | blueswir1 | } |
3039 | 81ad8ba2 | blueswir1 | } |
3040 | 81ad8ba2 | blueswir1 | break;
|
3041 | 3475187d | bellard | case 0x14: // Bypass |
3042 | 3475187d | bellard | case 0x15: // Bypass, non-cacheable |
3043 | 81ad8ba2 | blueswir1 | case 0x1c: // Bypass LE |
3044 | 81ad8ba2 | blueswir1 | case 0x1d: // Bypass, non-cacheable LE |
3045 | 0f8a249a | blueswir1 | { |
3046 | 02aab46a | bellard | switch(size) {
|
3047 | 02aab46a | bellard | case 1: |
3048 | 1a2fb1c0 | blueswir1 | stb_phys(addr, val); |
3049 | 02aab46a | bellard | break;
|
3050 | 02aab46a | bellard | case 2: |
3051 | a4e7dd52 | blueswir1 | stw_phys(addr, val); |
3052 | 02aab46a | bellard | break;
|
3053 | 02aab46a | bellard | case 4: |
3054 | a4e7dd52 | blueswir1 | stl_phys(addr, val); |
3055 | 02aab46a | bellard | break;
|
3056 | 02aab46a | bellard | case 8: |
3057 | 02aab46a | bellard | default:
|
3058 | a4e7dd52 | blueswir1 | stq_phys(addr, val); |
3059 | 02aab46a | bellard | break;
|
3060 | 02aab46a | bellard | } |
3061 | 0f8a249a | blueswir1 | } |
3062 | 0f8a249a | blueswir1 | return;
|
3063 | db166940 | blueswir1 | case 0x24: // Nucleus quad LDD 128 bit atomic |
3064 | db166940 | blueswir1 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
3065 | db166940 | blueswir1 | // Only ldda allowed
|
3066 | db166940 | blueswir1 | raise_exception(TT_ILL_INSN); |
3067 | db166940 | blueswir1 | return;
|
3068 | 83469015 | bellard | case 0x04: // Nucleus |
3069 | 83469015 | bellard | case 0x0c: // Nucleus Little Endian (LE) |
3070 | 2065061e | Igor V. Kovalenko | { |
3071 | 2065061e | Igor V. Kovalenko | switch(size) {
|
3072 | 2065061e | Igor V. Kovalenko | case 1: |
3073 | 2065061e | Igor V. Kovalenko | stb_nucleus(addr, val); |
3074 | 2065061e | Igor V. Kovalenko | break;
|
3075 | 2065061e | Igor V. Kovalenko | case 2: |
3076 | 2065061e | Igor V. Kovalenko | stw_nucleus(addr, val); |
3077 | 2065061e | Igor V. Kovalenko | break;
|
3078 | 2065061e | Igor V. Kovalenko | case 4: |
3079 | 2065061e | Igor V. Kovalenko | stl_nucleus(addr, val); |
3080 | 2065061e | Igor V. Kovalenko | break;
|
3081 | 2065061e | Igor V. Kovalenko | default:
|
3082 | 2065061e | Igor V. Kovalenko | case 8: |
3083 | 2065061e | Igor V. Kovalenko | stq_nucleus(addr, val); |
3084 | 2065061e | Igor V. Kovalenko | break;
|
3085 | 2065061e | Igor V. Kovalenko | } |
3086 | 2065061e | Igor V. Kovalenko | break;
|
3087 | 2065061e | Igor V. Kovalenko | } |
3088 | 2065061e | Igor V. Kovalenko | |
3089 | 83469015 | bellard | case 0x4a: // UPA config |
3090 | 0f8a249a | blueswir1 | // XXX
|
3091 | 0f8a249a | blueswir1 | return;
|
3092 | 3475187d | bellard | case 0x45: // LSU |
3093 | 0f8a249a | blueswir1 | { |
3094 | 0f8a249a | blueswir1 | uint64_t oldreg; |
3095 | 0f8a249a | blueswir1 | |
3096 | 0f8a249a | blueswir1 | oldreg = env->lsu; |
3097 | 1a2fb1c0 | blueswir1 | env->lsu = val & (DMMU_E | IMMU_E); |
3098 | 0f8a249a | blueswir1 | // Mappings generated during D/I MMU disabled mode are
|
3099 | 0f8a249a | blueswir1 | // invalid in normal mode
|
3100 | 0f8a249a | blueswir1 | if (oldreg != env->lsu) {
|
3101 | 77f193da | blueswir1 | DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", |
3102 | 77f193da | blueswir1 | oldreg, env->lsu); |
3103 | 83469015 | bellard | #ifdef DEBUG_MMU
|
3104 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env1); |
3105 | 83469015 | bellard | #endif
|
3106 | 0f8a249a | blueswir1 | tlb_flush(env, 1);
|
3107 | 0f8a249a | blueswir1 | } |
3108 | 0f8a249a | blueswir1 | return;
|
3109 | 0f8a249a | blueswir1 | } |
3110 | 3475187d | bellard | case 0x50: // I-MMU regs |
3111 | 0f8a249a | blueswir1 | { |
3112 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
3113 | 0f8a249a | blueswir1 | uint64_t oldreg; |
3114 | 3b46e624 | ths | |
3115 | 0f8a249a | blueswir1 | oldreg = env->immuregs[reg]; |
3116 | 3475187d | bellard | switch(reg) {
|
3117 | 3475187d | bellard | case 0: // RO |
3118 | 3475187d | bellard | return;
|
3119 | 3475187d | bellard | case 1: // Not in I-MMU |
3120 | 3475187d | bellard | case 2: |
3121 | 3475187d | bellard | return;
|
3122 | 3475187d | bellard | case 3: // SFSR |
3123 | 1a2fb1c0 | blueswir1 | if ((val & 1) == 0) |
3124 | 1a2fb1c0 | blueswir1 | val = 0; // Clear SFSR |
3125 | 6e8e7d4c | Igor Kovalenko | env->immu.sfsr = val; |
3126 | 3475187d | bellard | break;
|
3127 | 6e8e7d4c | Igor Kovalenko | case 4: // RO |
3128 | 6e8e7d4c | Igor Kovalenko | return;
|
3129 | 3475187d | bellard | case 5: // TSB access |
3130 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" |
3131 | 6e8e7d4c | Igor Kovalenko | PRIx64 "\n", env->immu.tsb, val);
|
3132 | 6e8e7d4c | Igor Kovalenko | env->immu.tsb = val; |
3133 | 6e8e7d4c | Igor Kovalenko | break;
|
3134 | 3475187d | bellard | case 6: // Tag access |
3135 | 6e8e7d4c | Igor Kovalenko | env->immu.tag_access = val; |
3136 | 6e8e7d4c | Igor Kovalenko | break;
|
3137 | 6e8e7d4c | Igor Kovalenko | case 7: |
3138 | 6e8e7d4c | Igor Kovalenko | case 8: |
3139 | 6e8e7d4c | Igor Kovalenko | return;
|
3140 | 3475187d | bellard | default:
|
3141 | 3475187d | bellard | break;
|
3142 | 3475187d | bellard | } |
3143 | 6e8e7d4c | Igor Kovalenko | |
3144 | 3475187d | bellard | if (oldreg != env->immuregs[reg]) {
|
3145 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
3146 | 77f193da | blueswir1 | PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
|
3147 | 3475187d | bellard | } |
3148 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
3149 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env); |
3150 | 3475187d | bellard | #endif
|
3151 | 0f8a249a | blueswir1 | return;
|
3152 | 0f8a249a | blueswir1 | } |
3153 | 3475187d | bellard | case 0x54: // I-MMU data in |
3154 | f707726e | Igor Kovalenko | replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
|
3155 | f707726e | Igor Kovalenko | return;
|
3156 | 3475187d | bellard | case 0x55: // I-MMU data access |
3157 | 0f8a249a | blueswir1 | { |
3158 | cc6747f4 | blueswir1 | // TODO: auto demap
|
3159 | cc6747f4 | blueswir1 | |
3160 | 1a2fb1c0 | blueswir1 | unsigned int i = (addr >> 3) & 0x3f; |
3161 | 3475187d | bellard | |
3162 | f707726e | Igor Kovalenko | replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env); |
3163 | 6e8e7d4c | Igor Kovalenko | |
3164 | 6e8e7d4c | Igor Kovalenko | #ifdef DEBUG_MMU
|
3165 | f707726e | Igor Kovalenko | DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
|
3166 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env); |
3167 | 6e8e7d4c | Igor Kovalenko | #endif
|
3168 | 0f8a249a | blueswir1 | return;
|
3169 | 0f8a249a | blueswir1 | } |
3170 | 3475187d | bellard | case 0x57: // I-MMU demap |
3171 | 170f4c55 | Igor V. Kovalenko | demap_tlb(env->itlb, addr, "immu", env);
|
3172 | 0f8a249a | blueswir1 | return;
|
3173 | 3475187d | bellard | case 0x58: // D-MMU regs |
3174 | 0f8a249a | blueswir1 | { |
3175 | 1a2fb1c0 | blueswir1 | int reg = (addr >> 3) & 0xf; |
3176 | 0f8a249a | blueswir1 | uint64_t oldreg; |
3177 | 3b46e624 | ths | |
3178 | 0f8a249a | blueswir1 | oldreg = env->dmmuregs[reg]; |
3179 | 3475187d | bellard | switch(reg) {
|
3180 | 3475187d | bellard | case 0: // RO |
3181 | 3475187d | bellard | case 4: |
3182 | 3475187d | bellard | return;
|
3183 | 3475187d | bellard | case 3: // SFSR |
3184 | 1a2fb1c0 | blueswir1 | if ((val & 1) == 0) { |
3185 | 1a2fb1c0 | blueswir1 | val = 0; // Clear SFSR, Fault address |
3186 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfar = 0;
|
3187 | 0f8a249a | blueswir1 | } |
3188 | 6e8e7d4c | Igor Kovalenko | env->dmmu.sfsr = val; |
3189 | 3475187d | bellard | break;
|
3190 | 3475187d | bellard | case 1: // Primary context |
3191 | 6e8e7d4c | Igor Kovalenko | env->dmmu.mmu_primary_context = val; |
3192 | 664a65b0 | Igor V. Kovalenko | /* can be optimized to only flush MMU_USER_IDX
|
3193 | 664a65b0 | Igor V. Kovalenko | and MMU_KERNEL_IDX entries */
|
3194 | 664a65b0 | Igor V. Kovalenko | tlb_flush(env, 1);
|
3195 | 6e8e7d4c | Igor Kovalenko | break;
|
3196 | 3475187d | bellard | case 2: // Secondary context |
3197 | 6e8e7d4c | Igor Kovalenko | env->dmmu.mmu_secondary_context = val; |
3198 | 664a65b0 | Igor V. Kovalenko | /* can be optimized to only flush MMU_USER_SECONDARY_IDX
|
3199 | 664a65b0 | Igor V. Kovalenko | and MMU_KERNEL_SECONDARY_IDX entries */
|
3200 | 664a65b0 | Igor V. Kovalenko | tlb_flush(env, 1);
|
3201 | 6e8e7d4c | Igor Kovalenko | break;
|
3202 | 3475187d | bellard | case 5: // TSB access |
3203 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" |
3204 | 6e8e7d4c | Igor Kovalenko | PRIx64 "\n", env->dmmu.tsb, val);
|
3205 | 6e8e7d4c | Igor Kovalenko | env->dmmu.tsb = val; |
3206 | 6e8e7d4c | Igor Kovalenko | break;
|
3207 | 3475187d | bellard | case 6: // Tag access |
3208 | 6e8e7d4c | Igor Kovalenko | env->dmmu.tag_access = val; |
3209 | 6e8e7d4c | Igor Kovalenko | break;
|
3210 | 3475187d | bellard | case 7: // Virtual Watchpoint |
3211 | 3475187d | bellard | case 8: // Physical Watchpoint |
3212 | 3475187d | bellard | default:
|
3213 | 6e8e7d4c | Igor Kovalenko | env->dmmuregs[reg] = val; |
3214 | 3475187d | bellard | break;
|
3215 | 3475187d | bellard | } |
3216 | 6e8e7d4c | Igor Kovalenko | |
3217 | 3475187d | bellard | if (oldreg != env->dmmuregs[reg]) {
|
3218 | 6e8e7d4c | Igor Kovalenko | DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" |
3219 | 77f193da | blueswir1 | PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
|
3220 | 3475187d | bellard | } |
3221 | 952a328f | blueswir1 | #ifdef DEBUG_MMU
|
3222 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env); |
3223 | 3475187d | bellard | #endif
|
3224 | 0f8a249a | blueswir1 | return;
|
3225 | 0f8a249a | blueswir1 | } |
3226 | 3475187d | bellard | case 0x5c: // D-MMU data in |
3227 | f707726e | Igor Kovalenko | replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
|
3228 | f707726e | Igor Kovalenko | return;
|
3229 | 3475187d | bellard | case 0x5d: // D-MMU data access |
3230 | 0f8a249a | blueswir1 | { |
3231 | 1a2fb1c0 | blueswir1 | unsigned int i = (addr >> 3) & 0x3f; |
3232 | 3475187d | bellard | |
3233 | f707726e | Igor Kovalenko | replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env); |
3234 | f707726e | Igor Kovalenko | |
3235 | 6e8e7d4c | Igor Kovalenko | #ifdef DEBUG_MMU
|
3236 | f707726e | Igor Kovalenko | DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
|
3237 | d41160a3 | Blue Swirl | dump_mmu(stdout, fprintf, env); |
3238 | 6e8e7d4c | Igor Kovalenko | #endif
|
3239 | 0f8a249a | blueswir1 | return;
|
3240 | 0f8a249a | blueswir1 | } |
3241 | 3475187d | bellard | case 0x5f: // D-MMU demap |
3242 | 170f4c55 | Igor V. Kovalenko | demap_tlb(env->dtlb, addr, "dmmu", env);
|
3243 | cc6747f4 | blueswir1 | return;
|
3244 | 83469015 | bellard | case 0x49: // Interrupt data receive |
3245 | 0f8a249a | blueswir1 | // XXX
|
3246 | 0f8a249a | blueswir1 | return;
|
3247 | f7350b47 | blueswir1 | case 0x46: // D-cache data |
3248 | f7350b47 | blueswir1 | case 0x47: // D-cache tag access |
3249 | a5a52cf2 | blueswir1 | case 0x4b: // E-cache error enable |
3250 | a5a52cf2 | blueswir1 | case 0x4c: // E-cache asynchronous fault status |
3251 | a5a52cf2 | blueswir1 | case 0x4d: // E-cache asynchronous fault address |
3252 | f7350b47 | blueswir1 | case 0x4e: // E-cache tag data |
3253 | f7350b47 | blueswir1 | case 0x66: // I-cache instruction access |
3254 | f7350b47 | blueswir1 | case 0x67: // I-cache tag access |
3255 | f7350b47 | blueswir1 | case 0x6e: // I-cache predecode |
3256 | f7350b47 | blueswir1 | case 0x6f: // I-cache LRU etc. |
3257 | f7350b47 | blueswir1 | case 0x76: // E-cache tag |
3258 | f7350b47 | blueswir1 | case 0x7e: // E-cache tag |
3259 | f7350b47 | blueswir1 | return;
|
3260 | 3475187d | bellard | case 0x51: // I-MMU 8k TSB pointer, RO |
3261 | 3475187d | bellard | case 0x52: // I-MMU 64k TSB pointer, RO |
3262 | 3475187d | bellard | case 0x56: // I-MMU tag read, RO |
3263 | 3475187d | bellard | case 0x59: // D-MMU 8k TSB pointer, RO |
3264 | 3475187d | bellard | case 0x5a: // D-MMU 64k TSB pointer, RO |
3265 | 3475187d | bellard | case 0x5b: // D-MMU data pointer, RO |
3266 | 3475187d | bellard | case 0x5e: // D-MMU tag read, RO |
3267 | 83469015 | bellard | case 0x48: // Interrupt dispatch, RO |
3268 | 83469015 | bellard | case 0x7f: // Incoming interrupt vector, RO |
3269 | 83469015 | bellard | case 0x82: // Primary no-fault, RO |
3270 | 83469015 | bellard | case 0x83: // Secondary no-fault, RO |
3271 | 83469015 | bellard | case 0x8a: // Primary no-fault LE, RO |
3272 | 83469015 | bellard | case 0x8b: // Secondary no-fault LE, RO |
3273 | 3475187d | bellard | default:
|
3274 | e18231a3 | blueswir1 | do_unassigned_access(addr, 1, 0, 1, size); |
3275 | 0f8a249a | blueswir1 | return;
|
3276 | 3475187d | bellard | } |
3277 | 3475187d | bellard | } |
3278 | 81ad8ba2 | blueswir1 | #endif /* CONFIG_USER_ONLY */ |
3279 | 3391c818 | blueswir1 | |
3280 | db166940 | blueswir1 | void helper_ldda_asi(target_ulong addr, int asi, int rd) |
3281 | db166940 | blueswir1 | { |
3282 | db166940 | blueswir1 | if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
3283 | 2aae2b8e | Igor V. Kovalenko | || (cpu_has_hypervisor(env) |
3284 | 5578ceab | blueswir1 | && asi >= 0x30 && asi < 0x80 |
3285 | fb79ceb9 | blueswir1 | && !(env->hpstate & HS_PRIV))) |
3286 | db166940 | blueswir1 | raise_exception(TT_PRIV_ACT); |
3287 | db166940 | blueswir1 | |
3288 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
3289 | 1295001c | Igor V. Kovalenko | |
3290 | db166940 | blueswir1 | switch (asi) {
|
3291 | 03ae77d6 | Blue Swirl | #if !defined(CONFIG_USER_ONLY)
|
3292 | db166940 | blueswir1 | case 0x24: // Nucleus quad LDD 128 bit atomic |
3293 | db166940 | blueswir1 | case 0x2c: // Nucleus quad LDD 128 bit atomic LE |
3294 | db166940 | blueswir1 | helper_check_align(addr, 0xf);
|
3295 | db166940 | blueswir1 | if (rd == 0) { |
3296 | 54a3c0f0 | Igor V. Kovalenko | env->gregs[1] = ldq_nucleus(addr + 8); |
3297 | db166940 | blueswir1 | if (asi == 0x2c) |
3298 | db166940 | blueswir1 | bswap64s(&env->gregs[1]);
|
3299 | db166940 | blueswir1 | } else if (rd < 8) { |
3300 | 54a3c0f0 | Igor V. Kovalenko | env->gregs[rd] = ldq_nucleus(addr); |
3301 | 54a3c0f0 | Igor V. Kovalenko | env->gregs[rd + 1] = ldq_nucleus(addr + 8); |
3302 | db166940 | blueswir1 | if (asi == 0x2c) { |
3303 | db166940 | blueswir1 | bswap64s(&env->gregs[rd]); |
3304 | db166940 | blueswir1 | bswap64s(&env->gregs[rd + 1]);
|
3305 | db166940 | blueswir1 | } |
3306 | db166940 | blueswir1 | } else {
|
3307 | 54a3c0f0 | Igor V. Kovalenko | env->regwptr[rd] = ldq_nucleus(addr); |
3308 | 54a3c0f0 | Igor V. Kovalenko | env->regwptr[rd + 1] = ldq_nucleus(addr + 8); |
3309 | db166940 | blueswir1 | if (asi == 0x2c) { |
3310 | db166940 | blueswir1 | bswap64s(&env->regwptr[rd]); |
3311 | db166940 | blueswir1 | bswap64s(&env->regwptr[rd + 1]);
|
3312 | db166940 | blueswir1 | } |
3313 | db166940 | blueswir1 | } |
3314 | db166940 | blueswir1 | break;
|
3315 | 03ae77d6 | Blue Swirl | #endif
|
3316 | db166940 | blueswir1 | default:
|
3317 | db166940 | blueswir1 | helper_check_align(addr, 0x3);
|
3318 | db166940 | blueswir1 | if (rd == 0) |
3319 | db166940 | blueswir1 | env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3320 | db166940 | blueswir1 | else if (rd < 8) { |
3321 | db166940 | blueswir1 | env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0); |
3322 | db166940 | blueswir1 | env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3323 | db166940 | blueswir1 | } else {
|
3324 | db166940 | blueswir1 | env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0); |
3325 | db166940 | blueswir1 | env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0); |
3326 | db166940 | blueswir1 | } |
3327 | db166940 | blueswir1 | break;
|
3328 | db166940 | blueswir1 | } |
3329 | db166940 | blueswir1 | } |
3330 | db166940 | blueswir1 | |
3331 | 1a2fb1c0 | blueswir1 | void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
3332 | 3391c818 | blueswir1 | { |
3333 | 3391c818 | blueswir1 | unsigned int i; |
3334 | 4183f36d | Tsuneo Saito | CPU_DoubleU u; |
3335 | 3391c818 | blueswir1 | |
3336 | c2bc0e38 | blueswir1 | helper_check_align(addr, 3);
|
3337 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
3338 | 1295001c | Igor V. Kovalenko | |
3339 | 3391c818 | blueswir1 | switch (asi) {
|
3340 | 3391c818 | blueswir1 | case 0xf0: // Block load primary |
3341 | 3391c818 | blueswir1 | case 0xf1: // Block load secondary |
3342 | 3391c818 | blueswir1 | case 0xf8: // Block load primary LE |
3343 | 3391c818 | blueswir1 | case 0xf9: // Block load secondary LE |
3344 | 51996525 | blueswir1 | if (rd & 7) { |
3345 | 51996525 | blueswir1 | raise_exception(TT_ILL_INSN); |
3346 | 51996525 | blueswir1 | return;
|
3347 | 51996525 | blueswir1 | } |
3348 | c2bc0e38 | blueswir1 | helper_check_align(addr, 0x3f);
|
3349 | 51996525 | blueswir1 | for (i = 0; i < 16; i++) { |
3350 | 77f193da | blueswir1 | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, |
3351 | 77f193da | blueswir1 | 0);
|
3352 | 1a2fb1c0 | blueswir1 | addr += 4;
|
3353 | 3391c818 | blueswir1 | } |
3354 | 3391c818 | blueswir1 | |
3355 | 3391c818 | blueswir1 | return;
|
3356 | 0e2fa9ca | Igor V. Kovalenko | case 0x70: // Block load primary, user privilege |
3357 | 0e2fa9ca | Igor V. Kovalenko | case 0x71: // Block load secondary, user privilege |
3358 | 0e2fa9ca | Igor V. Kovalenko | if (rd & 7) { |
3359 | 0e2fa9ca | Igor V. Kovalenko | raise_exception(TT_ILL_INSN); |
3360 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3361 | 0e2fa9ca | Igor V. Kovalenko | } |
3362 | 0e2fa9ca | Igor V. Kovalenko | helper_check_align(addr, 0x3f);
|
3363 | 0e2fa9ca | Igor V. Kovalenko | for (i = 0; i < 16; i++) { |
3364 | 0e2fa9ca | Igor V. Kovalenko | *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x1f, 4, |
3365 | 0e2fa9ca | Igor V. Kovalenko | 0);
|
3366 | 0e2fa9ca | Igor V. Kovalenko | addr += 4;
|
3367 | 0e2fa9ca | Igor V. Kovalenko | } |
3368 | 0e2fa9ca | Igor V. Kovalenko | |
3369 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3370 | 3391c818 | blueswir1 | default:
|
3371 | 3391c818 | blueswir1 | break;
|
3372 | 3391c818 | blueswir1 | } |
3373 | 3391c818 | blueswir1 | |
3374 | 3391c818 | blueswir1 | switch(size) {
|
3375 | 3391c818 | blueswir1 | default:
|
3376 | 3391c818 | blueswir1 | case 4: |
3377 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd]) = helper_ld_asi(addr, asi, size, 0);
|
3378 | 3391c818 | blueswir1 | break;
|
3379 | 3391c818 | blueswir1 | case 8: |
3380 | 4183f36d | Tsuneo Saito | u.ll = helper_ld_asi(addr, asi, size, 0);
|
3381 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
3382 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
3383 | 3391c818 | blueswir1 | break;
|
3384 | 1f587329 | blueswir1 | case 16: |
3385 | 4183f36d | Tsuneo Saito | u.ll = helper_ld_asi(addr, asi, 8, 0); |
3386 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
3387 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
3388 | 4183f36d | Tsuneo Saito | u.ll = helper_ld_asi(addr + 8, asi, 8, 0); |
3389 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd++]) = u.l.upper; |
3390 | 4183f36d | Tsuneo Saito | *((uint32_t *)&env->fpr[rd++]) = u.l.lower; |
3391 | 1f587329 | blueswir1 | break;
|
3392 | 3391c818 | blueswir1 | } |
3393 | 3391c818 | blueswir1 | } |
3394 | 3391c818 | blueswir1 | |
3395 | 1a2fb1c0 | blueswir1 | void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
3396 | 3391c818 | blueswir1 | { |
3397 | 3391c818 | blueswir1 | unsigned int i; |
3398 | 1a2fb1c0 | blueswir1 | target_ulong val = 0;
|
3399 | e1ef36c4 | Tsuneo Saito | CPU_DoubleU u; |
3400 | 3391c818 | blueswir1 | |
3401 | c2bc0e38 | blueswir1 | helper_check_align(addr, 3);
|
3402 | 1295001c | Igor V. Kovalenko | addr = asi_address_mask(env, asi, addr); |
3403 | 1295001c | Igor V. Kovalenko | |
3404 | 3391c818 | blueswir1 | switch (asi) {
|
3405 | c99657d3 | blueswir1 | case 0xe0: // UA2007 Block commit store primary (cache flush) |
3406 | c99657d3 | blueswir1 | case 0xe1: // UA2007 Block commit store secondary (cache flush) |
3407 | 3391c818 | blueswir1 | case 0xf0: // Block store primary |
3408 | 3391c818 | blueswir1 | case 0xf1: // Block store secondary |
3409 | 3391c818 | blueswir1 | case 0xf8: // Block store primary LE |
3410 | 3391c818 | blueswir1 | case 0xf9: // Block store secondary LE |
3411 | 51996525 | blueswir1 | if (rd & 7) { |
3412 | 51996525 | blueswir1 | raise_exception(TT_ILL_INSN); |
3413 | 51996525 | blueswir1 | return;
|
3414 | 51996525 | blueswir1 | } |
3415 | c2bc0e38 | blueswir1 | helper_check_align(addr, 0x3f);
|
3416 | 51996525 | blueswir1 | for (i = 0; i < 16; i++) { |
3417 | 1a2fb1c0 | blueswir1 | val = *(uint32_t *)&env->fpr[rd++]; |
3418 | 1a2fb1c0 | blueswir1 | helper_st_asi(addr, val, asi & 0x8f, 4); |
3419 | 1a2fb1c0 | blueswir1 | addr += 4;
|
3420 | 3391c818 | blueswir1 | } |
3421 | 3391c818 | blueswir1 | |
3422 | 3391c818 | blueswir1 | return;
|
3423 | 0e2fa9ca | Igor V. Kovalenko | case 0x70: // Block store primary, user privilege |
3424 | 0e2fa9ca | Igor V. Kovalenko | case 0x71: // Block store secondary, user privilege |
3425 | 0e2fa9ca | Igor V. Kovalenko | if (rd & 7) { |
3426 | 0e2fa9ca | Igor V. Kovalenko | raise_exception(TT_ILL_INSN); |
3427 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3428 | 0e2fa9ca | Igor V. Kovalenko | } |
3429 | 0e2fa9ca | Igor V. Kovalenko | helper_check_align(addr, 0x3f);
|
3430 | 0e2fa9ca | Igor V. Kovalenko | for (i = 0; i < 16; i++) { |
3431 | 0e2fa9ca | Igor V. Kovalenko | val = *(uint32_t *)&env->fpr[rd++]; |
3432 | 0e2fa9ca | Igor V. Kovalenko | helper_st_asi(addr, val, asi & 0x1f, 4); |
3433 | 0e2fa9ca | Igor V. Kovalenko | addr += 4;
|
3434 | 0e2fa9ca | Igor V. Kovalenko | } |
3435 | 0e2fa9ca | Igor V. Kovalenko | |
3436 | 0e2fa9ca | Igor V. Kovalenko | return;
|
3437 | 3391c818 | blueswir1 | default:
|
3438 | 3391c818 | blueswir1 | break;
|
3439 | 3391c818 | blueswir1 | } |
3440 | 3391c818 | blueswir1 | |
3441 | 3391c818 | blueswir1 | switch(size) {
|
3442 | 3391c818 | blueswir1 | default:
|
3443 | 3391c818 | blueswir1 | case 4: |
3444 | e1ef36c4 | Tsuneo Saito | helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size); |
3445 | 3391c818 | blueswir1 | break;
|
3446 | 3391c818 | blueswir1 | case 8: |
3447 | e1ef36c4 | Tsuneo Saito | u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
3448 | e1ef36c4 | Tsuneo Saito | u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
3449 | e1ef36c4 | Tsuneo Saito | helper_st_asi(addr, u.ll, asi, size); |
3450 | 3391c818 | blueswir1 | break;
|
3451 | 1f587329 | blueswir1 | case 16: |
3452 | e1ef36c4 | Tsuneo Saito | u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
3453 | e1ef36c4 | Tsuneo Saito | u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
3454 | e1ef36c4 | Tsuneo Saito | helper_st_asi(addr, u.ll, asi, 8);
|
3455 | e1ef36c4 | Tsuneo Saito | u.l.upper = *(uint32_t *)&env->fpr[rd++]; |
3456 | e1ef36c4 | Tsuneo Saito | u.l.lower = *(uint32_t *)&env->fpr[rd++]; |
3457 | e1ef36c4 | Tsuneo Saito | helper_st_asi(addr + 8, u.ll, asi, 8); |
3458 | 1f587329 | blueswir1 | break;
|
3459 | 3391c818 | blueswir1 | } |
3460 | 1a2fb1c0 | blueswir1 | } |
3461 | 1a2fb1c0 | blueswir1 | |
3462 | 1a2fb1c0 | blueswir1 | target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, |
3463 | 1a2fb1c0 | blueswir1 | target_ulong val2, uint32_t asi) |
3464 | 1a2fb1c0 | blueswir1 | { |
3465 | 1a2fb1c0 | blueswir1 | target_ulong ret; |
3466 | 1a2fb1c0 | blueswir1 | |
3467 | 1121f879 | blueswir1 | val2 &= 0xffffffffUL;
|
3468 | 1a2fb1c0 | blueswir1 | ret = helper_ld_asi(addr, asi, 4, 0); |
3469 | 1a2fb1c0 | blueswir1 | ret &= 0xffffffffUL;
|
3470 | 1121f879 | blueswir1 | if (val2 == ret)
|
3471 | 1121f879 | blueswir1 | helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4); |
3472 | 1a2fb1c0 | blueswir1 | return ret;
|
3473 | 3391c818 | blueswir1 | } |
3474 | 3391c818 | blueswir1 | |
3475 | 1a2fb1c0 | blueswir1 | target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
3476 | 1a2fb1c0 | blueswir1 | target_ulong val2, uint32_t asi) |
3477 | 1a2fb1c0 | blueswir1 | { |
3478 | 1a2fb1c0 | blueswir1 | target_ulong ret; |
3479 | 1a2fb1c0 | blueswir1 | |
3480 | 1a2fb1c0 | blueswir1 | ret = helper_ld_asi(addr, asi, 8, 0); |
3481 | 1121f879 | blueswir1 | if (val2 == ret)
|
3482 | 1121f879 | blueswir1 | helper_st_asi(addr, val1, asi, 8);
|
3483 | 1a2fb1c0 | blueswir1 | return ret;
|
3484 | 1a2fb1c0 | blueswir1 | } |
3485 | 81ad8ba2 | blueswir1 | #endif /* TARGET_SPARC64 */ |
3486 | 3475187d | bellard | |
3487 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3488 | 1a2fb1c0 | blueswir1 | void helper_rett(void) |
3489 | e8af50a3 | bellard | { |
3490 | af7bf89b | bellard | unsigned int cwp; |
3491 | af7bf89b | bellard | |
3492 | d4218d99 | blueswir1 | if (env->psret == 1) |
3493 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
3494 | d4218d99 | blueswir1 | |
3495 | e8af50a3 | bellard | env->psret = 1;
|
3496 | 5a834bb4 | Blue Swirl | cwp = cwp_inc(env->cwp + 1) ;
|
3497 | e8af50a3 | bellard | if (env->wim & (1 << cwp)) { |
3498 | e8af50a3 | bellard | raise_exception(TT_WIN_UNF); |
3499 | e8af50a3 | bellard | } |
3500 | e8af50a3 | bellard | set_cwp(cwp); |
3501 | e8af50a3 | bellard | env->psrs = env->psrps; |
3502 | e8af50a3 | bellard | } |
3503 | 3475187d | bellard | #endif
|
3504 | e8af50a3 | bellard | |
3505 | 0fcec41e | Aurelien Jarno | static target_ulong helper_udiv_common(target_ulong a, target_ulong b, int cc) |
3506 | 3b89f26c | blueswir1 | { |
3507 | 0fcec41e | Aurelien Jarno | int overflow = 0; |
3508 | 3b89f26c | blueswir1 | uint64_t x0; |
3509 | 3b89f26c | blueswir1 | uint32_t x1; |
3510 | 3b89f26c | blueswir1 | |
3511 | 7621a90d | blueswir1 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3512 | 09487205 | Igor V. Kovalenko | x1 = (b & 0xffffffff);
|
3513 | 3b89f26c | blueswir1 | |
3514 | 3b89f26c | blueswir1 | if (x1 == 0) { |
3515 | 3b89f26c | blueswir1 | raise_exception(TT_DIV_ZERO); |
3516 | 3b89f26c | blueswir1 | } |
3517 | 3b89f26c | blueswir1 | |
3518 | 3b89f26c | blueswir1 | x0 = x0 / x1; |
3519 | 3b89f26c | blueswir1 | if (x0 > 0xffffffff) { |
3520 | 0fcec41e | Aurelien Jarno | x0 = 0xffffffff;
|
3521 | 0fcec41e | Aurelien Jarno | overflow = 1;
|
3522 | 0fcec41e | Aurelien Jarno | } |
3523 | 0fcec41e | Aurelien Jarno | |
3524 | 0fcec41e | Aurelien Jarno | if (cc) {
|
3525 | 0fcec41e | Aurelien Jarno | env->cc_dst = x0; |
3526 | 0fcec41e | Aurelien Jarno | env->cc_src2 = overflow; |
3527 | 0fcec41e | Aurelien Jarno | env->cc_op = CC_OP_DIV; |
3528 | 3b89f26c | blueswir1 | } |
3529 | 0fcec41e | Aurelien Jarno | return x0;
|
3530 | 3b89f26c | blueswir1 | } |
3531 | 3b89f26c | blueswir1 | |
3532 | 0fcec41e | Aurelien Jarno | target_ulong helper_udiv(target_ulong a, target_ulong b) |
3533 | 0fcec41e | Aurelien Jarno | { |
3534 | 0fcec41e | Aurelien Jarno | return helper_udiv_common(a, b, 0); |
3535 | 0fcec41e | Aurelien Jarno | } |
3536 | 0fcec41e | Aurelien Jarno | |
3537 | 0fcec41e | Aurelien Jarno | target_ulong helper_udiv_cc(target_ulong a, target_ulong b) |
3538 | 0fcec41e | Aurelien Jarno | { |
3539 | 0fcec41e | Aurelien Jarno | return helper_udiv_common(a, b, 1); |
3540 | 0fcec41e | Aurelien Jarno | } |
3541 | 0fcec41e | Aurelien Jarno | |
3542 | 0fcec41e | Aurelien Jarno | static target_ulong helper_sdiv_common(target_ulong a, target_ulong b, int cc) |
3543 | 3b89f26c | blueswir1 | { |
3544 | 0fcec41e | Aurelien Jarno | int overflow = 0; |
3545 | 3b89f26c | blueswir1 | int64_t x0; |
3546 | 3b89f26c | blueswir1 | int32_t x1; |
3547 | 3b89f26c | blueswir1 | |
3548 | 7621a90d | blueswir1 | x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32); |
3549 | 09487205 | Igor V. Kovalenko | x1 = (b & 0xffffffff);
|
3550 | 3b89f26c | blueswir1 | |
3551 | 3b89f26c | blueswir1 | if (x1 == 0) { |
3552 | 3b89f26c | blueswir1 | raise_exception(TT_DIV_ZERO); |
3553 | 3b89f26c | blueswir1 | } |
3554 | 3b89f26c | blueswir1 | |
3555 | 3b89f26c | blueswir1 | x0 = x0 / x1; |
3556 | 3b89f26c | blueswir1 | if ((int32_t) x0 != x0) {
|
3557 | 0fcec41e | Aurelien Jarno | x0 = x0 < 0 ? 0x80000000: 0x7fffffff; |
3558 | 0fcec41e | Aurelien Jarno | overflow = 1;
|
3559 | 0fcec41e | Aurelien Jarno | } |
3560 | 0fcec41e | Aurelien Jarno | |
3561 | 0fcec41e | Aurelien Jarno | if (cc) {
|
3562 | 0fcec41e | Aurelien Jarno | env->cc_dst = x0; |
3563 | 0fcec41e | Aurelien Jarno | env->cc_src2 = overflow; |
3564 | 0fcec41e | Aurelien Jarno | env->cc_op = CC_OP_DIV; |
3565 | 3b89f26c | blueswir1 | } |
3566 | 0fcec41e | Aurelien Jarno | return x0;
|
3567 | 0fcec41e | Aurelien Jarno | } |
3568 | 0fcec41e | Aurelien Jarno | |
3569 | 0fcec41e | Aurelien Jarno | target_ulong helper_sdiv(target_ulong a, target_ulong b) |
3570 | 0fcec41e | Aurelien Jarno | { |
3571 | 0fcec41e | Aurelien Jarno | return helper_sdiv_common(a, b, 0); |
3572 | 0fcec41e | Aurelien Jarno | } |
3573 | 0fcec41e | Aurelien Jarno | |
3574 | 0fcec41e | Aurelien Jarno | target_ulong helper_sdiv_cc(target_ulong a, target_ulong b) |
3575 | 0fcec41e | Aurelien Jarno | { |
3576 | 0fcec41e | Aurelien Jarno | return helper_sdiv_common(a, b, 1); |
3577 | 3b89f26c | blueswir1 | } |
3578 | 3b89f26c | blueswir1 | |
3579 | 7fa76c0b | blueswir1 | void helper_stdf(target_ulong addr, int mem_idx) |
3580 | 7fa76c0b | blueswir1 | { |
3581 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3582 | 7fa76c0b | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3583 | 7fa76c0b | blueswir1 | switch (mem_idx) {
|
3584 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3585 | c2bc0e38 | blueswir1 | stfq_user(addr, DT0); |
3586 | 7fa76c0b | blueswir1 | break;
|
3587 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3588 | c2bc0e38 | blueswir1 | stfq_kernel(addr, DT0); |
3589 | 7fa76c0b | blueswir1 | break;
|
3590 | 7fa76c0b | blueswir1 | #ifdef TARGET_SPARC64
|
3591 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3592 | c2bc0e38 | blueswir1 | stfq_hypv(addr, DT0); |
3593 | 7fa76c0b | blueswir1 | break;
|
3594 | 7fa76c0b | blueswir1 | #endif
|
3595 | 7fa76c0b | blueswir1 | default:
|
3596 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_stdf: need to check MMU idx %d\n", mem_idx);
|
3597 | 7fa76c0b | blueswir1 | break;
|
3598 | 7fa76c0b | blueswir1 | } |
3599 | 7fa76c0b | blueswir1 | #else
|
3600 | 41db525e | Richard Henderson | stfq_raw(address_mask(env, addr), DT0); |
3601 | 7fa76c0b | blueswir1 | #endif
|
3602 | 7fa76c0b | blueswir1 | } |
3603 | 7fa76c0b | blueswir1 | |
3604 | 7fa76c0b | blueswir1 | void helper_lddf(target_ulong addr, int mem_idx) |
3605 | 7fa76c0b | blueswir1 | { |
3606 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3607 | 7fa76c0b | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3608 | 7fa76c0b | blueswir1 | switch (mem_idx) {
|
3609 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3610 | c2bc0e38 | blueswir1 | DT0 = ldfq_user(addr); |
3611 | 7fa76c0b | blueswir1 | break;
|
3612 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3613 | c2bc0e38 | blueswir1 | DT0 = ldfq_kernel(addr); |
3614 | 7fa76c0b | blueswir1 | break;
|
3615 | 7fa76c0b | blueswir1 | #ifdef TARGET_SPARC64
|
3616 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3617 | c2bc0e38 | blueswir1 | DT0 = ldfq_hypv(addr); |
3618 | 7fa76c0b | blueswir1 | break;
|
3619 | 7fa76c0b | blueswir1 | #endif
|
3620 | 7fa76c0b | blueswir1 | default:
|
3621 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_lddf: need to check MMU idx %d\n", mem_idx);
|
3622 | 7fa76c0b | blueswir1 | break;
|
3623 | 7fa76c0b | blueswir1 | } |
3624 | 7fa76c0b | blueswir1 | #else
|
3625 | 41db525e | Richard Henderson | DT0 = ldfq_raw(address_mask(env, addr)); |
3626 | 7fa76c0b | blueswir1 | #endif
|
3627 | 7fa76c0b | blueswir1 | } |
3628 | 7fa76c0b | blueswir1 | |
3629 | 64a88d5d | blueswir1 | void helper_ldqf(target_ulong addr, int mem_idx) |
3630 | 7fa76c0b | blueswir1 | { |
3631 | 7fa76c0b | blueswir1 | // XXX add 128 bit load
|
3632 | 7fa76c0b | blueswir1 | CPU_QuadU u; |
3633 | 7fa76c0b | blueswir1 | |
3634 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3635 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3636 | 64a88d5d | blueswir1 | switch (mem_idx) {
|
3637 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3638 | c2bc0e38 | blueswir1 | u.ll.upper = ldq_user(addr); |
3639 | c2bc0e38 | blueswir1 | u.ll.lower = ldq_user(addr + 8);
|
3640 | 64a88d5d | blueswir1 | QT0 = u.q; |
3641 | 64a88d5d | blueswir1 | break;
|
3642 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3643 | c2bc0e38 | blueswir1 | u.ll.upper = ldq_kernel(addr); |
3644 | c2bc0e38 | blueswir1 | u.ll.lower = ldq_kernel(addr + 8);
|
3645 | 64a88d5d | blueswir1 | QT0 = u.q; |
3646 | 64a88d5d | blueswir1 | break;
|
3647 | 64a88d5d | blueswir1 | #ifdef TARGET_SPARC64
|
3648 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3649 | c2bc0e38 | blueswir1 | u.ll.upper = ldq_hypv(addr); |
3650 | c2bc0e38 | blueswir1 | u.ll.lower = ldq_hypv(addr + 8);
|
3651 | 64a88d5d | blueswir1 | QT0 = u.q; |
3652 | 64a88d5d | blueswir1 | break;
|
3653 | 64a88d5d | blueswir1 | #endif
|
3654 | 64a88d5d | blueswir1 | default:
|
3655 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
|
3656 | 64a88d5d | blueswir1 | break;
|
3657 | 64a88d5d | blueswir1 | } |
3658 | 64a88d5d | blueswir1 | #else
|
3659 | 41db525e | Richard Henderson | u.ll.upper = ldq_raw(address_mask(env, addr)); |
3660 | 41db525e | Richard Henderson | u.ll.lower = ldq_raw(address_mask(env, addr + 8));
|
3661 | 7fa76c0b | blueswir1 | QT0 = u.q; |
3662 | 64a88d5d | blueswir1 | #endif
|
3663 | 7fa76c0b | blueswir1 | } |
3664 | 7fa76c0b | blueswir1 | |
3665 | 64a88d5d | blueswir1 | void helper_stqf(target_ulong addr, int mem_idx) |
3666 | 7fa76c0b | blueswir1 | { |
3667 | 7fa76c0b | blueswir1 | // XXX add 128 bit store
|
3668 | 7fa76c0b | blueswir1 | CPU_QuadU u; |
3669 | 7fa76c0b | blueswir1 | |
3670 | c2bc0e38 | blueswir1 | helper_check_align(addr, 7);
|
3671 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
3672 | 64a88d5d | blueswir1 | switch (mem_idx) {
|
3673 | b219094a | Igor V. Kovalenko | case MMU_USER_IDX:
|
3674 | 64a88d5d | blueswir1 | u.q = QT0; |
3675 | c2bc0e38 | blueswir1 | stq_user(addr, u.ll.upper); |
3676 | c2bc0e38 | blueswir1 | stq_user(addr + 8, u.ll.lower);
|
3677 | 64a88d5d | blueswir1 | break;
|
3678 | b219094a | Igor V. Kovalenko | case MMU_KERNEL_IDX:
|
3679 | 64a88d5d | blueswir1 | u.q = QT0; |
3680 | c2bc0e38 | blueswir1 | stq_kernel(addr, u.ll.upper); |
3681 | c2bc0e38 | blueswir1 | stq_kernel(addr + 8, u.ll.lower);
|
3682 | 64a88d5d | blueswir1 | break;
|
3683 | 64a88d5d | blueswir1 | #ifdef TARGET_SPARC64
|
3684 | b219094a | Igor V. Kovalenko | case MMU_HYPV_IDX:
|
3685 | 64a88d5d | blueswir1 | u.q = QT0; |
3686 | c2bc0e38 | blueswir1 | stq_hypv(addr, u.ll.upper); |
3687 | c2bc0e38 | blueswir1 | stq_hypv(addr + 8, u.ll.lower);
|
3688 | 64a88d5d | blueswir1 | break;
|
3689 | 64a88d5d | blueswir1 | #endif
|
3690 | 64a88d5d | blueswir1 | default:
|
3691 | b219094a | Igor V. Kovalenko | DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
|
3692 | 64a88d5d | blueswir1 | break;
|
3693 | 64a88d5d | blueswir1 | } |
3694 | 64a88d5d | blueswir1 | #else
|
3695 | 7fa76c0b | blueswir1 | u.q = QT0; |
3696 | 41db525e | Richard Henderson | stq_raw(address_mask(env, addr), u.ll.upper); |
3697 | 41db525e | Richard Henderson | stq_raw(address_mask(env, addr + 8), u.ll.lower);
|
3698 | 7fa76c0b | blueswir1 | #endif
|
3699 | 64a88d5d | blueswir1 | } |
3700 | 7fa76c0b | blueswir1 | |
3701 | 3a3b925d | blueswir1 | static inline void set_fsr(void) |
3702 | e8af50a3 | bellard | { |
3703 | 7a0e1f41 | bellard | int rnd_mode;
|
3704 | bb5529bb | blueswir1 | |
3705 | e8af50a3 | bellard | switch (env->fsr & FSR_RD_MASK) {
|
3706 | e8af50a3 | bellard | case FSR_RD_NEAREST:
|
3707 | 7a0e1f41 | bellard | rnd_mode = float_round_nearest_even; |
3708 | 0f8a249a | blueswir1 | break;
|
3709 | ed910241 | bellard | default:
|
3710 | e8af50a3 | bellard | case FSR_RD_ZERO:
|
3711 | 7a0e1f41 | bellard | rnd_mode = float_round_to_zero; |
3712 | 0f8a249a | blueswir1 | break;
|
3713 | e8af50a3 | bellard | case FSR_RD_POS:
|
3714 | 7a0e1f41 | bellard | rnd_mode = float_round_up; |
3715 | 0f8a249a | blueswir1 | break;
|
3716 | e8af50a3 | bellard | case FSR_RD_NEG:
|
3717 | 7a0e1f41 | bellard | rnd_mode = float_round_down; |
3718 | 0f8a249a | blueswir1 | break;
|
3719 | e8af50a3 | bellard | } |
3720 | 7a0e1f41 | bellard | set_float_rounding_mode(rnd_mode, &env->fp_status); |
3721 | e8af50a3 | bellard | } |
3722 | e80cfcfc | bellard | |
3723 | 3a3b925d | blueswir1 | void helper_ldfsr(uint32_t new_fsr)
|
3724 | bb5529bb | blueswir1 | { |
3725 | 3a3b925d | blueswir1 | env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK); |
3726 | 3a3b925d | blueswir1 | set_fsr(); |
3727 | bb5529bb | blueswir1 | } |
3728 | bb5529bb | blueswir1 | |
3729 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
3730 | 3a3b925d | blueswir1 | void helper_ldxfsr(uint64_t new_fsr)
|
3731 | 3a3b925d | blueswir1 | { |
3732 | 3a3b925d | blueswir1 | env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK); |
3733 | 3a3b925d | blueswir1 | set_fsr(); |
3734 | 3a3b925d | blueswir1 | } |
3735 | 3a3b925d | blueswir1 | #endif
|
3736 | 3a3b925d | blueswir1 | |
3737 | bb5529bb | blueswir1 | void helper_debug(void) |
3738 | e80cfcfc | bellard | { |
3739 | e80cfcfc | bellard | env->exception_index = EXCP_DEBUG; |
3740 | 1162c041 | Blue Swirl | cpu_loop_exit(env); |
3741 | e80cfcfc | bellard | } |
3742 | af7bf89b | bellard | |
3743 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
3744 | 72a9747b | blueswir1 | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
3745 | 72a9747b | blueswir1 | handling ? */
|
3746 | 72a9747b | blueswir1 | void helper_save(void) |
3747 | 72a9747b | blueswir1 | { |
3748 | 72a9747b | blueswir1 | uint32_t cwp; |
3749 | 72a9747b | blueswir1 | |
3750 | 5a834bb4 | Blue Swirl | cwp = cwp_dec(env->cwp - 1);
|
3751 | 72a9747b | blueswir1 | if (env->wim & (1 << cwp)) { |
3752 | 72a9747b | blueswir1 | raise_exception(TT_WIN_OVF); |
3753 | 72a9747b | blueswir1 | } |
3754 | 72a9747b | blueswir1 | set_cwp(cwp); |
3755 | 72a9747b | blueswir1 | } |
3756 | 72a9747b | blueswir1 | |
3757 | 72a9747b | blueswir1 | void helper_restore(void) |
3758 | 72a9747b | blueswir1 | { |
3759 | 72a9747b | blueswir1 | uint32_t cwp; |
3760 | 72a9747b | blueswir1 | |
3761 | 5a834bb4 | Blue Swirl | cwp = cwp_inc(env->cwp + 1);
|
3762 | 72a9747b | blueswir1 | if (env->wim & (1 << cwp)) { |
3763 | 72a9747b | blueswir1 | raise_exception(TT_WIN_UNF); |
3764 | 72a9747b | blueswir1 | } |
3765 | 72a9747b | blueswir1 | set_cwp(cwp); |
3766 | 72a9747b | blueswir1 | } |
3767 | 72a9747b | blueswir1 | |
3768 | 1a2fb1c0 | blueswir1 | void helper_wrpsr(target_ulong new_psr)
|
3769 | af7bf89b | bellard | { |
3770 | 5a834bb4 | Blue Swirl | if ((new_psr & PSR_CWP) >= env->nwindows) {
|
3771 | d4218d99 | blueswir1 | raise_exception(TT_ILL_INSN); |
3772 | 5a834bb4 | Blue Swirl | } else {
|
3773 | 5a834bb4 | Blue Swirl | cpu_put_psr(env, new_psr); |
3774 | 5a834bb4 | Blue Swirl | } |
3775 | af7bf89b | bellard | } |
3776 | af7bf89b | bellard | |
3777 | 1a2fb1c0 | blueswir1 | target_ulong helper_rdpsr(void)
|
3778 | af7bf89b | bellard | { |
3779 | 5a834bb4 | Blue Swirl | return get_psr();
|
3780 | af7bf89b | bellard | } |
3781 | 3475187d | bellard | |
3782 | 3475187d | bellard | #else
|
3783 | 72a9747b | blueswir1 | /* XXX: use another pointer for %iN registers to avoid slow wrapping
|
3784 | 72a9747b | blueswir1 | handling ? */
|
3785 | 72a9747b | blueswir1 | void helper_save(void) |
3786 | 72a9747b | blueswir1 | { |
3787 | 72a9747b | blueswir1 | uint32_t cwp; |
3788 | 72a9747b | blueswir1 | |
3789 | 5a834bb4 | Blue Swirl | cwp = cwp_dec(env->cwp - 1);
|
3790 | 72a9747b | blueswir1 | if (env->cansave == 0) { |
3791 | 72a9747b | blueswir1 | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
3792 | 72a9747b | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3793 | 72a9747b | blueswir1 | ((env->wstate & 0x7) << 2))); |
3794 | 72a9747b | blueswir1 | } else {
|
3795 | 72a9747b | blueswir1 | if (env->cleanwin - env->canrestore == 0) { |
3796 | 72a9747b | blueswir1 | // XXX Clean windows without trap
|
3797 | 72a9747b | blueswir1 | raise_exception(TT_CLRWIN); |
3798 | 72a9747b | blueswir1 | } else {
|
3799 | 72a9747b | blueswir1 | env->cansave--; |
3800 | 72a9747b | blueswir1 | env->canrestore++; |
3801 | 72a9747b | blueswir1 | set_cwp(cwp); |
3802 | 72a9747b | blueswir1 | } |
3803 | 72a9747b | blueswir1 | } |
3804 | 72a9747b | blueswir1 | } |
3805 | 72a9747b | blueswir1 | |
3806 | 72a9747b | blueswir1 | void helper_restore(void) |
3807 | 72a9747b | blueswir1 | { |
3808 | 72a9747b | blueswir1 | uint32_t cwp; |
3809 | 72a9747b | blueswir1 | |
3810 | 5a834bb4 | Blue Swirl | cwp = cwp_inc(env->cwp + 1);
|
3811 | 72a9747b | blueswir1 | if (env->canrestore == 0) { |
3812 | 72a9747b | blueswir1 | raise_exception(TT_FILL | (env->otherwin != 0 ?
|
3813 | 72a9747b | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3814 | 72a9747b | blueswir1 | ((env->wstate & 0x7) << 2))); |
3815 | 72a9747b | blueswir1 | } else {
|
3816 | 72a9747b | blueswir1 | env->cansave++; |
3817 | 72a9747b | blueswir1 | env->canrestore--; |
3818 | 72a9747b | blueswir1 | set_cwp(cwp); |
3819 | 72a9747b | blueswir1 | } |
3820 | 72a9747b | blueswir1 | } |
3821 | 72a9747b | blueswir1 | |
3822 | 72a9747b | blueswir1 | void helper_flushw(void) |
3823 | 72a9747b | blueswir1 | { |
3824 | 1a14026e | blueswir1 | if (env->cansave != env->nwindows - 2) { |
3825 | 72a9747b | blueswir1 | raise_exception(TT_SPILL | (env->otherwin != 0 ?
|
3826 | 72a9747b | blueswir1 | (TT_WOTHER | ((env->wstate & 0x38) >> 1)): |
3827 | 72a9747b | blueswir1 | ((env->wstate & 0x7) << 2))); |
3828 | 72a9747b | blueswir1 | } |
3829 | 72a9747b | blueswir1 | } |
3830 | 72a9747b | blueswir1 | |
3831 | 72a9747b | blueswir1 | void helper_saved(void) |
3832 | 72a9747b | blueswir1 | { |
3833 | 72a9747b | blueswir1 | env->cansave++; |
3834 | 72a9747b | blueswir1 | if (env->otherwin == 0) |
3835 | 72a9747b | blueswir1 | env->canrestore--; |
3836 | 72a9747b | blueswir1 | else
|
3837 | 72a9747b | blueswir1 | env->otherwin--; |
3838 | 72a9747b | blueswir1 | } |
3839 | 72a9747b | blueswir1 | |
3840 | 72a9747b | blueswir1 | void helper_restored(void) |
3841 | 72a9747b | blueswir1 | { |
3842 | 72a9747b | blueswir1 | env->canrestore++; |
3843 | 1a14026e | blueswir1 | if (env->cleanwin < env->nwindows - 1) |
3844 | 72a9747b | blueswir1 | env->cleanwin++; |
3845 | 72a9747b | blueswir1 | if (env->otherwin == 0) |
3846 | 72a9747b | blueswir1 | env->cansave--; |
3847 | 72a9747b | blueswir1 | else
|
3848 | 72a9747b | blueswir1 | env->otherwin--; |
3849 | 72a9747b | blueswir1 | } |
3850 | 72a9747b | blueswir1 | |
3851 | 5a834bb4 | Blue Swirl | static target_ulong get_ccr(void) |
3852 | 5a834bb4 | Blue Swirl | { |
3853 | 5a834bb4 | Blue Swirl | target_ulong psr; |
3854 | 5a834bb4 | Blue Swirl | |
3855 | 5a834bb4 | Blue Swirl | psr = get_psr(); |
3856 | 5a834bb4 | Blue Swirl | |
3857 | 5a834bb4 | Blue Swirl | return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20); |
3858 | 5a834bb4 | Blue Swirl | } |
3859 | 5a834bb4 | Blue Swirl | |
3860 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_ccr(CPUState *env1) |
3861 | 5a834bb4 | Blue Swirl | { |
3862 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3863 | 5a834bb4 | Blue Swirl | target_ulong ret; |
3864 | 5a834bb4 | Blue Swirl | |
3865 | 5a834bb4 | Blue Swirl | saved_env = env; |
3866 | 5a834bb4 | Blue Swirl | env = env1; |
3867 | 5a834bb4 | Blue Swirl | ret = get_ccr(); |
3868 | 5a834bb4 | Blue Swirl | env = saved_env; |
3869 | 5a834bb4 | Blue Swirl | return ret;
|
3870 | 5a834bb4 | Blue Swirl | } |
3871 | 5a834bb4 | Blue Swirl | |
3872 | 5a834bb4 | Blue Swirl | static void put_ccr(target_ulong val) |
3873 | 5a834bb4 | Blue Swirl | { |
3874 | 5a834bb4 | Blue Swirl | target_ulong tmp = val; |
3875 | 5a834bb4 | Blue Swirl | |
3876 | 5a834bb4 | Blue Swirl | env->xcc = (tmp >> 4) << 20; |
3877 | 5a834bb4 | Blue Swirl | env->psr = (tmp & 0xf) << 20; |
3878 | 5a834bb4 | Blue Swirl | CC_OP = CC_OP_FLAGS; |
3879 | 5a834bb4 | Blue Swirl | } |
3880 | 5a834bb4 | Blue Swirl | |
3881 | 5a834bb4 | Blue Swirl | void cpu_put_ccr(CPUState *env1, target_ulong val)
|
3882 | 5a834bb4 | Blue Swirl | { |
3883 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3884 | 5a834bb4 | Blue Swirl | |
3885 | 5a834bb4 | Blue Swirl | saved_env = env; |
3886 | 5a834bb4 | Blue Swirl | env = env1; |
3887 | 5a834bb4 | Blue Swirl | put_ccr(val); |
3888 | 5a834bb4 | Blue Swirl | env = saved_env; |
3889 | 5a834bb4 | Blue Swirl | } |
3890 | 5a834bb4 | Blue Swirl | |
3891 | 5a834bb4 | Blue Swirl | static target_ulong get_cwp64(void) |
3892 | 5a834bb4 | Blue Swirl | { |
3893 | 5a834bb4 | Blue Swirl | return env->nwindows - 1 - env->cwp; |
3894 | 5a834bb4 | Blue Swirl | } |
3895 | 5a834bb4 | Blue Swirl | |
3896 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_cwp64(CPUState *env1) |
3897 | 5a834bb4 | Blue Swirl | { |
3898 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3899 | 5a834bb4 | Blue Swirl | target_ulong ret; |
3900 | 5a834bb4 | Blue Swirl | |
3901 | 5a834bb4 | Blue Swirl | saved_env = env; |
3902 | 5a834bb4 | Blue Swirl | env = env1; |
3903 | 5a834bb4 | Blue Swirl | ret = get_cwp64(); |
3904 | 5a834bb4 | Blue Swirl | env = saved_env; |
3905 | 5a834bb4 | Blue Swirl | return ret;
|
3906 | 5a834bb4 | Blue Swirl | } |
3907 | 5a834bb4 | Blue Swirl | |
3908 | 5a834bb4 | Blue Swirl | static void put_cwp64(int cwp) |
3909 | 5a834bb4 | Blue Swirl | { |
3910 | 5a834bb4 | Blue Swirl | if (unlikely(cwp >= env->nwindows || cwp < 0)) { |
3911 | 5a834bb4 | Blue Swirl | cwp %= env->nwindows; |
3912 | 5a834bb4 | Blue Swirl | } |
3913 | 5a834bb4 | Blue Swirl | set_cwp(env->nwindows - 1 - cwp);
|
3914 | 5a834bb4 | Blue Swirl | } |
3915 | 5a834bb4 | Blue Swirl | |
3916 | 5a834bb4 | Blue Swirl | void cpu_put_cwp64(CPUState *env1, int cwp) |
3917 | 5a834bb4 | Blue Swirl | { |
3918 | 5a834bb4 | Blue Swirl | CPUState *saved_env; |
3919 | 5a834bb4 | Blue Swirl | |
3920 | 5a834bb4 | Blue Swirl | saved_env = env; |
3921 | 5a834bb4 | Blue Swirl | env = env1; |
3922 | 5a834bb4 | Blue Swirl | put_cwp64(cwp); |
3923 | 5a834bb4 | Blue Swirl | env = saved_env; |
3924 | 5a834bb4 | Blue Swirl | } |
3925 | 5a834bb4 | Blue Swirl | |
3926 | d35527d9 | blueswir1 | target_ulong helper_rdccr(void)
|
3927 | d35527d9 | blueswir1 | { |
3928 | 5a834bb4 | Blue Swirl | return get_ccr();
|
3929 | d35527d9 | blueswir1 | } |
3930 | d35527d9 | blueswir1 | |
3931 | d35527d9 | blueswir1 | void helper_wrccr(target_ulong new_ccr)
|
3932 | d35527d9 | blueswir1 | { |
3933 | 5a834bb4 | Blue Swirl | put_ccr(new_ccr); |
3934 | d35527d9 | blueswir1 | } |
3935 | d35527d9 | blueswir1 | |
3936 | d35527d9 | blueswir1 | // CWP handling is reversed in V9, but we still use the V8 register
|
3937 | d35527d9 | blueswir1 | // order.
|
3938 | d35527d9 | blueswir1 | target_ulong helper_rdcwp(void)
|
3939 | d35527d9 | blueswir1 | { |
3940 | 5a834bb4 | Blue Swirl | return get_cwp64();
|
3941 | d35527d9 | blueswir1 | } |
3942 | d35527d9 | blueswir1 | |
3943 | d35527d9 | blueswir1 | void helper_wrcwp(target_ulong new_cwp)
|
3944 | d35527d9 | blueswir1 | { |
3945 | 5a834bb4 | Blue Swirl | put_cwp64(new_cwp); |
3946 | d35527d9 | blueswir1 | } |
3947 | 3475187d | bellard | |
3948 | 1f5063fb | blueswir1 | // This function uses non-native bit order
|
3949 | 1f5063fb | blueswir1 | #define GET_FIELD(X, FROM, TO) \
|
3950 | 1f5063fb | blueswir1 | ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) |
3951 | 1f5063fb | blueswir1 | |
3952 | 1f5063fb | blueswir1 | // This function uses the order in the manuals, i.e. bit 0 is 2^0
|
3953 | 1f5063fb | blueswir1 | #define GET_FIELD_SP(X, FROM, TO) \
|
3954 | 1f5063fb | blueswir1 | GET_FIELD(X, 63 - (TO), 63 - (FROM)) |
3955 | 1f5063fb | blueswir1 | |
3956 | 1f5063fb | blueswir1 | target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) |
3957 | 1f5063fb | blueswir1 | { |
3958 | 1f5063fb | blueswir1 | return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | |
3959 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) | |
3960 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) | |
3961 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 56, 59) << 13) | |
3962 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 35, 38) << 9) | |
3963 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 13, 16) << 5) | |
3964 | 1f5063fb | blueswir1 | (((pixel_addr >> 55) & 1) << 4) | |
3965 | 1f5063fb | blueswir1 | (GET_FIELD_SP(pixel_addr, 33, 34) << 2) | |
3966 | 1f5063fb | blueswir1 | GET_FIELD_SP(pixel_addr, 11, 12); |
3967 | 1f5063fb | blueswir1 | } |
3968 | 1f5063fb | blueswir1 | |
3969 | 1f5063fb | blueswir1 | target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) |
3970 | 1f5063fb | blueswir1 | { |
3971 | 1f5063fb | blueswir1 | uint64_t tmp; |
3972 | 1f5063fb | blueswir1 | |
3973 | 1f5063fb | blueswir1 | tmp = addr + offset; |
3974 | 1f5063fb | blueswir1 | env->gsr &= ~7ULL;
|
3975 | 1f5063fb | blueswir1 | env->gsr |= tmp & 7ULL;
|
3976 | 1f5063fb | blueswir1 | return tmp & ~7ULL; |
3977 | 1f5063fb | blueswir1 | } |
3978 | 1f5063fb | blueswir1 | |
3979 | 1a2fb1c0 | blueswir1 | target_ulong helper_popc(target_ulong val) |
3980 | 3475187d | bellard | { |
3981 | 1a2fb1c0 | blueswir1 | return ctpop64(val);
|
3982 | 3475187d | bellard | } |
3983 | 83469015 | bellard | |
3984 | d780a466 | Igor V. Kovalenko | static inline uint64_t *get_gregset(uint32_t pstate) |
3985 | 83469015 | bellard | { |
3986 | 83469015 | bellard | switch (pstate) {
|
3987 | 83469015 | bellard | default:
|
3988 | 7e8695ed | Igor V. Kovalenko | DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
|
3989 | 7e8695ed | Igor V. Kovalenko | pstate, |
3990 | 7e8695ed | Igor V. Kovalenko | (pstate & PS_IG) ? " IG" : "", |
3991 | 7e8695ed | Igor V. Kovalenko | (pstate & PS_MG) ? " MG" : "", |
3992 | 7e8695ed | Igor V. Kovalenko | (pstate & PS_AG) ? " AG" : ""); |
3993 | 7e8695ed | Igor V. Kovalenko | /* pass through to normal set of global registers */
|
3994 | 83469015 | bellard | case 0: |
3995 | 0f8a249a | blueswir1 | return env->bgregs;
|
3996 | 83469015 | bellard | case PS_AG:
|
3997 | 0f8a249a | blueswir1 | return env->agregs;
|
3998 | 83469015 | bellard | case PS_MG:
|
3999 | 0f8a249a | blueswir1 | return env->mgregs;
|
4000 | 83469015 | bellard | case PS_IG:
|
4001 | 0f8a249a | blueswir1 | return env->igregs;
|
4002 | 83469015 | bellard | } |
4003 | 83469015 | bellard | } |
4004 | 83469015 | bellard | |
4005 | d780a466 | Igor V. Kovalenko | static inline void change_pstate(uint32_t new_pstate) |
4006 | 83469015 | bellard | { |
4007 | d780a466 | Igor V. Kovalenko | uint32_t pstate_regs, new_pstate_regs; |
4008 | 83469015 | bellard | uint64_t *src, *dst; |
4009 | 83469015 | bellard | |
4010 | 5210977a | Igor Kovalenko | if (env->def->features & CPU_FEATURE_GL) {
|
4011 | 5210977a | Igor Kovalenko | // PS_AG is not implemented in this case
|
4012 | 5210977a | Igor Kovalenko | new_pstate &= ~PS_AG; |
4013 | 5210977a | Igor Kovalenko | } |
4014 | 5210977a | Igor Kovalenko | |
4015 | 83469015 | bellard | pstate_regs = env->pstate & 0xc01;
|
4016 | 83469015 | bellard | new_pstate_regs = new_pstate & 0xc01;
|
4017 | 5210977a | Igor Kovalenko | |
4018 | 83469015 | bellard | if (new_pstate_regs != pstate_regs) {
|
4019 | 7e8695ed | Igor V. Kovalenko | DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
|
4020 | 7e8695ed | Igor V. Kovalenko | pstate_regs, new_pstate_regs); |
4021 | 0f8a249a | blueswir1 | // Switch global register bank
|
4022 | 0f8a249a | blueswir1 | src = get_gregset(new_pstate_regs); |
4023 | 0f8a249a | blueswir1 | dst = get_gregset(pstate_regs); |
4024 | 0f8a249a | blueswir1 | memcpy32(dst, env->gregs); |
4025 | 0f8a249a | blueswir1 | memcpy32(env->gregs, src); |
4026 | 83469015 | bellard | } |
4027 | 7e8695ed | Igor V. Kovalenko | else {
|
4028 | 7e8695ed | Igor V. Kovalenko | DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
|
4029 | 7e8695ed | Igor V. Kovalenko | new_pstate_regs); |
4030 | 7e8695ed | Igor V. Kovalenko | } |
4031 | 83469015 | bellard | env->pstate = new_pstate; |
4032 | 83469015 | bellard | } |
4033 | 83469015 | bellard | |
4034 | 1a2fb1c0 | blueswir1 | void helper_wrpstate(target_ulong new_state)
|
4035 | 8f1f22f6 | blueswir1 | { |
4036 | 5210977a | Igor Kovalenko | change_pstate(new_state & 0xf3f);
|
4037 | 4dc28134 | Igor V. Kovalenko | |
4038 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
4039 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
4040 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
4041 | 4dc28134 | Igor V. Kovalenko | } |
4042 | 4dc28134 | Igor V. Kovalenko | #endif
|
4043 | 8f1f22f6 | blueswir1 | } |
4044 | 8f1f22f6 | blueswir1 | |
4045 | e67768d0 | Blue Swirl | void cpu_change_pstate(CPUState *env1, uint32_t new_pstate)
|
4046 | e67768d0 | Blue Swirl | { |
4047 | e67768d0 | Blue Swirl | CPUState *saved_env; |
4048 | e67768d0 | Blue Swirl | |
4049 | e67768d0 | Blue Swirl | saved_env = env; |
4050 | e67768d0 | Blue Swirl | env = env1; |
4051 | e67768d0 | Blue Swirl | change_pstate(new_pstate); |
4052 | e67768d0 | Blue Swirl | env = saved_env; |
4053 | e67768d0 | Blue Swirl | } |
4054 | e67768d0 | Blue Swirl | |
4055 | 1fae7b70 | Igor V. Kovalenko | void helper_wrpil(target_ulong new_pil)
|
4056 | 1fae7b70 | Igor V. Kovalenko | { |
4057 | 1fae7b70 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
4058 | 1fae7b70 | Igor V. Kovalenko | DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
|
4059 | 1fae7b70 | Igor V. Kovalenko | env->psrpil, (uint32_t)new_pil); |
4060 | 1fae7b70 | Igor V. Kovalenko | |
4061 | 1fae7b70 | Igor V. Kovalenko | env->psrpil = new_pil; |
4062 | 1fae7b70 | Igor V. Kovalenko | |
4063 | 1fae7b70 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
4064 | 1fae7b70 | Igor V. Kovalenko | cpu_check_irqs(env); |
4065 | 1fae7b70 | Igor V. Kovalenko | } |
4066 | 1fae7b70 | Igor V. Kovalenko | #endif
|
4067 | 1fae7b70 | Igor V. Kovalenko | } |
4068 | 1fae7b70 | Igor V. Kovalenko | |
4069 | 1a2fb1c0 | blueswir1 | void helper_done(void) |
4070 | 83469015 | bellard | { |
4071 | 8194f35a | Igor Kovalenko | trap_state* tsptr = cpu_tsptr(env); |
4072 | 8194f35a | Igor Kovalenko | |
4073 | 3723cd09 | Igor V. Kovalenko | env->pc = tsptr->tnpc; |
4074 | 8194f35a | Igor Kovalenko | env->npc = tsptr->tnpc + 4;
|
4075 | 5a834bb4 | Blue Swirl | put_ccr(tsptr->tstate >> 32);
|
4076 | 8194f35a | Igor Kovalenko | env->asi = (tsptr->tstate >> 24) & 0xff; |
4077 | 8194f35a | Igor Kovalenko | change_pstate((tsptr->tstate >> 8) & 0xf3f); |
4078 | 5a834bb4 | Blue Swirl | put_cwp64(tsptr->tstate & 0xff);
|
4079 | e6bf7d70 | blueswir1 | env->tl--; |
4080 | 4dc28134 | Igor V. Kovalenko | |
4081 | 4dc28134 | Igor V. Kovalenko | DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
|
4082 | 4dc28134 | Igor V. Kovalenko | |
4083 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
4084 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
4085 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
4086 | 4dc28134 | Igor V. Kovalenko | } |
4087 | 4dc28134 | Igor V. Kovalenko | #endif
|
4088 | 83469015 | bellard | } |
4089 | 83469015 | bellard | |
4090 | 1a2fb1c0 | blueswir1 | void helper_retry(void) |
4091 | 83469015 | bellard | { |
4092 | 8194f35a | Igor Kovalenko | trap_state* tsptr = cpu_tsptr(env); |
4093 | 8194f35a | Igor Kovalenko | |
4094 | 8194f35a | Igor Kovalenko | env->pc = tsptr->tpc; |
4095 | 8194f35a | Igor Kovalenko | env->npc = tsptr->tnpc; |
4096 | 5a834bb4 | Blue Swirl | put_ccr(tsptr->tstate >> 32);
|
4097 | 8194f35a | Igor Kovalenko | env->asi = (tsptr->tstate >> 24) & 0xff; |
4098 | 8194f35a | Igor Kovalenko | change_pstate((tsptr->tstate >> 8) & 0xf3f); |
4099 | 5a834bb4 | Blue Swirl | put_cwp64(tsptr->tstate & 0xff);
|
4100 | e6bf7d70 | blueswir1 | env->tl--; |
4101 | 4dc28134 | Igor V. Kovalenko | |
4102 | 4dc28134 | Igor V. Kovalenko | DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
|
4103 | 4dc28134 | Igor V. Kovalenko | |
4104 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
4105 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
4106 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
4107 | 4dc28134 | Igor V. Kovalenko | } |
4108 | 4dc28134 | Igor V. Kovalenko | #endif
|
4109 | 4dc28134 | Igor V. Kovalenko | } |
4110 | 4dc28134 | Igor V. Kovalenko | |
4111 | 4dc28134 | Igor V. Kovalenko | static void do_modify_softint(const char* operation, uint32_t value) |
4112 | 4dc28134 | Igor V. Kovalenko | { |
4113 | 4dc28134 | Igor V. Kovalenko | if (env->softint != value) {
|
4114 | 4dc28134 | Igor V. Kovalenko | env->softint = value; |
4115 | 4dc28134 | Igor V. Kovalenko | DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
|
4116 | 4dc28134 | Igor V. Kovalenko | #if !defined(CONFIG_USER_ONLY)
|
4117 | 4dc28134 | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
|
4118 | 4dc28134 | Igor V. Kovalenko | cpu_check_irqs(env); |
4119 | 4dc28134 | Igor V. Kovalenko | } |
4120 | 4dc28134 | Igor V. Kovalenko | #endif
|
4121 | 4dc28134 | Igor V. Kovalenko | } |
4122 | 83469015 | bellard | } |
4123 | 9d926598 | blueswir1 | |
4124 | 9d926598 | blueswir1 | void helper_set_softint(uint64_t value)
|
4125 | 9d926598 | blueswir1 | { |
4126 | 4dc28134 | Igor V. Kovalenko | do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
|
4127 | 9d926598 | blueswir1 | } |
4128 | 9d926598 | blueswir1 | |
4129 | 9d926598 | blueswir1 | void helper_clear_softint(uint64_t value)
|
4130 | 9d926598 | blueswir1 | { |
4131 | 4dc28134 | Igor V. Kovalenko | do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
|
4132 | 9d926598 | blueswir1 | } |
4133 | 9d926598 | blueswir1 | |
4134 | 9d926598 | blueswir1 | void helper_write_softint(uint64_t value)
|
4135 | 9d926598 | blueswir1 | { |
4136 | 4dc28134 | Igor V. Kovalenko | do_modify_softint("helper_write_softint", (uint32_t)value);
|
4137 | 9d926598 | blueswir1 | } |
4138 | 3475187d | bellard | #endif
|
4139 | ee5bbe38 | bellard | |
4140 | 91736d37 | blueswir1 | #ifdef TARGET_SPARC64
|
4141 | 8194f35a | Igor Kovalenko | trap_state* cpu_tsptr(CPUState* env) |
4142 | 8194f35a | Igor Kovalenko | { |
4143 | 8194f35a | Igor Kovalenko | return &env->ts[env->tl & MAXTL_MASK];
|
4144 | 8194f35a | Igor Kovalenko | } |
4145 | 91736d37 | blueswir1 | #endif
|
4146 | ee5bbe38 | bellard | |
4147 | 5fafdf24 | ths | #if !defined(CONFIG_USER_ONLY)
|
4148 | ee5bbe38 | bellard | |
4149 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4150 | d2889a3e | blueswir1 | void *retaddr);
|
4151 | d2889a3e | blueswir1 | |
4152 | ee5bbe38 | bellard | #define MMUSUFFIX _mmu
|
4153 | d2889a3e | blueswir1 | #define ALIGNED_ONLY
|
4154 | ee5bbe38 | bellard | |
4155 | ee5bbe38 | bellard | #define SHIFT 0 |
4156 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4157 | ee5bbe38 | bellard | |
4158 | ee5bbe38 | bellard | #define SHIFT 1 |
4159 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4160 | ee5bbe38 | bellard | |
4161 | ee5bbe38 | bellard | #define SHIFT 2 |
4162 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4163 | ee5bbe38 | bellard | |
4164 | ee5bbe38 | bellard | #define SHIFT 3 |
4165 | ee5bbe38 | bellard | #include "softmmu_template.h" |
4166 | ee5bbe38 | bellard | |
4167 | c2bc0e38 | blueswir1 | /* XXX: make it generic ? */
|
4168 | c2bc0e38 | blueswir1 | static void cpu_restore_state2(void *retaddr) |
4169 | c2bc0e38 | blueswir1 | { |
4170 | c2bc0e38 | blueswir1 | TranslationBlock *tb; |
4171 | c2bc0e38 | blueswir1 | unsigned long pc; |
4172 | c2bc0e38 | blueswir1 | |
4173 | c2bc0e38 | blueswir1 | if (retaddr) {
|
4174 | c2bc0e38 | blueswir1 | /* now we have a real cpu fault */
|
4175 | c2bc0e38 | blueswir1 | pc = (unsigned long)retaddr; |
4176 | c2bc0e38 | blueswir1 | tb = tb_find_pc(pc); |
4177 | c2bc0e38 | blueswir1 | if (tb) {
|
4178 | c2bc0e38 | blueswir1 | /* the PC is inside the translated code. It means that we have
|
4179 | c2bc0e38 | blueswir1 | a virtual CPU fault */
|
4180 | 618ba8e6 | Stefan Weil | cpu_restore_state(tb, env, pc); |
4181 | c2bc0e38 | blueswir1 | } |
4182 | c2bc0e38 | blueswir1 | } |
4183 | c2bc0e38 | blueswir1 | } |
4184 | c2bc0e38 | blueswir1 | |
4185 | d2889a3e | blueswir1 | static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
4186 | d2889a3e | blueswir1 | void *retaddr)
|
4187 | d2889a3e | blueswir1 | { |
4188 | 94554550 | blueswir1 | #ifdef DEBUG_UNALIGNED
|
4189 | c2bc0e38 | blueswir1 | printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx |
4190 | c2bc0e38 | blueswir1 | "\n", addr, env->pc);
|
4191 | 94554550 | blueswir1 | #endif
|
4192 | c2bc0e38 | blueswir1 | cpu_restore_state2(retaddr); |
4193 | 94554550 | blueswir1 | raise_exception(TT_UNALIGNED); |
4194 | d2889a3e | blueswir1 | } |
4195 | ee5bbe38 | bellard | |
4196 | ee5bbe38 | bellard | /* try to fill the TLB and return an exception if error. If retaddr is
|
4197 | ee5bbe38 | bellard | NULL, it means that the function was called in C code (i.e. not
|
4198 | ee5bbe38 | bellard | from generated code or from helper.c) */
|
4199 | ee5bbe38 | bellard | /* XXX: fix it to restore all registers */
|
4200 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
4201 | ee5bbe38 | bellard | { |
4202 | ee5bbe38 | bellard | int ret;
|
4203 | ee5bbe38 | bellard | CPUState *saved_env; |
4204 | ee5bbe38 | bellard | |
4205 | ee5bbe38 | bellard | /* XXX: hack to restore env in all cases, even if not called from
|
4206 | ee5bbe38 | bellard | generated code */
|
4207 | ee5bbe38 | bellard | saved_env = env; |
4208 | ee5bbe38 | bellard | env = cpu_single_env; |
4209 | ee5bbe38 | bellard | |
4210 | 6ebbf390 | j_mayer | ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
4211 | ee5bbe38 | bellard | if (ret) {
|
4212 | c2bc0e38 | blueswir1 | cpu_restore_state2(retaddr); |
4213 | 1162c041 | Blue Swirl | cpu_loop_exit(env); |
4214 | ee5bbe38 | bellard | } |
4215 | ee5bbe38 | bellard | env = saved_env; |
4216 | ee5bbe38 | bellard | } |
4217 | ee5bbe38 | bellard | |
4218 | 3c7b48b7 | Paul Brook | #endif /* !CONFIG_USER_ONLY */ |
4219 | 6c36d3fa | blueswir1 | |
4220 | 6c36d3fa | blueswir1 | #ifndef TARGET_SPARC64
|
4221 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
4222 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
4223 | e18231a3 | blueswir1 | int is_asi, int size) |
4224 | 6c36d3fa | blueswir1 | { |
4225 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
4226 | 576c2cdc | Artyom Tarasenko | int fault_type;
|
4227 | 6c36d3fa | blueswir1 | |
4228 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
|
4229 | 6c36d3fa | blueswir1 | generated code */
|
4230 | 6c36d3fa | blueswir1 | saved_env = env; |
4231 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
4232 | 8543e2cf | blueswir1 | #ifdef DEBUG_UNASSIGNED
|
4233 | 8543e2cf | blueswir1 | if (is_asi)
|
4234 | e18231a3 | blueswir1 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
4235 | 77f193da | blueswir1 | " asi 0x%02x from " TARGET_FMT_lx "\n", |
4236 | e18231a3 | blueswir1 | is_exec ? "exec" : is_write ? "write" : "read", size, |
4237 | e18231a3 | blueswir1 | size == 1 ? "" : "s", addr, is_asi, env->pc); |
4238 | 8543e2cf | blueswir1 | else
|
4239 | e18231a3 | blueswir1 | printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
|
4240 | e18231a3 | blueswir1 | " from " TARGET_FMT_lx "\n", |
4241 | e18231a3 | blueswir1 | is_exec ? "exec" : is_write ? "write" : "read", size, |
4242 | e18231a3 | blueswir1 | size == 1 ? "" : "s", addr, env->pc); |
4243 | 8543e2cf | blueswir1 | #endif
|
4244 | 576c2cdc | Artyom Tarasenko | /* Don't overwrite translation and access faults */
|
4245 | 576c2cdc | Artyom Tarasenko | fault_type = (env->mmuregs[3] & 0x1c) >> 2; |
4246 | 576c2cdc | Artyom Tarasenko | if ((fault_type > 4) || (fault_type == 0)) { |
4247 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] = 0; /* Fault status register */ |
4248 | 576c2cdc | Artyom Tarasenko | if (is_asi)
|
4249 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 16; |
4250 | 576c2cdc | Artyom Tarasenko | if (env->psrs)
|
4251 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 5; |
4252 | 576c2cdc | Artyom Tarasenko | if (is_exec)
|
4253 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 6; |
4254 | 576c2cdc | Artyom Tarasenko | if (is_write)
|
4255 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1 << 7; |
4256 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= (5 << 2) | 2; |
4257 | 576c2cdc | Artyom Tarasenko | /* SuperSPARC will never place instruction fault addresses in the FAR */
|
4258 | 576c2cdc | Artyom Tarasenko | if (!is_exec) {
|
4259 | 576c2cdc | Artyom Tarasenko | env->mmuregs[4] = addr; /* Fault address register */ |
4260 | 576c2cdc | Artyom Tarasenko | } |
4261 | 576c2cdc | Artyom Tarasenko | } |
4262 | 576c2cdc | Artyom Tarasenko | /* overflow (same type fault was not read before another fault) */
|
4263 | 576c2cdc | Artyom Tarasenko | if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { |
4264 | 576c2cdc | Artyom Tarasenko | env->mmuregs[3] |= 1; |
4265 | 576c2cdc | Artyom Tarasenko | } |
4266 | 576c2cdc | Artyom Tarasenko | |
4267 | 6c36d3fa | blueswir1 | if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
4268 | 1b2e93c1 | blueswir1 | if (is_exec)
|
4269 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
4270 | 1b2e93c1 | blueswir1 | else
|
4271 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
4272 | 6c36d3fa | blueswir1 | } |
4273 | 576c2cdc | Artyom Tarasenko | |
4274 | 576c2cdc | Artyom Tarasenko | /* flush neverland mappings created during no-fault mode,
|
4275 | 576c2cdc | Artyom Tarasenko | so the sequential MMU faults report proper fault types */
|
4276 | 576c2cdc | Artyom Tarasenko | if (env->mmuregs[0] & MMU_NF) { |
4277 | 576c2cdc | Artyom Tarasenko | tlb_flush(env, 1);
|
4278 | 576c2cdc | Artyom Tarasenko | } |
4279 | 15e7c451 | Artyom Tarasenko | |
4280 | 15e7c451 | Artyom Tarasenko | env = saved_env; |
4281 | 6c36d3fa | blueswir1 | } |
4282 | 3c7b48b7 | Paul Brook | #endif
|
4283 | 3c7b48b7 | Paul Brook | #else
|
4284 | 3c7b48b7 | Paul Brook | #if defined(CONFIG_USER_ONLY)
|
4285 | 3c7b48b7 | Paul Brook | static void do_unassigned_access(target_ulong addr, int is_write, int is_exec, |
4286 | 3c7b48b7 | Paul Brook | int is_asi, int size) |
4287 | 6c36d3fa | blueswir1 | #else
|
4288 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
4289 | e18231a3 | blueswir1 | int is_asi, int size) |
4290 | 3c7b48b7 | Paul Brook | #endif
|
4291 | 6c36d3fa | blueswir1 | { |
4292 | 6c36d3fa | blueswir1 | CPUState *saved_env; |
4293 | 6c36d3fa | blueswir1 | |
4294 | 6c36d3fa | blueswir1 | /* XXX: hack to restore env in all cases, even if not called from
|
4295 | 6c36d3fa | blueswir1 | generated code */
|
4296 | 6c36d3fa | blueswir1 | saved_env = env; |
4297 | 6c36d3fa | blueswir1 | env = cpu_single_env; |
4298 | dffbe217 | Igor V. Kovalenko | |
4299 | dffbe217 | Igor V. Kovalenko | #ifdef DEBUG_UNASSIGNED
|
4300 | 77f193da | blueswir1 | printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx |
4301 | 77f193da | blueswir1 | "\n", addr, env->pc);
|
4302 | 6c36d3fa | blueswir1 | #endif
|
4303 | dffbe217 | Igor V. Kovalenko | |
4304 | 1b2e93c1 | blueswir1 | if (is_exec)
|
4305 | 1b2e93c1 | blueswir1 | raise_exception(TT_CODE_ACCESS); |
4306 | 1b2e93c1 | blueswir1 | else
|
4307 | 1b2e93c1 | blueswir1 | raise_exception(TT_DATA_ACCESS); |
4308 | dffbe217 | Igor V. Kovalenko | |
4309 | dffbe217 | Igor V. Kovalenko | env = saved_env; |
4310 | 6c36d3fa | blueswir1 | } |
4311 | 6c36d3fa | blueswir1 | #endif
|
4312 | 20c9f095 | blueswir1 | |
4313 | 3c7b48b7 | Paul Brook | |
4314 | f4b1a842 | blueswir1 | #ifdef TARGET_SPARC64
|
4315 | f4b1a842 | blueswir1 | void helper_tick_set_count(void *opaque, uint64_t count) |
4316 | f4b1a842 | blueswir1 | { |
4317 | f4b1a842 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4318 | f4b1a842 | blueswir1 | cpu_tick_set_count(opaque, count); |
4319 | f4b1a842 | blueswir1 | #endif
|
4320 | f4b1a842 | blueswir1 | } |
4321 | f4b1a842 | blueswir1 | |
4322 | f4b1a842 | blueswir1 | uint64_t helper_tick_get_count(void *opaque)
|
4323 | f4b1a842 | blueswir1 | { |
4324 | f4b1a842 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4325 | f4b1a842 | blueswir1 | return cpu_tick_get_count(opaque);
|
4326 | f4b1a842 | blueswir1 | #else
|
4327 | f4b1a842 | blueswir1 | return 0; |
4328 | f4b1a842 | blueswir1 | #endif
|
4329 | f4b1a842 | blueswir1 | } |
4330 | f4b1a842 | blueswir1 | |
4331 | f4b1a842 | blueswir1 | void helper_tick_set_limit(void *opaque, uint64_t limit) |
4332 | f4b1a842 | blueswir1 | { |
4333 | f4b1a842 | blueswir1 | #if !defined(CONFIG_USER_ONLY)
|
4334 | f4b1a842 | blueswir1 | cpu_tick_set_limit(opaque, limit); |
4335 | f4b1a842 | blueswir1 | #endif
|
4336 | f4b1a842 | blueswir1 | } |
4337 | f4b1a842 | blueswir1 | #endif |