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# Date Author Comment
ff9d2afa 10/04/2012 04:54 pm David Gibson

pseries: Remove XICS irq type enum type

Currently the XICS interrupt controller emulation uses a custom enum to
specify whether a given interrupt is level-sensitive or message-triggered.
This enum makes life awkward for saving the state, and isn't particularly...
3fe719f4 10/04/2012 04:54 pm David Gibson

pseries: Fix semantics of RTAS int-on, int-off and set-xive functions

Currently the ibm,int-on and ibm,int-off RTAS functions are implemented as
no-ops. This is because when implemented as specified in PAPR they caused
Linux (which calls both int-on/off and set-xive) to end up with interrupts...
256b408a 10/04/2012 04:54 pm David Gibson

pseries: Fix XICS reset

The XICS interrupt controller used on the pseries machine currently has no
reset handler. We can get away with this under some circumstances, but
it's not correct, and can cause failures if the XICS happens to be in the
wrong state at the time of reset....
98ca8c02 10/04/2012 04:54 pm David Gibson

pseries: Remove C bitfields from xics code

The XICS interrupt controller emulation uses some C bitfield variables in
its internal state structure. This makes like awkward for saving the state
because we don't have easy VMSTATE helpers for bitfields.

This patch removes the bitfields, instead using explicit bit masking in a...
a307d594 08/15/2012 08:43 pm Alexey Kardashevskiy

pseries: Rework irq assignment to avoid carrying qemu_irqs around

Currently, the interfaces in the pseries machine code for assignment
and setup of interrupts pass around qemu_irq objects. That was done
in an attempt not to be too closely linked to the specific XICS...
d07fee7e 03/15/2012 02:12 pm David Gibson

pseries: Add support for level interrupts to XICS

The pseries "xics" interrupt controller, like most interrupt
controllers can support both message (i.e. edge sensitive) interrupts
and level sensitive interrupts, but it needs to know which are which.

When I implemented the xics emulation for qemu, the only devices we...
e2684c0b 03/14/2012 11:20 pm Andreas Färber

ppc hw/: Don't use CPUState

Scripted conversion:
for file in hw/ppc*.[hc] hw/mpc8544_guts.c hw/spapr*.[hc] hw/virtex_ml507.c hw/xics.c; do
sed -i "s/CPUState/CPUPPCState/g" $file
done

Signed-off-by: Andreas Färber <>
Acked-by: Anthony Liguori <>
cc67b9c8 10/06/2011 10:48 am David Gibson

pseries: Bugfixes for interrupt numbering in XICS code

The implementation of the XICS interrupt controller contains several
(difficult to trigger) bugs due to the fact that we were not 100%
consistent with which irq numbering we used. In most places, global...
43b26fc8 09/21/2011 12:49 pm Jan Kiszka

Drop unneeded pthread.h inclusions

Signed-off-by: Jan Kiszka <>
Signed-off-by: Stefan Hajnoczi <>
7267c094 08/21/2011 07:01 am Anthony Liguori

Use glib memory allocation and free functions

qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <>
c7a5c0c9 04/08/2011 12:32 pm David Gibson

pseries: Abolish envs array

Currently the pseries machine init code builds up an array, envs, of
CPUState pointers for all the cpus in the system. This is kind of
pointless, given the generic code already has a perfectly good linked list
of the cpus.

In addition, there are a number of places which assume that the cpu's...
b5cec4c5 04/01/2011 07:34 pm David Gibson

Implement the PAPR (pSeries) virtualized interrupt controller (xics)

PAPR defines an interrupt control architecture which is logically divided
into ICS (Interrupt Control Presentation, each unit is responsible for
presenting interrupts to a particular "interrupt server", i.e. CPU) and...