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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation for qemu: main translation routines.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 90dc8812 | Scott Wood | * Copyright (C) 2011 Freescale Semiconductor, Inc.
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6 | 79aceca5 | bellard | *
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7 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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8 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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10 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 79aceca5 | bellard | *
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12 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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13 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 79aceca5 | bellard | * Lesser General Public License for more details.
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16 | 79aceca5 | bellard | *
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17 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 79aceca5 | bellard | */
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20 | c6a1c22b | bellard | |
21 | 79aceca5 | bellard | #include "cpu.h" |
22 | 76cad711 | Paolo Bonzini | #include "disas/disas.h" |
23 | 57fec1fe | bellard | #include "tcg-op.h" |
24 | 1de7afc9 | Paolo Bonzini | #include "qemu/host-utils.h" |
25 | 79aceca5 | bellard | |
26 | a7812ae4 | pbrook | #include "helper.h" |
27 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
28 | a7812ae4 | pbrook | #include "helper.h" |
29 | a7812ae4 | pbrook | |
30 | 8cbcb4fa | aurel32 | #define CPU_SINGLE_STEP 0x1 |
31 | 8cbcb4fa | aurel32 | #define CPU_BRANCH_STEP 0x2 |
32 | 8cbcb4fa | aurel32 | #define GDBSTUB_SINGLE_STEP 0x4 |
33 | 8cbcb4fa | aurel32 | |
34 | a750fc0b | j_mayer | /* Include definitions for instructions classes and implementations flags */
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35 | 9fddaa0c | bellard | //#define PPC_DEBUG_DISAS
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36 | 76a66253 | j_mayer | //#define DO_PPC_STATISTICS
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37 | 79aceca5 | bellard | |
38 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_DISAS
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39 | 93fcfe39 | aliguori | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
40 | d12d51d5 | aliguori | #else
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41 | d12d51d5 | aliguori | # define LOG_DISAS(...) do { } while (0) |
42 | d12d51d5 | aliguori | #endif
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43 | a750fc0b | j_mayer | /*****************************************************************************/
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44 | a750fc0b | j_mayer | /* Code translation helpers */
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45 | c53be334 | bellard | |
46 | f78fb44e | aurel32 | /* global register indexes */
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47 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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48 | 1d542695 | aurel32 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
49 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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50 | 1d542695 | aurel32 | + 10*4 + 22*5 /* SPE GPRh */ |
51 | f78fb44e | aurel32 | #endif
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52 | a5e26afa | aurel32 | + 10*4 + 22*5 /* FPR */ |
53 | 47e4661c | aurel32 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
54 | 472b24ce | Tom Musta | + 10*5 + 22*6 /* VSR */ |
55 | 47e4661c | aurel32 | + 8*5 /* CRF */]; |
56 | f78fb44e | aurel32 | static TCGv cpu_gpr[32]; |
57 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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58 | f78fb44e | aurel32 | static TCGv cpu_gprh[32]; |
59 | f78fb44e | aurel32 | #endif
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60 | a7812ae4 | pbrook | static TCGv_i64 cpu_fpr[32]; |
61 | a7812ae4 | pbrook | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; |
62 | 472b24ce | Tom Musta | static TCGv_i64 cpu_vsr[32]; |
63 | a7812ae4 | pbrook | static TCGv_i32 cpu_crf[8]; |
64 | bd568f18 | aurel32 | static TCGv cpu_nip;
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65 | 6527f6ea | aurel32 | static TCGv cpu_msr;
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66 | cfdcd37a | aurel32 | static TCGv cpu_ctr;
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67 | cfdcd37a | aurel32 | static TCGv cpu_lr;
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68 | 697ab892 | David Gibson | #if defined(TARGET_PPC64)
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69 | 697ab892 | David Gibson | static TCGv cpu_cfar;
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70 | 697ab892 | David Gibson | #endif
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71 | da91a00f | Richard Henderson | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
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72 | cf360a32 | aurel32 | static TCGv cpu_reserve;
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73 | 30304420 | David Gibson | static TCGv cpu_fpscr;
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74 | a7859e89 | aurel32 | static TCGv_i32 cpu_access_type;
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75 | f78fb44e | aurel32 | |
76 | 022c62cb | Paolo Bonzini | #include "exec/gen-icount.h" |
77 | 2e70f6ef | pbrook | |
78 | 2e70f6ef | pbrook | void ppc_translate_init(void) |
79 | 2e70f6ef | pbrook | { |
80 | f78fb44e | aurel32 | int i;
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81 | f78fb44e | aurel32 | char* p;
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82 | 2dc766da | blueswir1 | size_t cpu_reg_names_size; |
83 | b2437bf2 | pbrook | static int done_init = 0; |
84 | f78fb44e | aurel32 | |
85 | 2e70f6ef | pbrook | if (done_init)
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86 | 2e70f6ef | pbrook | return;
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87 | f78fb44e | aurel32 | |
88 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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89 | a7812ae4 | pbrook | |
90 | f78fb44e | aurel32 | p = cpu_reg_names; |
91 | 2dc766da | blueswir1 | cpu_reg_names_size = sizeof(cpu_reg_names);
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92 | 47e4661c | aurel32 | |
93 | 47e4661c | aurel32 | for (i = 0; i < 8; i++) { |
94 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "crf%d", i);
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95 | a7812ae4 | pbrook | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
96 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, crf[i]), p); |
97 | 47e4661c | aurel32 | p += 5;
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98 | 2dc766da | blueswir1 | cpu_reg_names_size -= 5;
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99 | 47e4661c | aurel32 | } |
100 | 47e4661c | aurel32 | |
101 | f78fb44e | aurel32 | for (i = 0; i < 32; i++) { |
102 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%d", i);
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103 | a7812ae4 | pbrook | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
104 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, gpr[i]), p); |
105 | f78fb44e | aurel32 | p += (i < 10) ? 3 : 4; |
106 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
107 | f78fb44e | aurel32 | #if !defined(TARGET_PPC64)
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108 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "r%dH", i);
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109 | a7812ae4 | pbrook | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
110 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, gprh[i]), p); |
111 | f78fb44e | aurel32 | p += (i < 10) ? 4 : 5; |
112 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
113 | f78fb44e | aurel32 | #endif
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114 | 1d542695 | aurel32 | |
115 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "fp%d", i);
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116 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
117 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, fpr[i]), p); |
118 | ec1ac72d | aurel32 | p += (i < 10) ? 4 : 5; |
119 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
120 | a5e26afa | aurel32 | |
121 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dH", i);
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122 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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123 | fe1e5c53 | aurel32 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
124 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, avr[i].u64[0]), p);
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125 | fe1e5c53 | aurel32 | #else
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126 | a7812ae4 | pbrook | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
127 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, avr[i].u64[1]), p);
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128 | fe1e5c53 | aurel32 | #endif
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129 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
130 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
131 | ec1ac72d | aurel32 | |
132 | 2dc766da | blueswir1 | snprintf(p, cpu_reg_names_size, "avr%dL", i);
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133 | e2542fe2 | Juan Quintela | #ifdef HOST_WORDS_BIGENDIAN
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134 | fe1e5c53 | aurel32 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
135 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, avr[i].u64[1]), p);
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136 | fe1e5c53 | aurel32 | #else
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137 | a7812ae4 | pbrook | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
138 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, avr[i].u64[0]), p);
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139 | fe1e5c53 | aurel32 | #endif
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140 | 1d542695 | aurel32 | p += (i < 10) ? 6 : 7; |
141 | 2dc766da | blueswir1 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
142 | 472b24ce | Tom Musta | snprintf(p, cpu_reg_names_size, "vsr%d", i);
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143 | 472b24ce | Tom Musta | cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
144 | 472b24ce | Tom Musta | offsetof(CPUPPCState, vsr[i]), p); |
145 | 472b24ce | Tom Musta | p += (i < 10) ? 5 : 6; |
146 | 472b24ce | Tom Musta | cpu_reg_names_size -= (i < 10) ? 5 : 6; |
147 | f78fb44e | aurel32 | } |
148 | f10dc08e | aurel32 | |
149 | a7812ae4 | pbrook | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
150 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, nip), "nip");
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151 | bd568f18 | aurel32 | |
152 | 6527f6ea | aurel32 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
153 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, msr), "msr");
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154 | 6527f6ea | aurel32 | |
155 | a7812ae4 | pbrook | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
156 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, ctr), "ctr");
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157 | cfdcd37a | aurel32 | |
158 | a7812ae4 | pbrook | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
159 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, lr), "lr");
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160 | cfdcd37a | aurel32 | |
161 | 697ab892 | David Gibson | #if defined(TARGET_PPC64)
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162 | 697ab892 | David Gibson | cpu_cfar = tcg_global_mem_new(TCG_AREG0, |
163 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, cfar), "cfar");
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164 | 697ab892 | David Gibson | #endif
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165 | 697ab892 | David Gibson | |
166 | a7812ae4 | pbrook | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
167 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, xer), "xer");
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168 | da91a00f | Richard Henderson | cpu_so = tcg_global_mem_new(TCG_AREG0, |
169 | da91a00f | Richard Henderson | offsetof(CPUPPCState, so), "SO");
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170 | da91a00f | Richard Henderson | cpu_ov = tcg_global_mem_new(TCG_AREG0, |
171 | da91a00f | Richard Henderson | offsetof(CPUPPCState, ov), "OV");
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172 | da91a00f | Richard Henderson | cpu_ca = tcg_global_mem_new(TCG_AREG0, |
173 | da91a00f | Richard Henderson | offsetof(CPUPPCState, ca), "CA");
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174 | 3d7b417e | aurel32 | |
175 | cf360a32 | aurel32 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
176 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, reserve_addr), |
177 | 18b21a2f | Nathan Froyd | "reserve_addr");
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178 | cf360a32 | aurel32 | |
179 | 30304420 | David Gibson | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
180 | 30304420 | David Gibson | offsetof(CPUPPCState, fpscr), "fpscr");
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181 | e1571908 | aurel32 | |
182 | a7859e89 | aurel32 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
183 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, access_type), "access_type");
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184 | a7859e89 | aurel32 | |
185 | 2e70f6ef | pbrook | done_init = 1;
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186 | 2e70f6ef | pbrook | } |
187 | 2e70f6ef | pbrook | |
188 | 79aceca5 | bellard | /* internal defines */
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189 | 79aceca5 | bellard | typedef struct DisasContext { |
190 | 79aceca5 | bellard | struct TranslationBlock *tb;
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191 | 0fa85d43 | bellard | target_ulong nip; |
192 | 79aceca5 | bellard | uint32_t opcode; |
193 | 9a64fbe4 | bellard | uint32_t exception; |
194 | 3cc62370 | bellard | /* Routine used to access memory */
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195 | 3cc62370 | bellard | int mem_idx;
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196 | 76db3ba4 | aurel32 | int access_type;
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197 | 3cc62370 | bellard | /* Translation flags */
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198 | 76db3ba4 | aurel32 | int le_mode;
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199 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
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200 | d9bce9d9 | j_mayer | int sf_mode;
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201 | 697ab892 | David Gibson | int has_cfar;
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202 | d9bce9d9 | j_mayer | #endif
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203 | 3cc62370 | bellard | int fpu_enabled;
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204 | a9d9eb8f | j_mayer | int altivec_enabled;
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205 | 1f29871c | Tom Musta | int vsx_enabled;
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206 | 0487d6a8 | j_mayer | int spe_enabled;
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207 | c227f099 | Anthony Liguori | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
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208 | ea4e754f | bellard | int singlestep_enabled;
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209 | 7d08d856 | Aurelien Jarno | uint64_t insns_flags; |
210 | 7d08d856 | Aurelien Jarno | uint64_t insns_flags2; |
211 | 79aceca5 | bellard | } DisasContext; |
212 | 79aceca5 | bellard | |
213 | 79482e5a | Richard Henderson | /* True when active word size < size of target_long. */
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214 | 79482e5a | Richard Henderson | #ifdef TARGET_PPC64
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215 | 79482e5a | Richard Henderson | # define NARROW_MODE(C) (!(C)->sf_mode)
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216 | 79482e5a | Richard Henderson | #else
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217 | 79482e5a | Richard Henderson | # define NARROW_MODE(C) 0 |
218 | 79482e5a | Richard Henderson | #endif
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219 | 79482e5a | Richard Henderson | |
220 | c227f099 | Anthony Liguori | struct opc_handler_t {
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221 | 70560da7 | Fabien Chouteau | /* invalid bits for instruction 1 (Rc(opcode) == 0) */
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222 | 70560da7 | Fabien Chouteau | uint32_t inval1; |
223 | 70560da7 | Fabien Chouteau | /* invalid bits for instruction 2 (Rc(opcode) == 1) */
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224 | 70560da7 | Fabien Chouteau | uint32_t inval2; |
225 | 9a64fbe4 | bellard | /* instruction type */
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226 | 0487d6a8 | j_mayer | uint64_t type; |
227 | a5858d7a | Alexander Graf | /* extended instruction type */
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228 | a5858d7a | Alexander Graf | uint64_t type2; |
229 | 79aceca5 | bellard | /* handler */
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230 | 79aceca5 | bellard | void (*handler)(DisasContext *ctx);
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231 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
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232 | b55266b5 | blueswir1 | const char *oname; |
233 | a750fc0b | j_mayer | #endif
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234 | a750fc0b | j_mayer | #if defined(DO_PPC_STATISTICS)
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235 | 76a66253 | j_mayer | uint64_t count; |
236 | 76a66253 | j_mayer | #endif
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237 | 3fc6c082 | bellard | }; |
238 | 79aceca5 | bellard | |
239 | 636aa200 | Blue Swirl | static inline void gen_reset_fpstatus(void) |
240 | 7c58044c | j_mayer | { |
241 | 8e703949 | Blue Swirl | gen_helper_reset_fpstatus(cpu_env); |
242 | 7c58044c | j_mayer | } |
243 | 7c58044c | j_mayer | |
244 | 636aa200 | Blue Swirl | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
245 | 7c58044c | j_mayer | { |
246 | 0f2f39c2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
247 | af12906f | aurel32 | |
248 | 7c58044c | j_mayer | if (set_fprf != 0) { |
249 | 7c58044c | j_mayer | /* This case might be optimized later */
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250 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 1);
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251 | 8e703949 | Blue Swirl | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
252 | a7812ae4 | pbrook | if (unlikely(set_rc)) {
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253 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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254 | a7812ae4 | pbrook | } |
255 | 8e703949 | Blue Swirl | gen_helper_float_check_status(cpu_env); |
256 | 7c58044c | j_mayer | } else if (unlikely(set_rc)) { |
257 | 7c58044c | j_mayer | /* We always need to compute fpcc */
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258 | 0f2f39c2 | aurel32 | tcg_gen_movi_i32(t0, 0);
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259 | 8e703949 | Blue Swirl | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
260 | 0f2f39c2 | aurel32 | tcg_gen_mov_i32(cpu_crf[1], t0);
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261 | 7c58044c | j_mayer | } |
262 | af12906f | aurel32 | |
263 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
264 | 7c58044c | j_mayer | } |
265 | 7c58044c | j_mayer | |
266 | 636aa200 | Blue Swirl | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
267 | a7859e89 | aurel32 | { |
268 | 76db3ba4 | aurel32 | if (ctx->access_type != access_type) {
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269 | 76db3ba4 | aurel32 | tcg_gen_movi_i32(cpu_access_type, access_type); |
270 | 76db3ba4 | aurel32 | ctx->access_type = access_type; |
271 | 76db3ba4 | aurel32 | } |
272 | a7859e89 | aurel32 | } |
273 | a7859e89 | aurel32 | |
274 | 636aa200 | Blue Swirl | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
275 | d9bce9d9 | j_mayer | { |
276 | e0c8f9ce | Richard Henderson | if (NARROW_MODE(ctx)) {
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277 | e0c8f9ce | Richard Henderson | nip = (uint32_t)nip; |
278 | e0c8f9ce | Richard Henderson | } |
279 | e0c8f9ce | Richard Henderson | tcg_gen_movi_tl(cpu_nip, nip); |
280 | d9bce9d9 | j_mayer | } |
281 | d9bce9d9 | j_mayer | |
282 | 636aa200 | Blue Swirl | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
283 | e06fcd75 | aurel32 | { |
284 | e06fcd75 | aurel32 | TCGv_i32 t0, t1; |
285 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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286 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
287 | e06fcd75 | aurel32 | } |
288 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
289 | e06fcd75 | aurel32 | t1 = tcg_const_i32(error); |
290 | e5f17ac6 | Blue Swirl | gen_helper_raise_exception_err(cpu_env, t0, t1); |
291 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
292 | e06fcd75 | aurel32 | tcg_temp_free_i32(t1); |
293 | e06fcd75 | aurel32 | ctx->exception = (excp); |
294 | e06fcd75 | aurel32 | } |
295 | e1833e1f | j_mayer | |
296 | 636aa200 | Blue Swirl | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
297 | e06fcd75 | aurel32 | { |
298 | e06fcd75 | aurel32 | TCGv_i32 t0; |
299 | e06fcd75 | aurel32 | if (ctx->exception == POWERPC_EXCP_NONE) {
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300 | e06fcd75 | aurel32 | gen_update_nip(ctx, ctx->nip); |
301 | e06fcd75 | aurel32 | } |
302 | e06fcd75 | aurel32 | t0 = tcg_const_i32(excp); |
303 | e5f17ac6 | Blue Swirl | gen_helper_raise_exception(cpu_env, t0); |
304 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
305 | e06fcd75 | aurel32 | ctx->exception = (excp); |
306 | e06fcd75 | aurel32 | } |
307 | e1833e1f | j_mayer | |
308 | 636aa200 | Blue Swirl | static inline void gen_debug_exception(DisasContext *ctx) |
309 | e06fcd75 | aurel32 | { |
310 | e06fcd75 | aurel32 | TCGv_i32 t0; |
311 | 5518f3a6 | blueswir1 | |
312 | ee2b3994 | Sebastian Bauer | if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
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313 | ee2b3994 | Sebastian Bauer | (ctx->exception != POWERPC_EXCP_SYNC)) { |
314 | 5518f3a6 | blueswir1 | gen_update_nip(ctx, ctx->nip); |
315 | ee2b3994 | Sebastian Bauer | } |
316 | e06fcd75 | aurel32 | t0 = tcg_const_i32(EXCP_DEBUG); |
317 | e5f17ac6 | Blue Swirl | gen_helper_raise_exception(cpu_env, t0); |
318 | e06fcd75 | aurel32 | tcg_temp_free_i32(t0); |
319 | e06fcd75 | aurel32 | } |
320 | 9a64fbe4 | bellard | |
321 | 636aa200 | Blue Swirl | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
322 | e06fcd75 | aurel32 | { |
323 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); |
324 | e06fcd75 | aurel32 | } |
325 | a9d9eb8f | j_mayer | |
326 | f24e5695 | bellard | /* Stop translation */
|
327 | 636aa200 | Blue Swirl | static inline void gen_stop_exception(DisasContext *ctx) |
328 | 3fc6c082 | bellard | { |
329 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip); |
330 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_STOP; |
331 | 3fc6c082 | bellard | } |
332 | 3fc6c082 | bellard | |
333 | f24e5695 | bellard | /* No need to update nip here, as execution flow will change */
|
334 | 636aa200 | Blue Swirl | static inline void gen_sync_exception(DisasContext *ctx) |
335 | 2be0071f | bellard | { |
336 | e1833e1f | j_mayer | ctx->exception = POWERPC_EXCP_SYNC; |
337 | 2be0071f | bellard | } |
338 | 2be0071f | bellard | |
339 | 79aceca5 | bellard | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
|
340 | a5858d7a | Alexander Graf | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
341 | a5858d7a | Alexander Graf | |
342 | a5858d7a | Alexander Graf | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
|
343 | a5858d7a | Alexander Graf | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) |
344 | 79aceca5 | bellard | |
345 | c7697e1f | j_mayer | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
|
346 | a5858d7a | Alexander Graf | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
347 | a5858d7a | Alexander Graf | |
348 | a5858d7a | Alexander Graf | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
|
349 | a5858d7a | Alexander Graf | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) |
350 | c7697e1f | j_mayer | |
351 | c227f099 | Anthony Liguori | typedef struct opcode_t { |
352 | 79aceca5 | bellard | unsigned char opc1, opc2, opc3; |
353 | 1235fc06 | ths | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
354 | 18fba28c | bellard | unsigned char pad[5]; |
355 | 18fba28c | bellard | #else
|
356 | 18fba28c | bellard | unsigned char pad[1]; |
357 | 18fba28c | bellard | #endif
|
358 | c227f099 | Anthony Liguori | opc_handler_t handler; |
359 | b55266b5 | blueswir1 | const char *oname; |
360 | c227f099 | Anthony Liguori | } opcode_t; |
361 | 79aceca5 | bellard | |
362 | a750fc0b | j_mayer | /*****************************************************************************/
|
363 | 79aceca5 | bellard | /*** Instruction decoding ***/
|
364 | 79aceca5 | bellard | #define EXTRACT_HELPER(name, shift, nb) \
|
365 | 636aa200 | Blue Swirl | static inline uint32_t name(uint32_t opcode) \ |
366 | 79aceca5 | bellard | { \ |
367 | 79aceca5 | bellard | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ |
368 | 79aceca5 | bellard | } |
369 | 79aceca5 | bellard | |
370 | 79aceca5 | bellard | #define EXTRACT_SHELPER(name, shift, nb) \
|
371 | 636aa200 | Blue Swirl | static inline int32_t name(uint32_t opcode) \ |
372 | 79aceca5 | bellard | { \ |
373 | 18fba28c | bellard | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
374 | 79aceca5 | bellard | } |
375 | 79aceca5 | bellard | |
376 | f9fc6d81 | Tom Musta | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
|
377 | f9fc6d81 | Tom Musta | static inline uint32_t name(uint32_t opcode) \ |
378 | f9fc6d81 | Tom Musta | { \ |
379 | f9fc6d81 | Tom Musta | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ |
380 | f9fc6d81 | Tom Musta | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ |
381 | f9fc6d81 | Tom Musta | } |
382 | 79aceca5 | bellard | /* Opcode part 1 */
|
383 | 79aceca5 | bellard | EXTRACT_HELPER(opc1, 26, 6); |
384 | 79aceca5 | bellard | /* Opcode part 2 */
|
385 | 79aceca5 | bellard | EXTRACT_HELPER(opc2, 1, 5); |
386 | 79aceca5 | bellard | /* Opcode part 3 */
|
387 | 79aceca5 | bellard | EXTRACT_HELPER(opc3, 6, 5); |
388 | 79aceca5 | bellard | /* Update Cr0 flags */
|
389 | 79aceca5 | bellard | EXTRACT_HELPER(Rc, 0, 1); |
390 | 79aceca5 | bellard | /* Destination */
|
391 | 79aceca5 | bellard | EXTRACT_HELPER(rD, 21, 5); |
392 | 79aceca5 | bellard | /* Source */
|
393 | 79aceca5 | bellard | EXTRACT_HELPER(rS, 21, 5); |
394 | 79aceca5 | bellard | /* First operand */
|
395 | 79aceca5 | bellard | EXTRACT_HELPER(rA, 16, 5); |
396 | 79aceca5 | bellard | /* Second operand */
|
397 | 79aceca5 | bellard | EXTRACT_HELPER(rB, 11, 5); |
398 | 79aceca5 | bellard | /* Third operand */
|
399 | 79aceca5 | bellard | EXTRACT_HELPER(rC, 6, 5); |
400 | 79aceca5 | bellard | /*** Get CRn ***/
|
401 | 79aceca5 | bellard | EXTRACT_HELPER(crfD, 23, 3); |
402 | 79aceca5 | bellard | EXTRACT_HELPER(crfS, 18, 3); |
403 | 79aceca5 | bellard | EXTRACT_HELPER(crbD, 21, 5); |
404 | 79aceca5 | bellard | EXTRACT_HELPER(crbA, 16, 5); |
405 | 79aceca5 | bellard | EXTRACT_HELPER(crbB, 11, 5); |
406 | 79aceca5 | bellard | /* SPR / TBL */
|
407 | 3fc6c082 | bellard | EXTRACT_HELPER(_SPR, 11, 10); |
408 | 636aa200 | Blue Swirl | static inline uint32_t SPR(uint32_t opcode) |
409 | 3fc6c082 | bellard | { |
410 | 3fc6c082 | bellard | uint32_t sprn = _SPR(opcode); |
411 | 3fc6c082 | bellard | |
412 | 3fc6c082 | bellard | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
413 | 3fc6c082 | bellard | } |
414 | 79aceca5 | bellard | /*** Get constants ***/
|
415 | 79aceca5 | bellard | EXTRACT_HELPER(IMM, 12, 8); |
416 | 79aceca5 | bellard | /* 16 bits signed immediate value */
|
417 | 79aceca5 | bellard | EXTRACT_SHELPER(SIMM, 0, 16); |
418 | 79aceca5 | bellard | /* 16 bits unsigned immediate value */
|
419 | 79aceca5 | bellard | EXTRACT_HELPER(UIMM, 0, 16); |
420 | 21d21583 | aurel32 | /* 5 bits signed immediate value */
|
421 | 21d21583 | aurel32 | EXTRACT_HELPER(SIMM5, 16, 5); |
422 | 27a4edb3 | aurel32 | /* 5 bits signed immediate value */
|
423 | 27a4edb3 | aurel32 | EXTRACT_HELPER(UIMM5, 16, 5); |
424 | 79aceca5 | bellard | /* Bit count */
|
425 | 79aceca5 | bellard | EXTRACT_HELPER(NB, 11, 5); |
426 | 79aceca5 | bellard | /* Shift count */
|
427 | 79aceca5 | bellard | EXTRACT_HELPER(SH, 11, 5); |
428 | cd633b10 | aurel32 | /* Vector shift count */
|
429 | cd633b10 | aurel32 | EXTRACT_HELPER(VSH, 6, 4); |
430 | 79aceca5 | bellard | /* Mask start */
|
431 | 79aceca5 | bellard | EXTRACT_HELPER(MB, 6, 5); |
432 | 79aceca5 | bellard | /* Mask end */
|
433 | 79aceca5 | bellard | EXTRACT_HELPER(ME, 1, 5); |
434 | fb0eaffc | bellard | /* Trap operand */
|
435 | fb0eaffc | bellard | EXTRACT_HELPER(TO, 21, 5); |
436 | 79aceca5 | bellard | |
437 | 79aceca5 | bellard | EXTRACT_HELPER(CRM, 12, 8); |
438 | 79aceca5 | bellard | EXTRACT_HELPER(SR, 16, 4); |
439 | 7d08d856 | Aurelien Jarno | |
440 | 7d08d856 | Aurelien Jarno | /* mtfsf/mtfsfi */
|
441 | 779f6590 | Aurelien Jarno | EXTRACT_HELPER(FPBF, 23, 3); |
442 | e4bb997e | aurel32 | EXTRACT_HELPER(FPIMM, 12, 4); |
443 | 779f6590 | Aurelien Jarno | EXTRACT_HELPER(FPL, 25, 1); |
444 | 7d08d856 | Aurelien Jarno | EXTRACT_HELPER(FPFLM, 17, 8); |
445 | 7d08d856 | Aurelien Jarno | EXTRACT_HELPER(FPW, 16, 1); |
446 | fb0eaffc | bellard | |
447 | 79aceca5 | bellard | /*** Jump target decoding ***/
|
448 | 79aceca5 | bellard | /* Displacement */
|
449 | 79aceca5 | bellard | EXTRACT_SHELPER(d, 0, 16); |
450 | 79aceca5 | bellard | /* Immediate address */
|
451 | 636aa200 | Blue Swirl | static inline target_ulong LI(uint32_t opcode) |
452 | 79aceca5 | bellard | { |
453 | 79aceca5 | bellard | return (opcode >> 0) & 0x03FFFFFC; |
454 | 79aceca5 | bellard | } |
455 | 79aceca5 | bellard | |
456 | 636aa200 | Blue Swirl | static inline uint32_t BD(uint32_t opcode) |
457 | 79aceca5 | bellard | { |
458 | 79aceca5 | bellard | return (opcode >> 0) & 0xFFFC; |
459 | 79aceca5 | bellard | } |
460 | 79aceca5 | bellard | |
461 | 79aceca5 | bellard | EXTRACT_HELPER(BO, 21, 5); |
462 | 79aceca5 | bellard | EXTRACT_HELPER(BI, 16, 5); |
463 | 79aceca5 | bellard | /* Absolute/relative address */
|
464 | 79aceca5 | bellard | EXTRACT_HELPER(AA, 1, 1); |
465 | 79aceca5 | bellard | /* Link */
|
466 | 79aceca5 | bellard | EXTRACT_HELPER(LK, 0, 1); |
467 | 79aceca5 | bellard | |
468 | 79aceca5 | bellard | /* Create a mask between <start> and <end> bits */
|
469 | 636aa200 | Blue Swirl | static inline target_ulong MASK(uint32_t start, uint32_t end) |
470 | 79aceca5 | bellard | { |
471 | 76a66253 | j_mayer | target_ulong ret; |
472 | 79aceca5 | bellard | |
473 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
474 | 76a66253 | j_mayer | if (likely(start == 0)) { |
475 | 6f2d8978 | j_mayer | ret = UINT64_MAX << (63 - end);
|
476 | 76a66253 | j_mayer | } else if (likely(end == 63)) { |
477 | 6f2d8978 | j_mayer | ret = UINT64_MAX >> start; |
478 | 76a66253 | j_mayer | } |
479 | 76a66253 | j_mayer | #else
|
480 | 76a66253 | j_mayer | if (likely(start == 0)) { |
481 | 6f2d8978 | j_mayer | ret = UINT32_MAX << (31 - end);
|
482 | 76a66253 | j_mayer | } else if (likely(end == 31)) { |
483 | 6f2d8978 | j_mayer | ret = UINT32_MAX >> start; |
484 | 76a66253 | j_mayer | } |
485 | 76a66253 | j_mayer | #endif
|
486 | 76a66253 | j_mayer | else {
|
487 | 76a66253 | j_mayer | ret = (((target_ulong)(-1ULL)) >> (start)) ^
|
488 | 76a66253 | j_mayer | (((target_ulong)(-1ULL) >> (end)) >> 1); |
489 | 76a66253 | j_mayer | if (unlikely(start > end))
|
490 | 76a66253 | j_mayer | return ~ret;
|
491 | 76a66253 | j_mayer | } |
492 | 79aceca5 | bellard | |
493 | 79aceca5 | bellard | return ret;
|
494 | 79aceca5 | bellard | } |
495 | 79aceca5 | bellard | |
496 | f9fc6d81 | Tom Musta | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
497 | f9fc6d81 | Tom Musta | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); |
498 | f9fc6d81 | Tom Musta | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); |
499 | f9fc6d81 | Tom Musta | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); |
500 | 551e3ef7 | Tom Musta | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
501 | f9fc6d81 | Tom Musta | EXTRACT_HELPER(DM, 8, 2); |
502 | 76c15fe0 | Tom Musta | EXTRACT_HELPER(UIM, 16, 2); |
503 | acc42968 | Tom Musta | EXTRACT_HELPER(SHW, 8, 2); |
504 | a750fc0b | j_mayer | /*****************************************************************************/
|
505 | a750fc0b | j_mayer | /* PowerPC instructions table */
|
506 | 933dc6eb | bellard | |
507 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
508 | a5858d7a | Alexander Graf | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
|
509 | 5c55ff99 | Blue Swirl | { \ |
510 | 79aceca5 | bellard | .opc1 = op1, \ |
511 | 79aceca5 | bellard | .opc2 = op2, \ |
512 | 79aceca5 | bellard | .opc3 = op3, \ |
513 | 18fba28c | bellard | .pad = { 0, }, \
|
514 | 79aceca5 | bellard | .handler = { \ |
515 | 70560da7 | Fabien Chouteau | .inval1 = invl, \ |
516 | 70560da7 | Fabien Chouteau | .type = _typ, \ |
517 | 70560da7 | Fabien Chouteau | .type2 = _typ2, \ |
518 | 70560da7 | Fabien Chouteau | .handler = &gen_##name, \ |
519 | 70560da7 | Fabien Chouteau | .oname = stringify(name), \ |
520 | 70560da7 | Fabien Chouteau | }, \ |
521 | 70560da7 | Fabien Chouteau | .oname = stringify(name), \ |
522 | 70560da7 | Fabien Chouteau | } |
523 | 70560da7 | Fabien Chouteau | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
|
524 | 70560da7 | Fabien Chouteau | { \ |
525 | 70560da7 | Fabien Chouteau | .opc1 = op1, \ |
526 | 70560da7 | Fabien Chouteau | .opc2 = op2, \ |
527 | 70560da7 | Fabien Chouteau | .opc3 = op3, \ |
528 | 70560da7 | Fabien Chouteau | .pad = { 0, }, \
|
529 | 70560da7 | Fabien Chouteau | .handler = { \ |
530 | 70560da7 | Fabien Chouteau | .inval1 = invl1, \ |
531 | 70560da7 | Fabien Chouteau | .inval2 = invl2, \ |
532 | 9a64fbe4 | bellard | .type = _typ, \ |
533 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
534 | 79aceca5 | bellard | .handler = &gen_##name, \ |
535 | 76a66253 | j_mayer | .oname = stringify(name), \ |
536 | 79aceca5 | bellard | }, \ |
537 | 3fc6c082 | bellard | .oname = stringify(name), \ |
538 | 79aceca5 | bellard | } |
539 | a5858d7a | Alexander Graf | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
|
540 | 5c55ff99 | Blue Swirl | { \ |
541 | c7697e1f | j_mayer | .opc1 = op1, \ |
542 | c7697e1f | j_mayer | .opc2 = op2, \ |
543 | c7697e1f | j_mayer | .opc3 = op3, \ |
544 | c7697e1f | j_mayer | .pad = { 0, }, \
|
545 | c7697e1f | j_mayer | .handler = { \ |
546 | 70560da7 | Fabien Chouteau | .inval1 = invl, \ |
547 | c7697e1f | j_mayer | .type = _typ, \ |
548 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
549 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
550 | c7697e1f | j_mayer | .oname = onam, \ |
551 | c7697e1f | j_mayer | }, \ |
552 | c7697e1f | j_mayer | .oname = onam, \ |
553 | c7697e1f | j_mayer | } |
554 | 76a66253 | j_mayer | #else
|
555 | a5858d7a | Alexander Graf | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
|
556 | 5c55ff99 | Blue Swirl | { \ |
557 | c7697e1f | j_mayer | .opc1 = op1, \ |
558 | c7697e1f | j_mayer | .opc2 = op2, \ |
559 | c7697e1f | j_mayer | .opc3 = op3, \ |
560 | c7697e1f | j_mayer | .pad = { 0, }, \
|
561 | c7697e1f | j_mayer | .handler = { \ |
562 | 70560da7 | Fabien Chouteau | .inval1 = invl, \ |
563 | 70560da7 | Fabien Chouteau | .type = _typ, \ |
564 | 70560da7 | Fabien Chouteau | .type2 = _typ2, \ |
565 | 70560da7 | Fabien Chouteau | .handler = &gen_##name, \ |
566 | 70560da7 | Fabien Chouteau | }, \ |
567 | 70560da7 | Fabien Chouteau | .oname = stringify(name), \ |
568 | 70560da7 | Fabien Chouteau | } |
569 | 70560da7 | Fabien Chouteau | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
|
570 | 70560da7 | Fabien Chouteau | { \ |
571 | 70560da7 | Fabien Chouteau | .opc1 = op1, \ |
572 | 70560da7 | Fabien Chouteau | .opc2 = op2, \ |
573 | 70560da7 | Fabien Chouteau | .opc3 = op3, \ |
574 | 70560da7 | Fabien Chouteau | .pad = { 0, }, \
|
575 | 70560da7 | Fabien Chouteau | .handler = { \ |
576 | 70560da7 | Fabien Chouteau | .inval1 = invl1, \ |
577 | 70560da7 | Fabien Chouteau | .inval2 = invl2, \ |
578 | c7697e1f | j_mayer | .type = _typ, \ |
579 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
580 | c7697e1f | j_mayer | .handler = &gen_##name, \ |
581 | 5c55ff99 | Blue Swirl | }, \ |
582 | 5c55ff99 | Blue Swirl | .oname = stringify(name), \ |
583 | 5c55ff99 | Blue Swirl | } |
584 | a5858d7a | Alexander Graf | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
|
585 | 5c55ff99 | Blue Swirl | { \ |
586 | 5c55ff99 | Blue Swirl | .opc1 = op1, \ |
587 | 5c55ff99 | Blue Swirl | .opc2 = op2, \ |
588 | 5c55ff99 | Blue Swirl | .opc3 = op3, \ |
589 | 5c55ff99 | Blue Swirl | .pad = { 0, }, \
|
590 | 5c55ff99 | Blue Swirl | .handler = { \ |
591 | 70560da7 | Fabien Chouteau | .inval1 = invl, \ |
592 | 5c55ff99 | Blue Swirl | .type = _typ, \ |
593 | a5858d7a | Alexander Graf | .type2 = _typ2, \ |
594 | 5c55ff99 | Blue Swirl | .handler = &gen_##name, \ |
595 | 5c55ff99 | Blue Swirl | }, \ |
596 | 5c55ff99 | Blue Swirl | .oname = onam, \ |
597 | 5c55ff99 | Blue Swirl | } |
598 | 5c55ff99 | Blue Swirl | #endif
|
599 | 2e610050 | Blue Swirl | |
600 | 5c55ff99 | Blue Swirl | /* SPR load/store helpers */
|
601 | 636aa200 | Blue Swirl | static inline void gen_load_spr(TCGv t, int reg) |
602 | 5c55ff99 | Blue Swirl | { |
603 | 1328c2bf | Andreas Färber | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
604 | 5c55ff99 | Blue Swirl | } |
605 | 2e610050 | Blue Swirl | |
606 | 636aa200 | Blue Swirl | static inline void gen_store_spr(int reg, TCGv t) |
607 | 5c55ff99 | Blue Swirl | { |
608 | 1328c2bf | Andreas Färber | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
609 | 5c55ff99 | Blue Swirl | } |
610 | 2e610050 | Blue Swirl | |
611 | 54623277 | Blue Swirl | /* Invalid instruction */
|
612 | 99e300ef | Blue Swirl | static void gen_invalid(DisasContext *ctx) |
613 | 9a64fbe4 | bellard | { |
614 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
615 | 9a64fbe4 | bellard | } |
616 | 9a64fbe4 | bellard | |
617 | c227f099 | Anthony Liguori | static opc_handler_t invalid_handler = {
|
618 | 70560da7 | Fabien Chouteau | .inval1 = 0xFFFFFFFF,
|
619 | 70560da7 | Fabien Chouteau | .inval2 = 0xFFFFFFFF,
|
620 | 9a64fbe4 | bellard | .type = PPC_NONE, |
621 | a5858d7a | Alexander Graf | .type2 = PPC_NONE, |
622 | 79aceca5 | bellard | .handler = gen_invalid, |
623 | 79aceca5 | bellard | }; |
624 | 79aceca5 | bellard | |
625 | e1571908 | aurel32 | /*** Integer comparison ***/
|
626 | e1571908 | aurel32 | |
627 | 636aa200 | Blue Swirl | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
628 | e1571908 | aurel32 | { |
629 | 2fdcb629 | Richard Henderson | TCGv t0 = tcg_temp_new(); |
630 | 2fdcb629 | Richard Henderson | TCGv_i32 t1 = tcg_temp_new_i32(); |
631 | e1571908 | aurel32 | |
632 | da91a00f | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
633 | e1571908 | aurel32 | |
634 | 2fdcb629 | Richard Henderson | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
635 | 2fdcb629 | Richard Henderson | tcg_gen_trunc_tl_i32(t1, t0); |
636 | 2fdcb629 | Richard Henderson | tcg_gen_shli_i32(t1, t1, CRF_LT); |
637 | 2fdcb629 | Richard Henderson | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); |
638 | 2fdcb629 | Richard Henderson | |
639 | 2fdcb629 | Richard Henderson | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); |
640 | 2fdcb629 | Richard Henderson | tcg_gen_trunc_tl_i32(t1, t0); |
641 | 2fdcb629 | Richard Henderson | tcg_gen_shli_i32(t1, t1, CRF_GT); |
642 | 2fdcb629 | Richard Henderson | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); |
643 | 2fdcb629 | Richard Henderson | |
644 | 2fdcb629 | Richard Henderson | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); |
645 | 2fdcb629 | Richard Henderson | tcg_gen_trunc_tl_i32(t1, t0); |
646 | 2fdcb629 | Richard Henderson | tcg_gen_shli_i32(t1, t1, CRF_EQ); |
647 | 2fdcb629 | Richard Henderson | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); |
648 | 2fdcb629 | Richard Henderson | |
649 | 2fdcb629 | Richard Henderson | tcg_temp_free(t0); |
650 | 2fdcb629 | Richard Henderson | tcg_temp_free_i32(t1); |
651 | e1571908 | aurel32 | } |
652 | e1571908 | aurel32 | |
653 | 636aa200 | Blue Swirl | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
654 | e1571908 | aurel32 | { |
655 | 2fdcb629 | Richard Henderson | TCGv t0 = tcg_const_tl(arg1); |
656 | ea363694 | aurel32 | gen_op_cmp(arg0, t0, s, crf); |
657 | ea363694 | aurel32 | tcg_temp_free(t0); |
658 | e1571908 | aurel32 | } |
659 | e1571908 | aurel32 | |
660 | 636aa200 | Blue Swirl | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
661 | e1571908 | aurel32 | { |
662 | ea363694 | aurel32 | TCGv t0, t1; |
663 | 2fdcb629 | Richard Henderson | t0 = tcg_temp_new(); |
664 | 2fdcb629 | Richard Henderson | t1 = tcg_temp_new(); |
665 | e1571908 | aurel32 | if (s) {
|
666 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t0, arg0); |
667 | ea363694 | aurel32 | tcg_gen_ext32s_tl(t1, arg1); |
668 | e1571908 | aurel32 | } else {
|
669 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t0, arg0); |
670 | ea363694 | aurel32 | tcg_gen_ext32u_tl(t1, arg1); |
671 | e1571908 | aurel32 | } |
672 | ea363694 | aurel32 | gen_op_cmp(t0, t1, s, crf); |
673 | ea363694 | aurel32 | tcg_temp_free(t1); |
674 | ea363694 | aurel32 | tcg_temp_free(t0); |
675 | e1571908 | aurel32 | } |
676 | e1571908 | aurel32 | |
677 | 636aa200 | Blue Swirl | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
678 | e1571908 | aurel32 | { |
679 | 2fdcb629 | Richard Henderson | TCGv t0 = tcg_const_tl(arg1); |
680 | ea363694 | aurel32 | gen_op_cmp32(arg0, t0, s, crf); |
681 | ea363694 | aurel32 | tcg_temp_free(t0); |
682 | e1571908 | aurel32 | } |
683 | e1571908 | aurel32 | |
684 | 636aa200 | Blue Swirl | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
685 | e1571908 | aurel32 | { |
686 | 02765534 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
687 | e1571908 | aurel32 | gen_op_cmpi32(reg, 0, 1, 0); |
688 | 02765534 | Richard Henderson | } else {
|
689 | e1571908 | aurel32 | gen_op_cmpi(reg, 0, 1, 0); |
690 | 02765534 | Richard Henderson | } |
691 | e1571908 | aurel32 | } |
692 | e1571908 | aurel32 | |
693 | e1571908 | aurel32 | /* cmp */
|
694 | 99e300ef | Blue Swirl | static void gen_cmp(DisasContext *ctx) |
695 | e1571908 | aurel32 | { |
696 | 36f48d9c | Alexander Graf | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
697 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
698 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
699 | 36f48d9c | Alexander Graf | } else {
|
700 | 36f48d9c | Alexander Graf | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
701 | 36f48d9c | Alexander Graf | 1, crfD(ctx->opcode));
|
702 | 02765534 | Richard Henderson | } |
703 | e1571908 | aurel32 | } |
704 | e1571908 | aurel32 | |
705 | e1571908 | aurel32 | /* cmpi */
|
706 | 99e300ef | Blue Swirl | static void gen_cmpi(DisasContext *ctx) |
707 | e1571908 | aurel32 | { |
708 | 36f48d9c | Alexander Graf | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
709 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
710 | e1571908 | aurel32 | 1, crfD(ctx->opcode));
|
711 | 36f48d9c | Alexander Graf | } else {
|
712 | 36f48d9c | Alexander Graf | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
713 | 36f48d9c | Alexander Graf | 1, crfD(ctx->opcode));
|
714 | 02765534 | Richard Henderson | } |
715 | e1571908 | aurel32 | } |
716 | e1571908 | aurel32 | |
717 | e1571908 | aurel32 | /* cmpl */
|
718 | 99e300ef | Blue Swirl | static void gen_cmpl(DisasContext *ctx) |
719 | e1571908 | aurel32 | { |
720 | 36f48d9c | Alexander Graf | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
721 | e1571908 | aurel32 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
722 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
723 | 36f48d9c | Alexander Graf | } else {
|
724 | 36f48d9c | Alexander Graf | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
725 | 36f48d9c | Alexander Graf | 0, crfD(ctx->opcode));
|
726 | 02765534 | Richard Henderson | } |
727 | e1571908 | aurel32 | } |
728 | e1571908 | aurel32 | |
729 | e1571908 | aurel32 | /* cmpli */
|
730 | 99e300ef | Blue Swirl | static void gen_cmpli(DisasContext *ctx) |
731 | e1571908 | aurel32 | { |
732 | 36f48d9c | Alexander Graf | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
733 | e1571908 | aurel32 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
734 | e1571908 | aurel32 | 0, crfD(ctx->opcode));
|
735 | 36f48d9c | Alexander Graf | } else {
|
736 | 36f48d9c | Alexander Graf | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
737 | 36f48d9c | Alexander Graf | 0, crfD(ctx->opcode));
|
738 | 02765534 | Richard Henderson | } |
739 | e1571908 | aurel32 | } |
740 | e1571908 | aurel32 | |
741 | e1571908 | aurel32 | /* isel (PowerPC 2.03 specification) */
|
742 | 99e300ef | Blue Swirl | static void gen_isel(DisasContext *ctx) |
743 | e1571908 | aurel32 | { |
744 | e1571908 | aurel32 | int l1, l2;
|
745 | e1571908 | aurel32 | uint32_t bi = rC(ctx->opcode); |
746 | e1571908 | aurel32 | uint32_t mask; |
747 | a7812ae4 | pbrook | TCGv_i32 t0; |
748 | e1571908 | aurel32 | |
749 | e1571908 | aurel32 | l1 = gen_new_label(); |
750 | e1571908 | aurel32 | l2 = gen_new_label(); |
751 | e1571908 | aurel32 | |
752 | e1571908 | aurel32 | mask = 1 << (3 - (bi & 0x03)); |
753 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); |
754 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
|
755 | fea0c503 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
756 | e1571908 | aurel32 | if (rA(ctx->opcode) == 0) |
757 | e1571908 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
758 | e1571908 | aurel32 | else
|
759 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
760 | e1571908 | aurel32 | tcg_gen_br(l2); |
761 | e1571908 | aurel32 | gen_set_label(l1); |
762 | e1571908 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
763 | e1571908 | aurel32 | gen_set_label(l2); |
764 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
765 | e1571908 | aurel32 | } |
766 | e1571908 | aurel32 | |
767 | fcfda20f | Aurelien Jarno | /* cmpb: PowerPC 2.05 specification */
|
768 | fcfda20f | Aurelien Jarno | static void gen_cmpb(DisasContext *ctx) |
769 | fcfda20f | Aurelien Jarno | { |
770 | fcfda20f | Aurelien Jarno | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
771 | fcfda20f | Aurelien Jarno | cpu_gpr[rB(ctx->opcode)]); |
772 | fcfda20f | Aurelien Jarno | } |
773 | fcfda20f | Aurelien Jarno | |
774 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
775 | 79aceca5 | bellard | |
776 | 636aa200 | Blue Swirl | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
777 | 636aa200 | Blue Swirl | TCGv arg1, TCGv arg2, int sub)
|
778 | 74637406 | aurel32 | { |
779 | ffe30937 | Richard Henderson | TCGv t0 = tcg_temp_new(); |
780 | 79aceca5 | bellard | |
781 | 8e7a6db9 | Aurelien Jarno | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
782 | 74637406 | aurel32 | tcg_gen_xor_tl(t0, arg1, arg2); |
783 | ffe30937 | Richard Henderson | if (sub) {
|
784 | ffe30937 | Richard Henderson | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); |
785 | ffe30937 | Richard Henderson | } else {
|
786 | ffe30937 | Richard Henderson | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); |
787 | ffe30937 | Richard Henderson | } |
788 | ffe30937 | Richard Henderson | tcg_temp_free(t0); |
789 | 02765534 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
790 | ffe30937 | Richard Henderson | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
791 | ffe30937 | Richard Henderson | } |
792 | ffe30937 | Richard Henderson | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
|
793 | ffe30937 | Richard Henderson | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
794 | 79aceca5 | bellard | } |
795 | 79aceca5 | bellard | |
796 | 74637406 | aurel32 | /* Common add function */
|
797 | 636aa200 | Blue Swirl | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
798 | b5a73f8d | Richard Henderson | TCGv arg2, bool add_ca, bool compute_ca, |
799 | b5a73f8d | Richard Henderson | bool compute_ov, bool compute_rc0) |
800 | 74637406 | aurel32 | { |
801 | b5a73f8d | Richard Henderson | TCGv t0 = ret; |
802 | d9bce9d9 | j_mayer | |
803 | 752d634e | Richard Henderson | if (compute_ca || compute_ov) {
|
804 | 146de60d | Richard Henderson | t0 = tcg_temp_new(); |
805 | 74637406 | aurel32 | } |
806 | 79aceca5 | bellard | |
807 | da91a00f | Richard Henderson | if (compute_ca) {
|
808 | 79482e5a | Richard Henderson | if (NARROW_MODE(ctx)) {
|
809 | 752d634e | Richard Henderson | /* Caution: a non-obvious corner case of the spec is that we
|
810 | 752d634e | Richard Henderson | must produce the *entire* 64-bit addition, but produce the
|
811 | 752d634e | Richard Henderson | carry into bit 32. */
|
812 | 79482e5a | Richard Henderson | TCGv t1 = tcg_temp_new(); |
813 | 752d634e | Richard Henderson | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
|
814 | 752d634e | Richard Henderson | tcg_gen_add_tl(t0, arg1, arg2); |
815 | 79482e5a | Richard Henderson | if (add_ca) {
|
816 | 79482e5a | Richard Henderson | tcg_gen_add_tl(t0, t0, cpu_ca); |
817 | 79482e5a | Richard Henderson | } |
818 | 752d634e | Richard Henderson | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
|
819 | 752d634e | Richard Henderson | tcg_temp_free(t1); |
820 | 752d634e | Richard Henderson | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ |
821 | 752d634e | Richard Henderson | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
|
822 | b5a73f8d | Richard Henderson | } else {
|
823 | 79482e5a | Richard Henderson | TCGv zero = tcg_const_tl(0);
|
824 | 79482e5a | Richard Henderson | if (add_ca) {
|
825 | 79482e5a | Richard Henderson | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); |
826 | 79482e5a | Richard Henderson | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); |
827 | 79482e5a | Richard Henderson | } else {
|
828 | 79482e5a | Richard Henderson | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); |
829 | 79482e5a | Richard Henderson | } |
830 | 79482e5a | Richard Henderson | tcg_temp_free(zero); |
831 | b5a73f8d | Richard Henderson | } |
832 | b5a73f8d | Richard Henderson | } else {
|
833 | b5a73f8d | Richard Henderson | tcg_gen_add_tl(t0, arg1, arg2); |
834 | b5a73f8d | Richard Henderson | if (add_ca) {
|
835 | b5a73f8d | Richard Henderson | tcg_gen_add_tl(t0, t0, cpu_ca); |
836 | b5a73f8d | Richard Henderson | } |
837 | da91a00f | Richard Henderson | } |
838 | 79aceca5 | bellard | |
839 | 74637406 | aurel32 | if (compute_ov) {
|
840 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
|
841 | 74637406 | aurel32 | } |
842 | b5a73f8d | Richard Henderson | if (unlikely(compute_rc0)) {
|
843 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
844 | b5a73f8d | Richard Henderson | } |
845 | 74637406 | aurel32 | |
846 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
847 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
848 | 74637406 | aurel32 | tcg_temp_free(t0); |
849 | 74637406 | aurel32 | } |
850 | 39dd32ee | aurel32 | } |
851 | 74637406 | aurel32 | /* Add functions with two operands */
|
852 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
853 | b5a73f8d | Richard Henderson | static void glue(gen_, name)(DisasContext *ctx) \ |
854 | 74637406 | aurel32 | { \ |
855 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
856 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
857 | b5a73f8d | Richard Henderson | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
858 | 74637406 | aurel32 | } |
859 | 74637406 | aurel32 | /* Add functions with one operand and one immediate */
|
860 | 74637406 | aurel32 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
861 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
862 | b5a73f8d | Richard Henderson | static void glue(gen_, name)(DisasContext *ctx) \ |
863 | 74637406 | aurel32 | { \ |
864 | b5a73f8d | Richard Henderson | TCGv t0 = tcg_const_tl(const_val); \ |
865 | 74637406 | aurel32 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
866 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
867 | b5a73f8d | Richard Henderson | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
868 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
869 | 74637406 | aurel32 | } |
870 | 74637406 | aurel32 | |
871 | 74637406 | aurel32 | /* add add. addo addo. */
|
872 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
873 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
874 | 74637406 | aurel32 | /* addc addc. addco addco. */
|
875 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
876 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
877 | 74637406 | aurel32 | /* adde adde. addeo addeo. */
|
878 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
879 | 74637406 | aurel32 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
880 | 74637406 | aurel32 | /* addme addme. addmeo addmeo. */
|
881 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
882 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
883 | 74637406 | aurel32 | /* addze addze. addzeo addzeo.*/
|
884 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
885 | 74637406 | aurel32 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
886 | 74637406 | aurel32 | /* addi */
|
887 | 99e300ef | Blue Swirl | static void gen_addi(DisasContext *ctx) |
888 | d9bce9d9 | j_mayer | { |
889 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
890 | 74637406 | aurel32 | |
891 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
892 | 74637406 | aurel32 | /* li case */
|
893 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); |
894 | 74637406 | aurel32 | } else {
|
895 | b5a73f8d | Richard Henderson | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
896 | b5a73f8d | Richard Henderson | cpu_gpr[rA(ctx->opcode)], simm); |
897 | 74637406 | aurel32 | } |
898 | d9bce9d9 | j_mayer | } |
899 | 74637406 | aurel32 | /* addic addic.*/
|
900 | b5a73f8d | Richard Henderson | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
901 | d9bce9d9 | j_mayer | { |
902 | b5a73f8d | Richard Henderson | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
903 | b5a73f8d | Richard Henderson | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
904 | b5a73f8d | Richard Henderson | c, 0, 1, 0, compute_rc0); |
905 | b5a73f8d | Richard Henderson | tcg_temp_free(c); |
906 | d9bce9d9 | j_mayer | } |
907 | 99e300ef | Blue Swirl | |
908 | 99e300ef | Blue Swirl | static void gen_addic(DisasContext *ctx) |
909 | d9bce9d9 | j_mayer | { |
910 | b5a73f8d | Richard Henderson | gen_op_addic(ctx, 0);
|
911 | d9bce9d9 | j_mayer | } |
912 | e8eaa2c0 | Blue Swirl | |
913 | e8eaa2c0 | Blue Swirl | static void gen_addic_(DisasContext *ctx) |
914 | d9bce9d9 | j_mayer | { |
915 | b5a73f8d | Richard Henderson | gen_op_addic(ctx, 1);
|
916 | d9bce9d9 | j_mayer | } |
917 | 99e300ef | Blue Swirl | |
918 | 54623277 | Blue Swirl | /* addis */
|
919 | 99e300ef | Blue Swirl | static void gen_addis(DisasContext *ctx) |
920 | d9bce9d9 | j_mayer | { |
921 | 74637406 | aurel32 | target_long simm = SIMM(ctx->opcode); |
922 | 74637406 | aurel32 | |
923 | 74637406 | aurel32 | if (rA(ctx->opcode) == 0) { |
924 | 74637406 | aurel32 | /* lis case */
|
925 | 74637406 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
|
926 | 74637406 | aurel32 | } else {
|
927 | b5a73f8d | Richard Henderson | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
928 | b5a73f8d | Richard Henderson | cpu_gpr[rA(ctx->opcode)], simm << 16);
|
929 | 74637406 | aurel32 | } |
930 | d9bce9d9 | j_mayer | } |
931 | 74637406 | aurel32 | |
932 | 636aa200 | Blue Swirl | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
933 | 636aa200 | Blue Swirl | TCGv arg2, int sign, int compute_ov) |
934 | d9bce9d9 | j_mayer | { |
935 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
936 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
937 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
938 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); |
939 | 74637406 | aurel32 | |
940 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t0, arg1); |
941 | 2ef1b120 | aurel32 | tcg_gen_trunc_tl_i32(t1, arg2); |
942 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
|
943 | 74637406 | aurel32 | if (sign) {
|
944 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
945 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
|
946 | 2ef1b120 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); |
947 | 74637406 | aurel32 | gen_set_label(l3); |
948 | 2ef1b120 | aurel32 | tcg_gen_div_i32(t0, t0, t1); |
949 | 74637406 | aurel32 | } else {
|
950 | 2ef1b120 | aurel32 | tcg_gen_divu_i32(t0, t0, t1); |
951 | 74637406 | aurel32 | } |
952 | 74637406 | aurel32 | if (compute_ov) {
|
953 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
954 | 74637406 | aurel32 | } |
955 | 74637406 | aurel32 | tcg_gen_br(l2); |
956 | 74637406 | aurel32 | gen_set_label(l1); |
957 | 74637406 | aurel32 | if (sign) {
|
958 | 2ef1b120 | aurel32 | tcg_gen_sari_i32(t0, t0, 31);
|
959 | 74637406 | aurel32 | } else {
|
960 | 74637406 | aurel32 | tcg_gen_movi_i32(t0, 0);
|
961 | 74637406 | aurel32 | } |
962 | 74637406 | aurel32 | if (compute_ov) {
|
963 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 1);
|
964 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 1);
|
965 | 74637406 | aurel32 | } |
966 | 74637406 | aurel32 | gen_set_label(l2); |
967 | 2ef1b120 | aurel32 | tcg_gen_extu_i32_tl(ret, t0); |
968 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
969 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
970 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
971 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
972 | d9bce9d9 | j_mayer | } |
973 | 74637406 | aurel32 | /* Div functions */
|
974 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
975 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
976 | 74637406 | aurel32 | { \ |
977 | 74637406 | aurel32 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
978 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
979 | 74637406 | aurel32 | sign, compute_ov); \ |
980 | 74637406 | aurel32 | } |
981 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
982 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |
983 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); |
984 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
985 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
986 | 74637406 | aurel32 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
987 | 98d1eb27 | Tom Musta | |
988 | 98d1eb27 | Tom Musta | /* div[wd]eu[o][.] */
|
989 | 98d1eb27 | Tom Musta | #define GEN_DIVE(name, hlpr, compute_ov) \
|
990 | 98d1eb27 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
991 | 98d1eb27 | Tom Musta | { \ |
992 | 98d1eb27 | Tom Musta | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ |
993 | 98d1eb27 | Tom Musta | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
994 | 98d1eb27 | Tom Musta | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ |
995 | 98d1eb27 | Tom Musta | tcg_temp_free_i32(t0); \ |
996 | 98d1eb27 | Tom Musta | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
997 | 98d1eb27 | Tom Musta | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ |
998 | 98d1eb27 | Tom Musta | } \ |
999 | 98d1eb27 | Tom Musta | } |
1000 | 98d1eb27 | Tom Musta | |
1001 | 6a4fda33 | Tom Musta | GEN_DIVE(divweu, divweu, 0);
|
1002 | 6a4fda33 | Tom Musta | GEN_DIVE(divweuo, divweu, 1);
|
1003 | a98eb9e9 | Tom Musta | GEN_DIVE(divwe, divwe, 0);
|
1004 | a98eb9e9 | Tom Musta | GEN_DIVE(divweo, divwe, 1);
|
1005 | 6a4fda33 | Tom Musta | |
1006 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1007 | 636aa200 | Blue Swirl | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1008 | 636aa200 | Blue Swirl | TCGv arg2, int sign, int compute_ov) |
1009 | d9bce9d9 | j_mayer | { |
1010 | 2ef1b120 | aurel32 | int l1 = gen_new_label();
|
1011 | 2ef1b120 | aurel32 | int l2 = gen_new_label();
|
1012 | 74637406 | aurel32 | |
1013 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
|
1014 | 74637406 | aurel32 | if (sign) {
|
1015 | 2ef1b120 | aurel32 | int l3 = gen_new_label();
|
1016 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
|
1017 | 74637406 | aurel32 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); |
1018 | 74637406 | aurel32 | gen_set_label(l3); |
1019 | 74637406 | aurel32 | tcg_gen_div_i64(ret, arg1, arg2); |
1020 | 74637406 | aurel32 | } else {
|
1021 | 74637406 | aurel32 | tcg_gen_divu_i64(ret, arg1, arg2); |
1022 | 74637406 | aurel32 | } |
1023 | 74637406 | aurel32 | if (compute_ov) {
|
1024 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
1025 | 74637406 | aurel32 | } |
1026 | 74637406 | aurel32 | tcg_gen_br(l2); |
1027 | 74637406 | aurel32 | gen_set_label(l1); |
1028 | 74637406 | aurel32 | if (sign) {
|
1029 | 74637406 | aurel32 | tcg_gen_sari_i64(ret, arg1, 63);
|
1030 | 74637406 | aurel32 | } else {
|
1031 | 74637406 | aurel32 | tcg_gen_movi_i64(ret, 0);
|
1032 | 74637406 | aurel32 | } |
1033 | 74637406 | aurel32 | if (compute_ov) {
|
1034 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 1);
|
1035 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 1);
|
1036 | 74637406 | aurel32 | } |
1037 | 74637406 | aurel32 | gen_set_label(l2); |
1038 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1039 | 74637406 | aurel32 | gen_set_Rc0(ctx, ret); |
1040 | d9bce9d9 | j_mayer | } |
1041 | 74637406 | aurel32 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
1042 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1043 | 74637406 | aurel32 | { \ |
1044 | 2ef1b120 | aurel32 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1045 | 2ef1b120 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1046 | 2ef1b120 | aurel32 | sign, compute_ov); \ |
1047 | 74637406 | aurel32 | } |
1048 | 74637406 | aurel32 | /* divwu divwu. divwuo divwuo. */
|
1049 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1050 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); |
1051 | 74637406 | aurel32 | /* divw divw. divwo divwo. */
|
1052 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1053 | 74637406 | aurel32 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); |
1054 | 98d1eb27 | Tom Musta | |
1055 | 98d1eb27 | Tom Musta | GEN_DIVE(divdeu, divdeu, 0);
|
1056 | 98d1eb27 | Tom Musta | GEN_DIVE(divdeuo, divdeu, 1);
|
1057 | e44259b6 | Tom Musta | GEN_DIVE(divde, divde, 0);
|
1058 | e44259b6 | Tom Musta | GEN_DIVE(divdeo, divde, 1);
|
1059 | d9bce9d9 | j_mayer | #endif
|
1060 | 74637406 | aurel32 | |
1061 | 74637406 | aurel32 | /* mulhw mulhw. */
|
1062 | 99e300ef | Blue Swirl | static void gen_mulhw(DisasContext *ctx) |
1063 | d9bce9d9 | j_mayer | { |
1064 | 23ad1d5d | Richard Henderson | TCGv_i32 t0 = tcg_temp_new_i32(); |
1065 | 23ad1d5d | Richard Henderson | TCGv_i32 t1 = tcg_temp_new_i32(); |
1066 | 74637406 | aurel32 | |
1067 | 23ad1d5d | Richard Henderson | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1068 | 23ad1d5d | Richard Henderson | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); |
1069 | 23ad1d5d | Richard Henderson | tcg_gen_muls2_i32(t0, t1, t0, t1); |
1070 | 23ad1d5d | Richard Henderson | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); |
1071 | 23ad1d5d | Richard Henderson | tcg_temp_free_i32(t0); |
1072 | 23ad1d5d | Richard Henderson | tcg_temp_free_i32(t1); |
1073 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1074 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1075 | d9bce9d9 | j_mayer | } |
1076 | 99e300ef | Blue Swirl | |
1077 | 54623277 | Blue Swirl | /* mulhwu mulhwu. */
|
1078 | 99e300ef | Blue Swirl | static void gen_mulhwu(DisasContext *ctx) |
1079 | d9bce9d9 | j_mayer | { |
1080 | 23ad1d5d | Richard Henderson | TCGv_i32 t0 = tcg_temp_new_i32(); |
1081 | 23ad1d5d | Richard Henderson | TCGv_i32 t1 = tcg_temp_new_i32(); |
1082 | 74637406 | aurel32 | |
1083 | 23ad1d5d | Richard Henderson | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1084 | 23ad1d5d | Richard Henderson | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); |
1085 | 23ad1d5d | Richard Henderson | tcg_gen_mulu2_i32(t0, t1, t0, t1); |
1086 | 23ad1d5d | Richard Henderson | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); |
1087 | 23ad1d5d | Richard Henderson | tcg_temp_free_i32(t0); |
1088 | 23ad1d5d | Richard Henderson | tcg_temp_free_i32(t1); |
1089 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1090 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1091 | d9bce9d9 | j_mayer | } |
1092 | 99e300ef | Blue Swirl | |
1093 | 54623277 | Blue Swirl | /* mullw mullw. */
|
1094 | 99e300ef | Blue Swirl | static void gen_mullw(DisasContext *ctx) |
1095 | d9bce9d9 | j_mayer | { |
1096 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1097 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1098 | 1e4c090f | aurel32 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
1099 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1100 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1101 | d9bce9d9 | j_mayer | } |
1102 | 99e300ef | Blue Swirl | |
1103 | 54623277 | Blue Swirl | /* mullwo mullwo. */
|
1104 | 99e300ef | Blue Swirl | static void gen_mullwo(DisasContext *ctx) |
1105 | d9bce9d9 | j_mayer | { |
1106 | e4a2c846 | Richard Henderson | TCGv_i32 t0 = tcg_temp_new_i32(); |
1107 | e4a2c846 | Richard Henderson | TCGv_i32 t1 = tcg_temp_new_i32(); |
1108 | 74637406 | aurel32 | |
1109 | e4a2c846 | Richard Henderson | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1110 | e4a2c846 | Richard Henderson | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); |
1111 | e4a2c846 | Richard Henderson | tcg_gen_muls2_i32(t0, t1, t0, t1); |
1112 | e4a2c846 | Richard Henderson | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
1113 | e4a2c846 | Richard Henderson | |
1114 | e4a2c846 | Richard Henderson | tcg_gen_sari_i32(t0, t0, 31);
|
1115 | e4a2c846 | Richard Henderson | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); |
1116 | e4a2c846 | Richard Henderson | tcg_gen_extu_i32_tl(cpu_ov, t0); |
1117 | e4a2c846 | Richard Henderson | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1118 | e4a2c846 | Richard Henderson | |
1119 | e4a2c846 | Richard Henderson | tcg_temp_free_i32(t0); |
1120 | e4a2c846 | Richard Henderson | tcg_temp_free_i32(t1); |
1121 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1122 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1123 | d9bce9d9 | j_mayer | } |
1124 | 99e300ef | Blue Swirl | |
1125 | 54623277 | Blue Swirl | /* mulli */
|
1126 | 99e300ef | Blue Swirl | static void gen_mulli(DisasContext *ctx) |
1127 | d9bce9d9 | j_mayer | { |
1128 | 74637406 | aurel32 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1129 | 74637406 | aurel32 | SIMM(ctx->opcode)); |
1130 | d9bce9d9 | j_mayer | } |
1131 | 23ad1d5d | Richard Henderson | |
1132 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1133 | 74637406 | aurel32 | /* mulhd mulhd. */
|
1134 | 23ad1d5d | Richard Henderson | static void gen_mulhd(DisasContext *ctx) |
1135 | 23ad1d5d | Richard Henderson | { |
1136 | 23ad1d5d | Richard Henderson | TCGv lo = tcg_temp_new(); |
1137 | 23ad1d5d | Richard Henderson | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], |
1138 | 23ad1d5d | Richard Henderson | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1139 | 23ad1d5d | Richard Henderson | tcg_temp_free(lo); |
1140 | 23ad1d5d | Richard Henderson | if (unlikely(Rc(ctx->opcode) != 0)) { |
1141 | 23ad1d5d | Richard Henderson | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1142 | 23ad1d5d | Richard Henderson | } |
1143 | 23ad1d5d | Richard Henderson | } |
1144 | 23ad1d5d | Richard Henderson | |
1145 | 74637406 | aurel32 | /* mulhdu mulhdu. */
|
1146 | 23ad1d5d | Richard Henderson | static void gen_mulhdu(DisasContext *ctx) |
1147 | 23ad1d5d | Richard Henderson | { |
1148 | 23ad1d5d | Richard Henderson | TCGv lo = tcg_temp_new(); |
1149 | 23ad1d5d | Richard Henderson | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], |
1150 | 23ad1d5d | Richard Henderson | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1151 | 23ad1d5d | Richard Henderson | tcg_temp_free(lo); |
1152 | 23ad1d5d | Richard Henderson | if (unlikely(Rc(ctx->opcode) != 0)) { |
1153 | 23ad1d5d | Richard Henderson | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1154 | 23ad1d5d | Richard Henderson | } |
1155 | 23ad1d5d | Richard Henderson | } |
1156 | 99e300ef | Blue Swirl | |
1157 | 54623277 | Blue Swirl | /* mulld mulld. */
|
1158 | 99e300ef | Blue Swirl | static void gen_mulld(DisasContext *ctx) |
1159 | d9bce9d9 | j_mayer | { |
1160 | 74637406 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1161 | 74637406 | aurel32 | cpu_gpr[rB(ctx->opcode)]); |
1162 | 74637406 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1163 | 74637406 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1164 | d9bce9d9 | j_mayer | } |
1165 | d15f74fb | Blue Swirl | |
1166 | 74637406 | aurel32 | /* mulldo mulldo. */
|
1167 | d15f74fb | Blue Swirl | static void gen_mulldo(DisasContext *ctx) |
1168 | d15f74fb | Blue Swirl | { |
1169 | d15f74fb | Blue Swirl | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
1170 | d15f74fb | Blue Swirl | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1171 | d15f74fb | Blue Swirl | if (unlikely(Rc(ctx->opcode) != 0)) { |
1172 | d15f74fb | Blue Swirl | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1173 | d15f74fb | Blue Swirl | } |
1174 | d15f74fb | Blue Swirl | } |
1175 | d9bce9d9 | j_mayer | #endif
|
1176 | 74637406 | aurel32 | |
1177 | 74637406 | aurel32 | /* Common subf function */
|
1178 | 636aa200 | Blue Swirl | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1179 | b5a73f8d | Richard Henderson | TCGv arg2, bool add_ca, bool compute_ca, |
1180 | b5a73f8d | Richard Henderson | bool compute_ov, bool compute_rc0) |
1181 | 79aceca5 | bellard | { |
1182 | b5a73f8d | Richard Henderson | TCGv t0 = ret; |
1183 | 79aceca5 | bellard | |
1184 | 752d634e | Richard Henderson | if (compute_ca || compute_ov) {
|
1185 | b5a73f8d | Richard Henderson | t0 = tcg_temp_new(); |
1186 | da91a00f | Richard Henderson | } |
1187 | 74637406 | aurel32 | |
1188 | 79482e5a | Richard Henderson | if (compute_ca) {
|
1189 | 79482e5a | Richard Henderson | /* dest = ~arg1 + arg2 [+ ca]. */
|
1190 | 79482e5a | Richard Henderson | if (NARROW_MODE(ctx)) {
|
1191 | 752d634e | Richard Henderson | /* Caution: a non-obvious corner case of the spec is that we
|
1192 | 752d634e | Richard Henderson | must produce the *entire* 64-bit addition, but produce the
|
1193 | 752d634e | Richard Henderson | carry into bit 32. */
|
1194 | 79482e5a | Richard Henderson | TCGv inv1 = tcg_temp_new(); |
1195 | 752d634e | Richard Henderson | TCGv t1 = tcg_temp_new(); |
1196 | 79482e5a | Richard Henderson | tcg_gen_not_tl(inv1, arg1); |
1197 | 79482e5a | Richard Henderson | if (add_ca) {
|
1198 | 752d634e | Richard Henderson | tcg_gen_add_tl(t0, arg2, cpu_ca); |
1199 | 79482e5a | Richard Henderson | } else {
|
1200 | 752d634e | Richard Henderson | tcg_gen_addi_tl(t0, arg2, 1);
|
1201 | 79482e5a | Richard Henderson | } |
1202 | 752d634e | Richard Henderson | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
|
1203 | 79482e5a | Richard Henderson | tcg_gen_add_tl(t0, t0, inv1); |
1204 | 752d634e | Richard Henderson | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
|
1205 | 752d634e | Richard Henderson | tcg_temp_free(t1); |
1206 | 752d634e | Richard Henderson | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ |
1207 | 752d634e | Richard Henderson | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
|
1208 | 79482e5a | Richard Henderson | } else if (add_ca) { |
1209 | 08f4a0f7 | Richard Henderson | TCGv zero, inv1 = tcg_temp_new(); |
1210 | 08f4a0f7 | Richard Henderson | tcg_gen_not_tl(inv1, arg1); |
1211 | b5a73f8d | Richard Henderson | zero = tcg_const_tl(0);
|
1212 | b5a73f8d | Richard Henderson | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); |
1213 | 08f4a0f7 | Richard Henderson | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
1214 | b5a73f8d | Richard Henderson | tcg_temp_free(zero); |
1215 | 08f4a0f7 | Richard Henderson | tcg_temp_free(inv1); |
1216 | b5a73f8d | Richard Henderson | } else {
|
1217 | 79482e5a | Richard Henderson | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
1218 | b5a73f8d | Richard Henderson | tcg_gen_sub_tl(t0, arg2, arg1); |
1219 | b5a73f8d | Richard Henderson | } |
1220 | 79482e5a | Richard Henderson | } else if (add_ca) { |
1221 | 79482e5a | Richard Henderson | /* Since we're ignoring carry-out, we can simplify the
|
1222 | 79482e5a | Richard Henderson | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
|
1223 | 79482e5a | Richard Henderson | tcg_gen_sub_tl(t0, arg2, arg1); |
1224 | 79482e5a | Richard Henderson | tcg_gen_add_tl(t0, t0, cpu_ca); |
1225 | 79482e5a | Richard Henderson | tcg_gen_subi_tl(t0, t0, 1);
|
1226 | 79aceca5 | bellard | } else {
|
1227 | b5a73f8d | Richard Henderson | tcg_gen_sub_tl(t0, arg2, arg1); |
1228 | 74637406 | aurel32 | } |
1229 | b5a73f8d | Richard Henderson | |
1230 | 74637406 | aurel32 | if (compute_ov) {
|
1231 | 74637406 | aurel32 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
|
1232 | 74637406 | aurel32 | } |
1233 | b5a73f8d | Richard Henderson | if (unlikely(compute_rc0)) {
|
1234 | 74637406 | aurel32 | gen_set_Rc0(ctx, t0); |
1235 | b5a73f8d | Richard Henderson | } |
1236 | 74637406 | aurel32 | |
1237 | a7812ae4 | pbrook | if (!TCGV_EQUAL(t0, ret)) {
|
1238 | 74637406 | aurel32 | tcg_gen_mov_tl(ret, t0); |
1239 | 74637406 | aurel32 | tcg_temp_free(t0); |
1240 | 79aceca5 | bellard | } |
1241 | 79aceca5 | bellard | } |
1242 | 74637406 | aurel32 | /* Sub functions with Two operands functions */
|
1243 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
1244 | b5a73f8d | Richard Henderson | static void glue(gen_, name)(DisasContext *ctx) \ |
1245 | 74637406 | aurel32 | { \ |
1246 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1247 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1248 | b5a73f8d | Richard Henderson | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
1249 | 74637406 | aurel32 | } |
1250 | 74637406 | aurel32 | /* Sub functions with one operand and one immediate */
|
1251 | 74637406 | aurel32 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
1252 | 74637406 | aurel32 | add_ca, compute_ca, compute_ov) \ |
1253 | b5a73f8d | Richard Henderson | static void glue(gen_, name)(DisasContext *ctx) \ |
1254 | 74637406 | aurel32 | { \ |
1255 | b5a73f8d | Richard Henderson | TCGv t0 = tcg_const_tl(const_val); \ |
1256 | 74637406 | aurel32 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1257 | 74637406 | aurel32 | cpu_gpr[rA(ctx->opcode)], t0, \ |
1258 | b5a73f8d | Richard Henderson | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
1259 | 74637406 | aurel32 | tcg_temp_free(t0); \ |
1260 | 74637406 | aurel32 | } |
1261 | 74637406 | aurel32 | /* subf subf. subfo subfo. */
|
1262 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
1263 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
1264 | 74637406 | aurel32 | /* subfc subfc. subfco subfco. */
|
1265 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
1266 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
1267 | 74637406 | aurel32 | /* subfe subfe. subfeo subfo. */
|
1268 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
1269 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
1270 | 74637406 | aurel32 | /* subfme subfme. subfmeo subfmeo. */
|
1271 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
1272 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
1273 | 74637406 | aurel32 | /* subfze subfze. subfzeo subfzeo.*/
|
1274 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
1275 | 74637406 | aurel32 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
1276 | 99e300ef | Blue Swirl | |
1277 | 54623277 | Blue Swirl | /* subfic */
|
1278 | 99e300ef | Blue Swirl | static void gen_subfic(DisasContext *ctx) |
1279 | 79aceca5 | bellard | { |
1280 | b5a73f8d | Richard Henderson | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1281 | b5a73f8d | Richard Henderson | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1282 | b5a73f8d | Richard Henderson | c, 0, 1, 0, 0); |
1283 | b5a73f8d | Richard Henderson | tcg_temp_free(c); |
1284 | 79aceca5 | bellard | } |
1285 | 79aceca5 | bellard | |
1286 | fd3f0081 | Richard Henderson | /* neg neg. nego nego. */
|
1287 | fd3f0081 | Richard Henderson | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) |
1288 | fd3f0081 | Richard Henderson | { |
1289 | fd3f0081 | Richard Henderson | TCGv zero = tcg_const_tl(0);
|
1290 | fd3f0081 | Richard Henderson | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1291 | fd3f0081 | Richard Henderson | zero, 0, 0, compute_ov, Rc(ctx->opcode)); |
1292 | fd3f0081 | Richard Henderson | tcg_temp_free(zero); |
1293 | fd3f0081 | Richard Henderson | } |
1294 | fd3f0081 | Richard Henderson | |
1295 | fd3f0081 | Richard Henderson | static void gen_neg(DisasContext *ctx) |
1296 | fd3f0081 | Richard Henderson | { |
1297 | fd3f0081 | Richard Henderson | gen_op_arith_neg(ctx, 0);
|
1298 | fd3f0081 | Richard Henderson | } |
1299 | fd3f0081 | Richard Henderson | |
1300 | fd3f0081 | Richard Henderson | static void gen_nego(DisasContext *ctx) |
1301 | fd3f0081 | Richard Henderson | { |
1302 | fd3f0081 | Richard Henderson | gen_op_arith_neg(ctx, 1);
|
1303 | fd3f0081 | Richard Henderson | } |
1304 | fd3f0081 | Richard Henderson | |
1305 | 79aceca5 | bellard | /*** Integer logical ***/
|
1306 | 26d67362 | aurel32 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
1307 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1308 | 79aceca5 | bellard | { \ |
1309 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1310 | 26d67362 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
1311 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1312 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1313 | 79aceca5 | bellard | } |
1314 | 79aceca5 | bellard | |
1315 | 26d67362 | aurel32 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
1316 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
1317 | 79aceca5 | bellard | { \ |
1318 | 26d67362 | aurel32 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
1319 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1320 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1321 | 79aceca5 | bellard | } |
1322 | 79aceca5 | bellard | |
1323 | 79aceca5 | bellard | /* and & and. */
|
1324 | 26d67362 | aurel32 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
|
1325 | 79aceca5 | bellard | /* andc & andc. */
|
1326 | 26d67362 | aurel32 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
|
1327 | e8eaa2c0 | Blue Swirl | |
1328 | 54623277 | Blue Swirl | /* andi. */
|
1329 | e8eaa2c0 | Blue Swirl | static void gen_andi_(DisasContext *ctx) |
1330 | 79aceca5 | bellard | { |
1331 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1332 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1333 | 79aceca5 | bellard | } |
1334 | e8eaa2c0 | Blue Swirl | |
1335 | 54623277 | Blue Swirl | /* andis. */
|
1336 | e8eaa2c0 | Blue Swirl | static void gen_andis_(DisasContext *ctx) |
1337 | 79aceca5 | bellard | { |
1338 | 26d67362 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
|
1339 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1340 | 79aceca5 | bellard | } |
1341 | 99e300ef | Blue Swirl | |
1342 | 54623277 | Blue Swirl | /* cntlzw */
|
1343 | 99e300ef | Blue Swirl | static void gen_cntlzw(DisasContext *ctx) |
1344 | 26d67362 | aurel32 | { |
1345 | a7812ae4 | pbrook | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1346 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1347 | 2e31f5d3 | pbrook | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1348 | 26d67362 | aurel32 | } |
1349 | 79aceca5 | bellard | /* eqv & eqv. */
|
1350 | 26d67362 | aurel32 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
|
1351 | 79aceca5 | bellard | /* extsb & extsb. */
|
1352 | 26d67362 | aurel32 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
|
1353 | 79aceca5 | bellard | /* extsh & extsh. */
|
1354 | 26d67362 | aurel32 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
|
1355 | 79aceca5 | bellard | /* nand & nand. */
|
1356 | 26d67362 | aurel32 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
|
1357 | 79aceca5 | bellard | /* nor & nor. */
|
1358 | 26d67362 | aurel32 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
|
1359 | 99e300ef | Blue Swirl | |
1360 | 54623277 | Blue Swirl | /* or & or. */
|
1361 | 99e300ef | Blue Swirl | static void gen_or(DisasContext *ctx) |
1362 | 9a64fbe4 | bellard | { |
1363 | 76a66253 | j_mayer | int rs, ra, rb;
|
1364 | 76a66253 | j_mayer | |
1365 | 76a66253 | j_mayer | rs = rS(ctx->opcode); |
1366 | 76a66253 | j_mayer | ra = rA(ctx->opcode); |
1367 | 76a66253 | j_mayer | rb = rB(ctx->opcode); |
1368 | 76a66253 | j_mayer | /* Optimisation for mr. ri case */
|
1369 | 76a66253 | j_mayer | if (rs != ra || rs != rb) {
|
1370 | 26d67362 | aurel32 | if (rs != rb)
|
1371 | 26d67362 | aurel32 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
1372 | 26d67362 | aurel32 | else
|
1373 | 26d67362 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
1374 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1375 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
1376 | 76a66253 | j_mayer | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
1377 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
1378 | c80f84e3 | j_mayer | #if defined(TARGET_PPC64)
|
1379 | c80f84e3 | j_mayer | } else {
|
1380 | 26d67362 | aurel32 | int prio = 0; |
1381 | 26d67362 | aurel32 | |
1382 | c80f84e3 | j_mayer | switch (rs) {
|
1383 | c80f84e3 | j_mayer | case 1: |
1384 | c80f84e3 | j_mayer | /* Set process priority to low */
|
1385 | 26d67362 | aurel32 | prio = 2;
|
1386 | c80f84e3 | j_mayer | break;
|
1387 | c80f84e3 | j_mayer | case 6: |
1388 | c80f84e3 | j_mayer | /* Set process priority to medium-low */
|
1389 | 26d67362 | aurel32 | prio = 3;
|
1390 | c80f84e3 | j_mayer | break;
|
1391 | c80f84e3 | j_mayer | case 2: |
1392 | c80f84e3 | j_mayer | /* Set process priority to normal */
|
1393 | 26d67362 | aurel32 | prio = 4;
|
1394 | c80f84e3 | j_mayer | break;
|
1395 | be147d08 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
1396 | be147d08 | j_mayer | case 31: |
1397 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1398 | be147d08 | j_mayer | /* Set process priority to very low */
|
1399 | 26d67362 | aurel32 | prio = 1;
|
1400 | be147d08 | j_mayer | } |
1401 | be147d08 | j_mayer | break;
|
1402 | be147d08 | j_mayer | case 5: |
1403 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1404 | be147d08 | j_mayer | /* Set process priority to medium-hight */
|
1405 | 26d67362 | aurel32 | prio = 5;
|
1406 | be147d08 | j_mayer | } |
1407 | be147d08 | j_mayer | break;
|
1408 | be147d08 | j_mayer | case 3: |
1409 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 0) { |
1410 | be147d08 | j_mayer | /* Set process priority to high */
|
1411 | 26d67362 | aurel32 | prio = 6;
|
1412 | be147d08 | j_mayer | } |
1413 | be147d08 | j_mayer | break;
|
1414 | be147d08 | j_mayer | case 7: |
1415 | 76db3ba4 | aurel32 | if (ctx->mem_idx > 1) { |
1416 | be147d08 | j_mayer | /* Set process priority to very high */
|
1417 | 26d67362 | aurel32 | prio = 7;
|
1418 | be147d08 | j_mayer | } |
1419 | be147d08 | j_mayer | break;
|
1420 | be147d08 | j_mayer | #endif
|
1421 | c80f84e3 | j_mayer | default:
|
1422 | c80f84e3 | j_mayer | /* nop */
|
1423 | c80f84e3 | j_mayer | break;
|
1424 | c80f84e3 | j_mayer | } |
1425 | 26d67362 | aurel32 | if (prio) {
|
1426 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1427 | 54cdcae6 | aurel32 | gen_load_spr(t0, SPR_PPR); |
1428 | ea363694 | aurel32 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
|
1429 | ea363694 | aurel32 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
|
1430 | 54cdcae6 | aurel32 | gen_store_spr(SPR_PPR, t0); |
1431 | ea363694 | aurel32 | tcg_temp_free(t0); |
1432 | 26d67362 | aurel32 | } |
1433 | c80f84e3 | j_mayer | #endif
|
1434 | 9a64fbe4 | bellard | } |
1435 | 9a64fbe4 | bellard | } |
1436 | 79aceca5 | bellard | /* orc & orc. */
|
1437 | 26d67362 | aurel32 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
|
1438 | 99e300ef | Blue Swirl | |
1439 | 54623277 | Blue Swirl | /* xor & xor. */
|
1440 | 99e300ef | Blue Swirl | static void gen_xor(DisasContext *ctx) |
1441 | 9a64fbe4 | bellard | { |
1442 | 9a64fbe4 | bellard | /* Optimisation for "set to zero" case */
|
1443 | 26d67362 | aurel32 | if (rS(ctx->opcode) != rB(ctx->opcode))
|
1444 | 312179c4 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1445 | 26d67362 | aurel32 | else
|
1446 | 26d67362 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
1447 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1448 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1449 | 9a64fbe4 | bellard | } |
1450 | 99e300ef | Blue Swirl | |
1451 | 54623277 | Blue Swirl | /* ori */
|
1452 | 99e300ef | Blue Swirl | static void gen_ori(DisasContext *ctx) |
1453 | 79aceca5 | bellard | { |
1454 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1455 | 79aceca5 | bellard | |
1456 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1457 | 9a64fbe4 | bellard | /* NOP */
|
1458 | 76a66253 | j_mayer | /* XXX: should handle special NOPs for POWER series */
|
1459 | 9a64fbe4 | bellard | return;
|
1460 | 76a66253 | j_mayer | } |
1461 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1462 | 79aceca5 | bellard | } |
1463 | 99e300ef | Blue Swirl | |
1464 | 54623277 | Blue Swirl | /* oris */
|
1465 | 99e300ef | Blue Swirl | static void gen_oris(DisasContext *ctx) |
1466 | 79aceca5 | bellard | { |
1467 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1468 | 79aceca5 | bellard | |
1469 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1470 | 9a64fbe4 | bellard | /* NOP */
|
1471 | 9a64fbe4 | bellard | return;
|
1472 | 76a66253 | j_mayer | } |
1473 | 26d67362 | aurel32 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1474 | 79aceca5 | bellard | } |
1475 | 99e300ef | Blue Swirl | |
1476 | 54623277 | Blue Swirl | /* xori */
|
1477 | 99e300ef | Blue Swirl | static void gen_xori(DisasContext *ctx) |
1478 | 79aceca5 | bellard | { |
1479 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1480 | 9a64fbe4 | bellard | |
1481 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1482 | 9a64fbe4 | bellard | /* NOP */
|
1483 | 9a64fbe4 | bellard | return;
|
1484 | 9a64fbe4 | bellard | } |
1485 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1486 | 79aceca5 | bellard | } |
1487 | 99e300ef | Blue Swirl | |
1488 | 54623277 | Blue Swirl | /* xoris */
|
1489 | 99e300ef | Blue Swirl | static void gen_xoris(DisasContext *ctx) |
1490 | 79aceca5 | bellard | { |
1491 | 76a66253 | j_mayer | target_ulong uimm = UIMM(ctx->opcode); |
1492 | 9a64fbe4 | bellard | |
1493 | 9a64fbe4 | bellard | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1494 | 9a64fbe4 | bellard | /* NOP */
|
1495 | 9a64fbe4 | bellard | return;
|
1496 | 9a64fbe4 | bellard | } |
1497 | 26d67362 | aurel32 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
|
1498 | 79aceca5 | bellard | } |
1499 | 99e300ef | Blue Swirl | |
1500 | 54623277 | Blue Swirl | /* popcntb : PowerPC 2.03 specification */
|
1501 | 99e300ef | Blue Swirl | static void gen_popcntb(DisasContext *ctx) |
1502 | d9bce9d9 | j_mayer | { |
1503 | eaabeef2 | David Gibson | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1504 | eaabeef2 | David Gibson | } |
1505 | eaabeef2 | David Gibson | |
1506 | eaabeef2 | David Gibson | static void gen_popcntw(DisasContext *ctx) |
1507 | eaabeef2 | David Gibson | { |
1508 | eaabeef2 | David Gibson | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1509 | eaabeef2 | David Gibson | } |
1510 | eaabeef2 | David Gibson | |
1511 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1512 | eaabeef2 | David Gibson | /* popcntd: PowerPC 2.06 specification */
|
1513 | eaabeef2 | David Gibson | static void gen_popcntd(DisasContext *ctx) |
1514 | eaabeef2 | David Gibson | { |
1515 | eaabeef2 | David Gibson | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1516 | d9bce9d9 | j_mayer | } |
1517 | eaabeef2 | David Gibson | #endif
|
1518 | d9bce9d9 | j_mayer | |
1519 | 725bcec2 | Aurelien Jarno | /* prtyw: PowerPC 2.05 specification */
|
1520 | 725bcec2 | Aurelien Jarno | static void gen_prtyw(DisasContext *ctx) |
1521 | 725bcec2 | Aurelien Jarno | { |
1522 | 725bcec2 | Aurelien Jarno | TCGv ra = cpu_gpr[rA(ctx->opcode)]; |
1523 | 725bcec2 | Aurelien Jarno | TCGv rs = cpu_gpr[rS(ctx->opcode)]; |
1524 | 725bcec2 | Aurelien Jarno | TCGv t0 = tcg_temp_new(); |
1525 | 725bcec2 | Aurelien Jarno | tcg_gen_shri_tl(t0, rs, 16);
|
1526 | 725bcec2 | Aurelien Jarno | tcg_gen_xor_tl(ra, rs, t0); |
1527 | 725bcec2 | Aurelien Jarno | tcg_gen_shri_tl(t0, ra, 8);
|
1528 | 725bcec2 | Aurelien Jarno | tcg_gen_xor_tl(ra, ra, t0); |
1529 | 725bcec2 | Aurelien Jarno | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
|
1530 | 725bcec2 | Aurelien Jarno | tcg_temp_free(t0); |
1531 | 725bcec2 | Aurelien Jarno | } |
1532 | 725bcec2 | Aurelien Jarno | |
1533 | 725bcec2 | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1534 | 725bcec2 | Aurelien Jarno | /* prtyd: PowerPC 2.05 specification */
|
1535 | 725bcec2 | Aurelien Jarno | static void gen_prtyd(DisasContext *ctx) |
1536 | 725bcec2 | Aurelien Jarno | { |
1537 | 725bcec2 | Aurelien Jarno | TCGv ra = cpu_gpr[rA(ctx->opcode)]; |
1538 | 725bcec2 | Aurelien Jarno | TCGv rs = cpu_gpr[rS(ctx->opcode)]; |
1539 | 725bcec2 | Aurelien Jarno | TCGv t0 = tcg_temp_new(); |
1540 | 725bcec2 | Aurelien Jarno | tcg_gen_shri_tl(t0, rs, 32);
|
1541 | 725bcec2 | Aurelien Jarno | tcg_gen_xor_tl(ra, rs, t0); |
1542 | 725bcec2 | Aurelien Jarno | tcg_gen_shri_tl(t0, ra, 16);
|
1543 | 725bcec2 | Aurelien Jarno | tcg_gen_xor_tl(ra, ra, t0); |
1544 | 725bcec2 | Aurelien Jarno | tcg_gen_shri_tl(t0, ra, 8);
|
1545 | 725bcec2 | Aurelien Jarno | tcg_gen_xor_tl(ra, ra, t0); |
1546 | 725bcec2 | Aurelien Jarno | tcg_gen_andi_tl(ra, ra, 1);
|
1547 | 725bcec2 | Aurelien Jarno | tcg_temp_free(t0); |
1548 | 725bcec2 | Aurelien Jarno | } |
1549 | 725bcec2 | Aurelien Jarno | #endif
|
1550 | 725bcec2 | Aurelien Jarno | |
1551 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1552 | 86ba37ed | Tom Musta | /* bpermd */
|
1553 | 86ba37ed | Tom Musta | static void gen_bpermd(DisasContext *ctx) |
1554 | 86ba37ed | Tom Musta | { |
1555 | 86ba37ed | Tom Musta | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], |
1556 | 86ba37ed | Tom Musta | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1557 | 86ba37ed | Tom Musta | } |
1558 | 86ba37ed | Tom Musta | #endif
|
1559 | 86ba37ed | Tom Musta | |
1560 | 86ba37ed | Tom Musta | #if defined(TARGET_PPC64)
|
1561 | d9bce9d9 | j_mayer | /* extsw & extsw. */
|
1562 | 26d67362 | aurel32 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
|
1563 | 99e300ef | Blue Swirl | |
1564 | 54623277 | Blue Swirl | /* cntlzd */
|
1565 | 99e300ef | Blue Swirl | static void gen_cntlzd(DisasContext *ctx) |
1566 | 26d67362 | aurel32 | { |
1567 | a7812ae4 | pbrook | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1568 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1569 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1570 | 26d67362 | aurel32 | } |
1571 | d9bce9d9 | j_mayer | #endif
|
1572 | d9bce9d9 | j_mayer | |
1573 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1574 | 99e300ef | Blue Swirl | |
1575 | 54623277 | Blue Swirl | /* rlwimi & rlwimi. */
|
1576 | 99e300ef | Blue Swirl | static void gen_rlwimi(DisasContext *ctx) |
1577 | 79aceca5 | bellard | { |
1578 | 76a66253 | j_mayer | uint32_t mb, me, sh; |
1579 | 79aceca5 | bellard | |
1580 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1581 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1582 | 76a66253 | j_mayer | sh = SH(ctx->opcode); |
1583 | d03ef511 | aurel32 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1584 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1585 | d03ef511 | aurel32 | } else {
|
1586 | d03ef511 | aurel32 | target_ulong mask; |
1587 | a7812ae4 | pbrook | TCGv t1; |
1588 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1589 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1590 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_new_i32(); |
1591 | a7812ae4 | pbrook | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); |
1592 | a7812ae4 | pbrook | tcg_gen_rotli_i32(t2, t2, sh); |
1593 | a7812ae4 | pbrook | tcg_gen_extu_i32_i64(t0, t2); |
1594 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1595 | 54843a58 | aurel32 | #else
|
1596 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1597 | 54843a58 | aurel32 | #endif
|
1598 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1599 | d03ef511 | aurel32 | mb += 32;
|
1600 | d03ef511 | aurel32 | me += 32;
|
1601 | 76a66253 | j_mayer | #endif
|
1602 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1603 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1604 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1605 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1606 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1607 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1608 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1609 | d03ef511 | aurel32 | } |
1610 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1611 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1612 | 79aceca5 | bellard | } |
1613 | 99e300ef | Blue Swirl | |
1614 | 54623277 | Blue Swirl | /* rlwinm & rlwinm. */
|
1615 | 99e300ef | Blue Swirl | static void gen_rlwinm(DisasContext *ctx) |
1616 | 79aceca5 | bellard | { |
1617 | 79aceca5 | bellard | uint32_t mb, me, sh; |
1618 | 3b46e624 | ths | |
1619 | 79aceca5 | bellard | sh = SH(ctx->opcode); |
1620 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1621 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1622 | d03ef511 | aurel32 | |
1623 | d03ef511 | aurel32 | if (likely(mb == 0 && me == (31 - sh))) { |
1624 | d03ef511 | aurel32 | if (likely(sh == 0)) { |
1625 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1626 | d03ef511 | aurel32 | } else {
|
1627 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1628 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1629 | d03ef511 | aurel32 | tcg_gen_shli_tl(t0, t0, sh); |
1630 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1631 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1632 | 79aceca5 | bellard | } |
1633 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
1634 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1635 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1636 | d03ef511 | aurel32 | tcg_gen_shri_tl(t0, t0, mb); |
1637 | d03ef511 | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1638 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1639 | d03ef511 | aurel32 | } else {
|
1640 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1641 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1642 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_new_i32(); |
1643 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1644 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t1, t1, sh); |
1645 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1646 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1647 | 54843a58 | aurel32 | #else
|
1648 | 54843a58 | aurel32 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1649 | 54843a58 | aurel32 | #endif
|
1650 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1651 | d03ef511 | aurel32 | mb += 32;
|
1652 | d03ef511 | aurel32 | me += 32;
|
1653 | 76a66253 | j_mayer | #endif
|
1654 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1655 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1656 | d03ef511 | aurel32 | } |
1657 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1658 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1659 | 79aceca5 | bellard | } |
1660 | 99e300ef | Blue Swirl | |
1661 | 54623277 | Blue Swirl | /* rlwnm & rlwnm. */
|
1662 | 99e300ef | Blue Swirl | static void gen_rlwnm(DisasContext *ctx) |
1663 | 79aceca5 | bellard | { |
1664 | 79aceca5 | bellard | uint32_t mb, me; |
1665 | 54843a58 | aurel32 | TCGv t0; |
1666 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1667 | a7812ae4 | pbrook | TCGv_i32 t1, t2; |
1668 | 54843a58 | aurel32 | #endif
|
1669 | 79aceca5 | bellard | |
1670 | 79aceca5 | bellard | mb = MB(ctx->opcode); |
1671 | 79aceca5 | bellard | me = ME(ctx->opcode); |
1672 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1673 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1674 | 54843a58 | aurel32 | #if defined(TARGET_PPC64)
|
1675 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); |
1676 | a7812ae4 | pbrook | t2 = tcg_temp_new_i32(); |
1677 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1678 | 54843a58 | aurel32 | tcg_gen_trunc_i64_i32(t2, t0); |
1679 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t1, t1, t2); |
1680 | 54843a58 | aurel32 | tcg_gen_extu_i32_i64(t0, t1); |
1681 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); |
1682 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); |
1683 | 54843a58 | aurel32 | #else
|
1684 | 54843a58 | aurel32 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1685 | 54843a58 | aurel32 | #endif
|
1686 | 76a66253 | j_mayer | if (unlikely(mb != 0 || me != 31)) { |
1687 | 76a66253 | j_mayer | #if defined(TARGET_PPC64)
|
1688 | 76a66253 | j_mayer | mb += 32;
|
1689 | 76a66253 | j_mayer | me += 32;
|
1690 | 76a66253 | j_mayer | #endif
|
1691 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1692 | d03ef511 | aurel32 | } else {
|
1693 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1694 | 79aceca5 | bellard | } |
1695 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1696 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1697 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1698 | 79aceca5 | bellard | } |
1699 | 79aceca5 | bellard | |
1700 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1701 | d9bce9d9 | j_mayer | #define GEN_PPC64_R2(name, opc1, opc2) \
|
1702 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1703 | d9bce9d9 | j_mayer | { \ |
1704 | d9bce9d9 | j_mayer | gen_##name(ctx, 0); \ |
1705 | d9bce9d9 | j_mayer | } \ |
1706 | e8eaa2c0 | Blue Swirl | \ |
1707 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1708 | d9bce9d9 | j_mayer | { \ |
1709 | d9bce9d9 | j_mayer | gen_##name(ctx, 1); \ |
1710 | d9bce9d9 | j_mayer | } |
1711 | d9bce9d9 | j_mayer | #define GEN_PPC64_R4(name, opc1, opc2) \
|
1712 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##0)(DisasContext *ctx) \ |
1713 | d9bce9d9 | j_mayer | { \ |
1714 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 0); \ |
1715 | d9bce9d9 | j_mayer | } \ |
1716 | e8eaa2c0 | Blue Swirl | \ |
1717 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##1)(DisasContext *ctx) \ |
1718 | d9bce9d9 | j_mayer | { \ |
1719 | d9bce9d9 | j_mayer | gen_##name(ctx, 0, 1); \ |
1720 | d9bce9d9 | j_mayer | } \ |
1721 | e8eaa2c0 | Blue Swirl | \ |
1722 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##2)(DisasContext *ctx) \ |
1723 | d9bce9d9 | j_mayer | { \ |
1724 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 0); \ |
1725 | d9bce9d9 | j_mayer | } \ |
1726 | e8eaa2c0 | Blue Swirl | \ |
1727 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name##3)(DisasContext *ctx) \ |
1728 | d9bce9d9 | j_mayer | { \ |
1729 | d9bce9d9 | j_mayer | gen_##name(ctx, 1, 1); \ |
1730 | d9bce9d9 | j_mayer | } |
1731 | 51789c41 | j_mayer | |
1732 | 636aa200 | Blue Swirl | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1733 | 636aa200 | Blue Swirl | uint32_t sh) |
1734 | 51789c41 | j_mayer | { |
1735 | d03ef511 | aurel32 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1736 | d03ef511 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
1737 | d03ef511 | aurel32 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { |
1738 | d03ef511 | aurel32 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); |
1739 | d03ef511 | aurel32 | } else {
|
1740 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
1741 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1742 | d03ef511 | aurel32 | if (likely(mb == 0 && me == 63)) { |
1743 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1744 | d03ef511 | aurel32 | } else {
|
1745 | d03ef511 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1746 | 51789c41 | j_mayer | } |
1747 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1748 | 51789c41 | j_mayer | } |
1749 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1750 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1751 | 51789c41 | j_mayer | } |
1752 | d9bce9d9 | j_mayer | /* rldicl - rldicl. */
|
1753 | 636aa200 | Blue Swirl | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
1754 | d9bce9d9 | j_mayer | { |
1755 | 51789c41 | j_mayer | uint32_t sh, mb; |
1756 | d9bce9d9 | j_mayer | |
1757 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1758 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1759 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63, sh);
|
1760 | d9bce9d9 | j_mayer | } |
1761 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
1762 | d9bce9d9 | j_mayer | /* rldicr - rldicr. */
|
1763 | 636aa200 | Blue Swirl | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
1764 | d9bce9d9 | j_mayer | { |
1765 | 51789c41 | j_mayer | uint32_t sh, me; |
1766 | d9bce9d9 | j_mayer | |
1767 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1768 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1769 | 51789c41 | j_mayer | gen_rldinm(ctx, 0, me, sh);
|
1770 | d9bce9d9 | j_mayer | } |
1771 | 51789c41 | j_mayer | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
1772 | d9bce9d9 | j_mayer | /* rldic - rldic. */
|
1773 | 636aa200 | Blue Swirl | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
1774 | d9bce9d9 | j_mayer | { |
1775 | 51789c41 | j_mayer | uint32_t sh, mb; |
1776 | d9bce9d9 | j_mayer | |
1777 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1778 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1779 | 51789c41 | j_mayer | gen_rldinm(ctx, mb, 63 - sh, sh);
|
1780 | 51789c41 | j_mayer | } |
1781 | 51789c41 | j_mayer | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
1782 | 51789c41 | j_mayer | |
1783 | 636aa200 | Blue Swirl | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
1784 | 51789c41 | j_mayer | { |
1785 | 54843a58 | aurel32 | TCGv t0; |
1786 | d03ef511 | aurel32 | |
1787 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1788 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1789 | 54843a58 | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1790 | 51789c41 | j_mayer | if (unlikely(mb != 0 || me != 63)) { |
1791 | 54843a58 | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1792 | 54843a58 | aurel32 | } else {
|
1793 | 54843a58 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
1794 | 54843a58 | aurel32 | } |
1795 | 54843a58 | aurel32 | tcg_temp_free(t0); |
1796 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1797 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1798 | d9bce9d9 | j_mayer | } |
1799 | 51789c41 | j_mayer | |
1800 | d9bce9d9 | j_mayer | /* rldcl - rldcl. */
|
1801 | 636aa200 | Blue Swirl | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
1802 | d9bce9d9 | j_mayer | { |
1803 | 51789c41 | j_mayer | uint32_t mb; |
1804 | d9bce9d9 | j_mayer | |
1805 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1806 | 51789c41 | j_mayer | gen_rldnm(ctx, mb, 63);
|
1807 | d9bce9d9 | j_mayer | } |
1808 | 36081602 | j_mayer | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
1809 | d9bce9d9 | j_mayer | /* rldcr - rldcr. */
|
1810 | 636aa200 | Blue Swirl | static inline void gen_rldcr(DisasContext *ctx, int men) |
1811 | d9bce9d9 | j_mayer | { |
1812 | 51789c41 | j_mayer | uint32_t me; |
1813 | d9bce9d9 | j_mayer | |
1814 | 9d53c753 | j_mayer | me = MB(ctx->opcode) | (men << 5);
|
1815 | 51789c41 | j_mayer | gen_rldnm(ctx, 0, me);
|
1816 | d9bce9d9 | j_mayer | } |
1817 | 36081602 | j_mayer | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
1818 | d9bce9d9 | j_mayer | /* rldimi - rldimi. */
|
1819 | 636aa200 | Blue Swirl | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
1820 | d9bce9d9 | j_mayer | { |
1821 | 271a916e | j_mayer | uint32_t sh, mb, me; |
1822 | d9bce9d9 | j_mayer | |
1823 | 9d53c753 | j_mayer | sh = SH(ctx->opcode) | (shn << 5);
|
1824 | 9d53c753 | j_mayer | mb = MB(ctx->opcode) | (mbn << 5);
|
1825 | 271a916e | j_mayer | me = 63 - sh;
|
1826 | d03ef511 | aurel32 | if (unlikely(sh == 0 && mb == 0)) { |
1827 | d03ef511 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1828 | d03ef511 | aurel32 | } else {
|
1829 | d03ef511 | aurel32 | TCGv t0, t1; |
1830 | d03ef511 | aurel32 | target_ulong mask; |
1831 | d03ef511 | aurel32 | |
1832 | a7812ae4 | pbrook | t0 = tcg_temp_new(); |
1833 | 54843a58 | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
1834 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1835 | d03ef511 | aurel32 | mask = MASK(mb, me); |
1836 | d03ef511 | aurel32 | tcg_gen_andi_tl(t0, t0, mask); |
1837 | d03ef511 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); |
1838 | d03ef511 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1839 | d03ef511 | aurel32 | tcg_temp_free(t0); |
1840 | d03ef511 | aurel32 | tcg_temp_free(t1); |
1841 | 51789c41 | j_mayer | } |
1842 | 51789c41 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
1843 | d03ef511 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1844 | d9bce9d9 | j_mayer | } |
1845 | 36081602 | j_mayer | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
1846 | d9bce9d9 | j_mayer | #endif
|
1847 | d9bce9d9 | j_mayer | |
1848 | 79aceca5 | bellard | /*** Integer shift ***/
|
1849 | 99e300ef | Blue Swirl | |
1850 | 54623277 | Blue Swirl | /* slw & slw. */
|
1851 | 99e300ef | Blue Swirl | static void gen_slw(DisasContext *ctx) |
1852 | 26d67362 | aurel32 | { |
1853 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1854 | 26d67362 | aurel32 | |
1855 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1856 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x20 */
|
1857 | 7fd6bf7d | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1858 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
|
1859 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1860 | 7fd6bf7d | Aurelien Jarno | #else
|
1861 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
|
1862 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x1f);
|
1863 | 7fd6bf7d | Aurelien Jarno | #endif
|
1864 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1865 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1866 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1867 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1868 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1869 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1870 | 7fd6bf7d | Aurelien Jarno | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1871 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1872 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1873 | 26d67362 | aurel32 | } |
1874 | 99e300ef | Blue Swirl | |
1875 | 54623277 | Blue Swirl | /* sraw & sraw. */
|
1876 | 99e300ef | Blue Swirl | static void gen_sraw(DisasContext *ctx) |
1877 | 26d67362 | aurel32 | { |
1878 | d15f74fb | Blue Swirl | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
1879 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1880 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1881 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1882 | 26d67362 | aurel32 | } |
1883 | 99e300ef | Blue Swirl | |
1884 | 54623277 | Blue Swirl | /* srawi & srawi. */
|
1885 | 99e300ef | Blue Swirl | static void gen_srawi(DisasContext *ctx) |
1886 | 79aceca5 | bellard | { |
1887 | 26d67362 | aurel32 | int sh = SH(ctx->opcode);
|
1888 | ba4af3e4 | Richard Henderson | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1889 | ba4af3e4 | Richard Henderson | TCGv src = cpu_gpr[rS(ctx->opcode)]; |
1890 | ba4af3e4 | Richard Henderson | if (sh == 0) { |
1891 | ba4af3e4 | Richard Henderson | tcg_gen_mov_tl(dst, src); |
1892 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 0);
|
1893 | 26d67362 | aurel32 | } else {
|
1894 | ba4af3e4 | Richard Henderson | TCGv t0; |
1895 | ba4af3e4 | Richard Henderson | tcg_gen_ext32s_tl(dst, src); |
1896 | ba4af3e4 | Richard Henderson | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); |
1897 | ba4af3e4 | Richard Henderson | t0 = tcg_temp_new(); |
1898 | ba4af3e4 | Richard Henderson | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
|
1899 | ba4af3e4 | Richard Henderson | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); |
1900 | ba4af3e4 | Richard Henderson | tcg_temp_free(t0); |
1901 | ba4af3e4 | Richard Henderson | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
|
1902 | ba4af3e4 | Richard Henderson | tcg_gen_sari_tl(dst, dst, sh); |
1903 | ba4af3e4 | Richard Henderson | } |
1904 | ba4af3e4 | Richard Henderson | if (unlikely(Rc(ctx->opcode) != 0)) { |
1905 | ba4af3e4 | Richard Henderson | gen_set_Rc0(ctx, dst); |
1906 | d9bce9d9 | j_mayer | } |
1907 | 79aceca5 | bellard | } |
1908 | 99e300ef | Blue Swirl | |
1909 | 54623277 | Blue Swirl | /* srw & srw. */
|
1910 | 99e300ef | Blue Swirl | static void gen_srw(DisasContext *ctx) |
1911 | 26d67362 | aurel32 | { |
1912 | fea0c503 | aurel32 | TCGv t0, t1; |
1913 | d9bce9d9 | j_mayer | |
1914 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1915 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x20 */
|
1916 | 7fd6bf7d | Aurelien Jarno | #if defined(TARGET_PPC64)
|
1917 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
|
1918 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1919 | 7fd6bf7d | Aurelien Jarno | #else
|
1920 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
|
1921 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x1f);
|
1922 | 7fd6bf7d | Aurelien Jarno | #endif
|
1923 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1924 | 7fd6bf7d | Aurelien Jarno | tcg_gen_ext32u_tl(t0, t0); |
1925 | a7812ae4 | pbrook | t1 = tcg_temp_new(); |
1926 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
|
1927 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1928 | fea0c503 | aurel32 | tcg_temp_free(t1); |
1929 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1930 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1931 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1932 | 26d67362 | aurel32 | } |
1933 | 54623277 | Blue Swirl | |
1934 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
1935 | d9bce9d9 | j_mayer | /* sld & sld. */
|
1936 | 99e300ef | Blue Swirl | static void gen_sld(DisasContext *ctx) |
1937 | 26d67362 | aurel32 | { |
1938 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
1939 | 26d67362 | aurel32 | |
1940 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
1941 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x40 */
|
1942 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
|
1943 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
1944 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
1945 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
1946 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
1947 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
1948 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
1949 | fea0c503 | aurel32 | tcg_temp_free(t0); |
1950 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1951 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1952 | 26d67362 | aurel32 | } |
1953 | 99e300ef | Blue Swirl | |
1954 | 54623277 | Blue Swirl | /* srad & srad. */
|
1955 | 99e300ef | Blue Swirl | static void gen_srad(DisasContext *ctx) |
1956 | 26d67362 | aurel32 | { |
1957 | d15f74fb | Blue Swirl | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
1958 | a7812ae4 | pbrook | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1959 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
1960 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1961 | 26d67362 | aurel32 | } |
1962 | d9bce9d9 | j_mayer | /* sradi & sradi. */
|
1963 | 636aa200 | Blue Swirl | static inline void gen_sradi(DisasContext *ctx, int n) |
1964 | d9bce9d9 | j_mayer | { |
1965 | 26d67362 | aurel32 | int sh = SH(ctx->opcode) + (n << 5); |
1966 | ba4af3e4 | Richard Henderson | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1967 | ba4af3e4 | Richard Henderson | TCGv src = cpu_gpr[rS(ctx->opcode)]; |
1968 | ba4af3e4 | Richard Henderson | if (sh == 0) { |
1969 | ba4af3e4 | Richard Henderson | tcg_gen_mov_tl(dst, src); |
1970 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 0);
|
1971 | 26d67362 | aurel32 | } else {
|
1972 | ba4af3e4 | Richard Henderson | TCGv t0; |
1973 | ba4af3e4 | Richard Henderson | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); |
1974 | ba4af3e4 | Richard Henderson | t0 = tcg_temp_new(); |
1975 | ba4af3e4 | Richard Henderson | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
|
1976 | ba4af3e4 | Richard Henderson | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); |
1977 | ba4af3e4 | Richard Henderson | tcg_temp_free(t0); |
1978 | ba4af3e4 | Richard Henderson | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
|
1979 | ba4af3e4 | Richard Henderson | tcg_gen_sari_tl(dst, src, sh); |
1980 | ba4af3e4 | Richard Henderson | } |
1981 | ba4af3e4 | Richard Henderson | if (unlikely(Rc(ctx->opcode) != 0)) { |
1982 | ba4af3e4 | Richard Henderson | gen_set_Rc0(ctx, dst); |
1983 | d9bce9d9 | j_mayer | } |
1984 | d9bce9d9 | j_mayer | } |
1985 | e8eaa2c0 | Blue Swirl | |
1986 | e8eaa2c0 | Blue Swirl | static void gen_sradi0(DisasContext *ctx) |
1987 | d9bce9d9 | j_mayer | { |
1988 | d9bce9d9 | j_mayer | gen_sradi(ctx, 0);
|
1989 | d9bce9d9 | j_mayer | } |
1990 | e8eaa2c0 | Blue Swirl | |
1991 | e8eaa2c0 | Blue Swirl | static void gen_sradi1(DisasContext *ctx) |
1992 | d9bce9d9 | j_mayer | { |
1993 | d9bce9d9 | j_mayer | gen_sradi(ctx, 1);
|
1994 | d9bce9d9 | j_mayer | } |
1995 | 99e300ef | Blue Swirl | |
1996 | 54623277 | Blue Swirl | /* srd & srd. */
|
1997 | 99e300ef | Blue Swirl | static void gen_srd(DisasContext *ctx) |
1998 | 26d67362 | aurel32 | { |
1999 | 7fd6bf7d | Aurelien Jarno | TCGv t0, t1; |
2000 | 26d67362 | aurel32 | |
2001 | 7fd6bf7d | Aurelien Jarno | t0 = tcg_temp_new(); |
2002 | 7fd6bf7d | Aurelien Jarno | /* AND rS with a mask that is 0 when rB >= 0x40 */
|
2003 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
|
2004 | 7fd6bf7d | Aurelien Jarno | tcg_gen_sari_tl(t0, t0, 0x3f);
|
2005 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
2006 | 7fd6bf7d | Aurelien Jarno | t1 = tcg_temp_new(); |
2007 | 7fd6bf7d | Aurelien Jarno | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
|
2008 | 7fd6bf7d | Aurelien Jarno | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
2009 | 7fd6bf7d | Aurelien Jarno | tcg_temp_free(t1); |
2010 | fea0c503 | aurel32 | tcg_temp_free(t0); |
2011 | 26d67362 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
2012 | 26d67362 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2013 | 26d67362 | aurel32 | } |
2014 | d9bce9d9 | j_mayer | #endif
|
2015 | 79aceca5 | bellard | |
2016 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
2017 | 7c58044c | j_mayer | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
2018 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2019 | 9a64fbe4 | bellard | { \ |
2020 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2021 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2022 | 3cc62370 | bellard | return; \
|
2023 | 3cc62370 | bellard | } \ |
2024 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2025 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2026 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2027 | 8e703949 | Blue Swirl | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2028 | 8e703949 | Blue Swirl | cpu_fpr[rA(ctx->opcode)], \ |
2029 | af12906f | aurel32 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2030 | 4ecc3190 | bellard | if (isfloat) { \
|
2031 | 8e703949 | Blue Swirl | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2032 | 8e703949 | Blue Swirl | cpu_fpr[rD(ctx->opcode)]); \ |
2033 | 4ecc3190 | bellard | } \ |
2034 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2035 | af12906f | aurel32 | Rc(ctx->opcode) != 0); \
|
2036 | 9a64fbe4 | bellard | } |
2037 | 9a64fbe4 | bellard | |
2038 | 7c58044c | j_mayer | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
2039 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ |
2040 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); |
2041 | 9a64fbe4 | bellard | |
2042 | 7c58044c | j_mayer | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
2043 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2044 | 9a64fbe4 | bellard | { \ |
2045 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2046 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2047 | 3cc62370 | bellard | return; \
|
2048 | 3cc62370 | bellard | } \ |
2049 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2050 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2051 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2052 | 8e703949 | Blue Swirl | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2053 | 8e703949 | Blue Swirl | cpu_fpr[rA(ctx->opcode)], \ |
2054 | af12906f | aurel32 | cpu_fpr[rB(ctx->opcode)]); \ |
2055 | 4ecc3190 | bellard | if (isfloat) { \
|
2056 | 8e703949 | Blue Swirl | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2057 | 8e703949 | Blue Swirl | cpu_fpr[rD(ctx->opcode)]); \ |
2058 | 4ecc3190 | bellard | } \ |
2059 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2060 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2061 | 9a64fbe4 | bellard | } |
2062 | 7c58044c | j_mayer | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
2063 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2064 | 7c58044c | j_mayer | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2065 | 9a64fbe4 | bellard | |
2066 | 7c58044c | j_mayer | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
2067 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2068 | 9a64fbe4 | bellard | { \ |
2069 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2070 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2071 | 3cc62370 | bellard | return; \
|
2072 | 3cc62370 | bellard | } \ |
2073 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2074 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2075 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2076 | 8e703949 | Blue Swirl | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2077 | 8e703949 | Blue Swirl | cpu_fpr[rA(ctx->opcode)], \ |
2078 | 8e703949 | Blue Swirl | cpu_fpr[rC(ctx->opcode)]); \ |
2079 | 4ecc3190 | bellard | if (isfloat) { \
|
2080 | 8e703949 | Blue Swirl | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2081 | 8e703949 | Blue Swirl | cpu_fpr[rD(ctx->opcode)]); \ |
2082 | 4ecc3190 | bellard | } \ |
2083 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2084 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2085 | 9a64fbe4 | bellard | } |
2086 | 7c58044c | j_mayer | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
2087 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ |
2088 | 7c58044c | j_mayer | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); |
2089 | 9a64fbe4 | bellard | |
2090 | 7c58044c | j_mayer | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
2091 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2092 | 9a64fbe4 | bellard | { \ |
2093 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2094 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2095 | 3cc62370 | bellard | return; \
|
2096 | 3cc62370 | bellard | } \ |
2097 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2098 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2099 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2100 | 8e703949 | Blue Swirl | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2101 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)]); \ |
2102 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2103 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2104 | 79aceca5 | bellard | } |
2105 | 79aceca5 | bellard | |
2106 | 7c58044c | j_mayer | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
2107 | 99e300ef | Blue Swirl | static void gen_f##name(DisasContext *ctx) \ |
2108 | 9a64fbe4 | bellard | { \ |
2109 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
2110 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
2111 | 3cc62370 | bellard | return; \
|
2112 | 3cc62370 | bellard | } \ |
2113 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
2114 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4); \
|
2115 | 7c58044c | j_mayer | gen_reset_fpstatus(); \ |
2116 | 8e703949 | Blue Swirl | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2117 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)]); \ |
2118 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2119 | af12906f | aurel32 | set_fprf, Rc(ctx->opcode) != 0); \
|
2120 | 79aceca5 | bellard | } |
2121 | 79aceca5 | bellard | |
2122 | 9a64fbe4 | bellard | /* fadd - fadds */
|
2123 | 7c58044c | j_mayer | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
2124 | 4ecc3190 | bellard | /* fdiv - fdivs */
|
2125 | 7c58044c | j_mayer | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
2126 | 4ecc3190 | bellard | /* fmul - fmuls */
|
2127 | 7c58044c | j_mayer | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
2128 | 79aceca5 | bellard | |
2129 | d7e4b87e | j_mayer | /* fre */
|
2130 | 7c58044c | j_mayer | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
2131 | d7e4b87e | j_mayer | |
2132 | a750fc0b | j_mayer | /* fres */
|
2133 | 7c58044c | j_mayer | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
2134 | 79aceca5 | bellard | |
2135 | a750fc0b | j_mayer | /* frsqrte */
|
2136 | 7c58044c | j_mayer | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2137 | 7c58044c | j_mayer | |
2138 | 7c58044c | j_mayer | /* frsqrtes */
|
2139 | 99e300ef | Blue Swirl | static void gen_frsqrtes(DisasContext *ctx) |
2140 | 7c58044c | j_mayer | { |
2141 | af12906f | aurel32 | if (unlikely(!ctx->fpu_enabled)) {
|
2142 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2143 | af12906f | aurel32 | return;
|
2144 | af12906f | aurel32 | } |
2145 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2146 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2147 | af12906f | aurel32 | gen_reset_fpstatus(); |
2148 | 8e703949 | Blue Swirl | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2149 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)]); |
2150 | 8e703949 | Blue Swirl | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2151 | 8e703949 | Blue Swirl | cpu_fpr[rD(ctx->opcode)]); |
2152 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2153 | 7c58044c | j_mayer | } |
2154 | 79aceca5 | bellard | |
2155 | a750fc0b | j_mayer | /* fsel */
|
2156 | 7c58044c | j_mayer | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
2157 | 4ecc3190 | bellard | /* fsub - fsubs */
|
2158 | 7c58044c | j_mayer | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
2159 | 79aceca5 | bellard | /* Optional: */
|
2160 | 99e300ef | Blue Swirl | |
2161 | 54623277 | Blue Swirl | /* fsqrt */
|
2162 | 99e300ef | Blue Swirl | static void gen_fsqrt(DisasContext *ctx) |
2163 | c7d344af | bellard | { |
2164 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2165 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2166 | c7d344af | bellard | return;
|
2167 | c7d344af | bellard | } |
2168 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2169 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2170 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2171 | 8e703949 | Blue Swirl | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2172 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)]); |
2173 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2174 | c7d344af | bellard | } |
2175 | 79aceca5 | bellard | |
2176 | 99e300ef | Blue Swirl | static void gen_fsqrts(DisasContext *ctx) |
2177 | 79aceca5 | bellard | { |
2178 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2179 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2180 | 3cc62370 | bellard | return;
|
2181 | 3cc62370 | bellard | } |
2182 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2183 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2184 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2185 | 8e703949 | Blue Swirl | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2186 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)]); |
2187 | 8e703949 | Blue Swirl | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2188 | 8e703949 | Blue Swirl | cpu_fpr[rD(ctx->opcode)]); |
2189 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
2190 | 79aceca5 | bellard | } |
2191 | 79aceca5 | bellard | |
2192 | 79aceca5 | bellard | /*** Floating-Point multiply-and-add ***/
|
2193 | 4ecc3190 | bellard | /* fmadd - fmadds */
|
2194 | 7c58044c | j_mayer | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
2195 | 4ecc3190 | bellard | /* fmsub - fmsubs */
|
2196 | 7c58044c | j_mayer | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
2197 | 4ecc3190 | bellard | /* fnmadd - fnmadds */
|
2198 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
2199 | 4ecc3190 | bellard | /* fnmsub - fnmsubs */
|
2200 | 7c58044c | j_mayer | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
2201 | 79aceca5 | bellard | |
2202 | 79aceca5 | bellard | /*** Floating-Point round & convert ***/
|
2203 | 79aceca5 | bellard | /* fctiw */
|
2204 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
2205 | fab7fe42 | Tom Musta | /* fctiwu */
|
2206 | fab7fe42 | Tom Musta | GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); |
2207 | 79aceca5 | bellard | /* fctiwz */
|
2208 | 7c58044c | j_mayer | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
2209 | fab7fe42 | Tom Musta | /* fctiwuz */
|
2210 | fab7fe42 | Tom Musta | GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); |
2211 | 79aceca5 | bellard | /* frsp */
|
2212 | 7c58044c | j_mayer | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
2213 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
2214 | 426613db | j_mayer | /* fcfid */
|
2215 | 7c58044c | j_mayer | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
2216 | 426613db | j_mayer | /* fctid */
|
2217 | 7c58044c | j_mayer | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
2218 | fab7fe42 | Tom Musta | /* fctidu */
|
2219 | fab7fe42 | Tom Musta | GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); |
2220 | 426613db | j_mayer | /* fctidz */
|
2221 | 7c58044c | j_mayer | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
2222 | fab7fe42 | Tom Musta | /* fctidu */
|
2223 | fab7fe42 | Tom Musta | GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); |
2224 | 426613db | j_mayer | #endif
|
2225 | 79aceca5 | bellard | |
2226 | d7e4b87e | j_mayer | /* frin */
|
2227 | 7c58044c | j_mayer | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
2228 | d7e4b87e | j_mayer | /* friz */
|
2229 | 7c58044c | j_mayer | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
2230 | d7e4b87e | j_mayer | /* frip */
|
2231 | 7c58044c | j_mayer | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
2232 | d7e4b87e | j_mayer | /* frim */
|
2233 | 7c58044c | j_mayer | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
2234 | d7e4b87e | j_mayer | |
2235 | 79aceca5 | bellard | /*** Floating-Point compare ***/
|
2236 | 99e300ef | Blue Swirl | |
2237 | 54623277 | Blue Swirl | /* fcmpo */
|
2238 | 99e300ef | Blue Swirl | static void gen_fcmpo(DisasContext *ctx) |
2239 | 79aceca5 | bellard | { |
2240 | 330c483b | aurel32 | TCGv_i32 crf; |
2241 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2242 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2243 | 3cc62370 | bellard | return;
|
2244 | 3cc62370 | bellard | } |
2245 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2246 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2247 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2248 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2249 | 8e703949 | Blue Swirl | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2250 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)], crf); |
2251 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2252 | 8e703949 | Blue Swirl | gen_helper_float_check_status(cpu_env); |
2253 | 79aceca5 | bellard | } |
2254 | 79aceca5 | bellard | |
2255 | 79aceca5 | bellard | /* fcmpu */
|
2256 | 99e300ef | Blue Swirl | static void gen_fcmpu(DisasContext *ctx) |
2257 | 79aceca5 | bellard | { |
2258 | 330c483b | aurel32 | TCGv_i32 crf; |
2259 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2260 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2261 | 3cc62370 | bellard | return;
|
2262 | 3cc62370 | bellard | } |
2263 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2264 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2265 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2266 | 9a819377 | aurel32 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2267 | 8e703949 | Blue Swirl | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2268 | 8e703949 | Blue Swirl | cpu_fpr[rB(ctx->opcode)], crf); |
2269 | 330c483b | aurel32 | tcg_temp_free_i32(crf); |
2270 | 8e703949 | Blue Swirl | gen_helper_float_check_status(cpu_env); |
2271 | 79aceca5 | bellard | } |
2272 | 79aceca5 | bellard | |
2273 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
2274 | 9a64fbe4 | bellard | /* fabs */
|
2275 | 7c58044c | j_mayer | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
|
2276 | bf45a2e6 | Aurelien Jarno | static void gen_fabs(DisasContext *ctx) |
2277 | bf45a2e6 | Aurelien Jarno | { |
2278 | bf45a2e6 | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
2279 | bf45a2e6 | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
2280 | bf45a2e6 | Aurelien Jarno | return;
|
2281 | bf45a2e6 | Aurelien Jarno | } |
2282 | bf45a2e6 | Aurelien Jarno | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], |
2283 | bf45a2e6 | Aurelien Jarno | ~(1ULL << 63)); |
2284 | bf45a2e6 | Aurelien Jarno | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2285 | bf45a2e6 | Aurelien Jarno | } |
2286 | 9a64fbe4 | bellard | |
2287 | 9a64fbe4 | bellard | /* fmr - fmr. */
|
2288 | 7c58044c | j_mayer | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
|
2289 | 99e300ef | Blue Swirl | static void gen_fmr(DisasContext *ctx) |
2290 | 9a64fbe4 | bellard | { |
2291 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2292 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2293 | 3cc62370 | bellard | return;
|
2294 | 3cc62370 | bellard | } |
2295 | af12906f | aurel32 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2296 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2297 | 9a64fbe4 | bellard | } |
2298 | 9a64fbe4 | bellard | |
2299 | 9a64fbe4 | bellard | /* fnabs */
|
2300 | 7c58044c | j_mayer | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
|
2301 | bf45a2e6 | Aurelien Jarno | static void gen_fnabs(DisasContext *ctx) |
2302 | bf45a2e6 | Aurelien Jarno | { |
2303 | bf45a2e6 | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
2304 | bf45a2e6 | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
2305 | bf45a2e6 | Aurelien Jarno | return;
|
2306 | bf45a2e6 | Aurelien Jarno | } |
2307 | bf45a2e6 | Aurelien Jarno | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], |
2308 | bf45a2e6 | Aurelien Jarno | 1ULL << 63); |
2309 | bf45a2e6 | Aurelien Jarno | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2310 | bf45a2e6 | Aurelien Jarno | } |
2311 | bf45a2e6 | Aurelien Jarno | |
2312 | 9a64fbe4 | bellard | /* fneg */
|
2313 | 7c58044c | j_mayer | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
|
2314 | bf45a2e6 | Aurelien Jarno | static void gen_fneg(DisasContext *ctx) |
2315 | bf45a2e6 | Aurelien Jarno | { |
2316 | bf45a2e6 | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
2317 | bf45a2e6 | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
2318 | bf45a2e6 | Aurelien Jarno | return;
|
2319 | bf45a2e6 | Aurelien Jarno | } |
2320 | bf45a2e6 | Aurelien Jarno | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], |
2321 | bf45a2e6 | Aurelien Jarno | 1ULL << 63); |
2322 | bf45a2e6 | Aurelien Jarno | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2323 | bf45a2e6 | Aurelien Jarno | } |
2324 | 9a64fbe4 | bellard | |
2325 | f0332888 | Aurelien Jarno | /* fcpsgn: PowerPC 2.05 specification */
|
2326 | f0332888 | Aurelien Jarno | /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
|
2327 | f0332888 | Aurelien Jarno | static void gen_fcpsgn(DisasContext *ctx) |
2328 | f0332888 | Aurelien Jarno | { |
2329 | f0332888 | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
2330 | f0332888 | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
2331 | f0332888 | Aurelien Jarno | return;
|
2332 | f0332888 | Aurelien Jarno | } |
2333 | f0332888 | Aurelien Jarno | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], |
2334 | f0332888 | Aurelien Jarno | cpu_fpr[rB(ctx->opcode)], 0, 63); |
2335 | f0332888 | Aurelien Jarno | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2336 | f0332888 | Aurelien Jarno | } |
2337 | f0332888 | Aurelien Jarno | |
2338 | 097ec5d8 | Tom Musta | static void gen_fmrgew(DisasContext *ctx) |
2339 | 097ec5d8 | Tom Musta | { |
2340 | 097ec5d8 | Tom Musta | TCGv_i64 b0; |
2341 | 097ec5d8 | Tom Musta | if (unlikely(!ctx->fpu_enabled)) {
|
2342 | 097ec5d8 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_FPU); |
2343 | 097ec5d8 | Tom Musta | return;
|
2344 | 097ec5d8 | Tom Musta | } |
2345 | 097ec5d8 | Tom Musta | b0 = tcg_temp_new_i64(); |
2346 | 097ec5d8 | Tom Musta | tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
|
2347 | 097ec5d8 | Tom Musta | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], |
2348 | 097ec5d8 | Tom Musta | b0, 0, 32); |
2349 | 097ec5d8 | Tom Musta | tcg_temp_free_i64(b0); |
2350 | 097ec5d8 | Tom Musta | } |
2351 | 097ec5d8 | Tom Musta | |
2352 | 097ec5d8 | Tom Musta | static void gen_fmrgow(DisasContext *ctx) |
2353 | 097ec5d8 | Tom Musta | { |
2354 | 097ec5d8 | Tom Musta | if (unlikely(!ctx->fpu_enabled)) {
|
2355 | 097ec5d8 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_FPU); |
2356 | 097ec5d8 | Tom Musta | return;
|
2357 | 097ec5d8 | Tom Musta | } |
2358 | 097ec5d8 | Tom Musta | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], |
2359 | 097ec5d8 | Tom Musta | cpu_fpr[rB(ctx->opcode)], |
2360 | 097ec5d8 | Tom Musta | cpu_fpr[rA(ctx->opcode)], |
2361 | 097ec5d8 | Tom Musta | 32, 32); |
2362 | 097ec5d8 | Tom Musta | } |
2363 | 097ec5d8 | Tom Musta | |
2364 | 79aceca5 | bellard | /*** Floating-Point status & ctrl register ***/
|
2365 | 99e300ef | Blue Swirl | |
2366 | 54623277 | Blue Swirl | /* mcrfs */
|
2367 | 99e300ef | Blue Swirl | static void gen_mcrfs(DisasContext *ctx) |
2368 | 79aceca5 | bellard | { |
2369 | 30304420 | David Gibson | TCGv tmp = tcg_temp_new(); |
2370 | 7c58044c | j_mayer | int bfa;
|
2371 | 7c58044c | j_mayer | |
2372 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2373 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2374 | 3cc62370 | bellard | return;
|
2375 | 3cc62370 | bellard | } |
2376 | 7c58044c | j_mayer | bfa = 4 * (7 - crfS(ctx->opcode)); |
2377 | 30304420 | David Gibson | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2378 | 30304420 | David Gibson | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); |
2379 | 30304420 | David Gibson | tcg_temp_free(tmp); |
2380 | e1571908 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
|
2381 | 30304420 | David Gibson | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
|
2382 | 79aceca5 | bellard | } |
2383 | 79aceca5 | bellard | |
2384 | 79aceca5 | bellard | /* mffs */
|
2385 | 99e300ef | Blue Swirl | static void gen_mffs(DisasContext *ctx) |
2386 | 79aceca5 | bellard | { |
2387 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2388 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2389 | 3cc62370 | bellard | return;
|
2390 | 3cc62370 | bellard | } |
2391 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2392 | 30304420 | David Gibson | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2393 | af12906f | aurel32 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
2394 | 79aceca5 | bellard | } |
2395 | 79aceca5 | bellard | |
2396 | 79aceca5 | bellard | /* mtfsb0 */
|
2397 | 99e300ef | Blue Swirl | static void gen_mtfsb0(DisasContext *ctx) |
2398 | 79aceca5 | bellard | { |
2399 | fb0eaffc | bellard | uint8_t crb; |
2400 | 3b46e624 | ths | |
2401 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2402 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2403 | 3cc62370 | bellard | return;
|
2404 | 3cc62370 | bellard | } |
2405 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2406 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2407 | 6e35d524 | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
|
2408 | eb44b959 | aurel32 | TCGv_i32 t0; |
2409 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2410 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2411 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2412 | 8e703949 | Blue Swirl | gen_helper_fpscr_clrbit(cpu_env, t0); |
2413 | 6e35d524 | aurel32 | tcg_temp_free_i32(t0); |
2414 | 6e35d524 | aurel32 | } |
2415 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2416 | 30304420 | David Gibson | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
|
2417 | 30304420 | David Gibson | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); |
2418 | 7c58044c | j_mayer | } |
2419 | 79aceca5 | bellard | } |
2420 | 79aceca5 | bellard | |
2421 | 79aceca5 | bellard | /* mtfsb1 */
|
2422 | 99e300ef | Blue Swirl | static void gen_mtfsb1(DisasContext *ctx) |
2423 | 79aceca5 | bellard | { |
2424 | fb0eaffc | bellard | uint8_t crb; |
2425 | 3b46e624 | ths | |
2426 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2427 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2428 | 3cc62370 | bellard | return;
|
2429 | 3cc62370 | bellard | } |
2430 | 6e35d524 | aurel32 | crb = 31 - crbD(ctx->opcode);
|
2431 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2432 | 7c58044c | j_mayer | /* XXX: we pretend we can only do IEEE floating-point computations */
|
2433 | af12906f | aurel32 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
|
2434 | eb44b959 | aurel32 | TCGv_i32 t0; |
2435 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2436 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2437 | eb44b959 | aurel32 | t0 = tcg_const_i32(crb); |
2438 | 8e703949 | Blue Swirl | gen_helper_fpscr_setbit(cpu_env, t0); |
2439 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2440 | af12906f | aurel32 | } |
2441 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2442 | 30304420 | David Gibson | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
|
2443 | 30304420 | David Gibson | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); |
2444 | 7c58044c | j_mayer | } |
2445 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2446 | 8e703949 | Blue Swirl | gen_helper_float_check_status(cpu_env); |
2447 | 79aceca5 | bellard | } |
2448 | 79aceca5 | bellard | |
2449 | 79aceca5 | bellard | /* mtfsf */
|
2450 | 99e300ef | Blue Swirl | static void gen_mtfsf(DisasContext *ctx) |
2451 | 79aceca5 | bellard | { |
2452 | 0f2f39c2 | aurel32 | TCGv_i32 t0; |
2453 | 7d08d856 | Aurelien Jarno | int flm, l, w;
|
2454 | af12906f | aurel32 | |
2455 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2456 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2457 | 3cc62370 | bellard | return;
|
2458 | 3cc62370 | bellard | } |
2459 | 7d08d856 | Aurelien Jarno | flm = FPFLM(ctx->opcode); |
2460 | 7d08d856 | Aurelien Jarno | l = FPL(ctx->opcode); |
2461 | 7d08d856 | Aurelien Jarno | w = FPW(ctx->opcode); |
2462 | 7d08d856 | Aurelien Jarno | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
|
2463 | 7d08d856 | Aurelien Jarno | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2464 | 7d08d856 | Aurelien Jarno | return;
|
2465 | 7d08d856 | Aurelien Jarno | } |
2466 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2467 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2468 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2469 | 7d08d856 | Aurelien Jarno | if (l) {
|
2470 | 7d08d856 | Aurelien Jarno | t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); |
2471 | 7d08d856 | Aurelien Jarno | } else {
|
2472 | 7d08d856 | Aurelien Jarno | t0 = tcg_const_i32(flm << (w * 8));
|
2473 | 7d08d856 | Aurelien Jarno | } |
2474 | 8e703949 | Blue Swirl | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
2475 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t0); |
2476 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2477 | 30304420 | David Gibson | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
|
2478 | 30304420 | David Gibson | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); |
2479 | 7c58044c | j_mayer | } |
2480 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2481 | 8e703949 | Blue Swirl | gen_helper_float_check_status(cpu_env); |
2482 | 79aceca5 | bellard | } |
2483 | 79aceca5 | bellard | |
2484 | 79aceca5 | bellard | /* mtfsfi */
|
2485 | 99e300ef | Blue Swirl | static void gen_mtfsfi(DisasContext *ctx) |
2486 | 79aceca5 | bellard | { |
2487 | 7d08d856 | Aurelien Jarno | int bf, sh, w;
|
2488 | 0f2f39c2 | aurel32 | TCGv_i64 t0; |
2489 | 0f2f39c2 | aurel32 | TCGv_i32 t1; |
2490 | 7c58044c | j_mayer | |
2491 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) {
|
2492 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); |
2493 | 3cc62370 | bellard | return;
|
2494 | 3cc62370 | bellard | } |
2495 | 7d08d856 | Aurelien Jarno | w = FPW(ctx->opcode); |
2496 | 7d08d856 | Aurelien Jarno | bf = FPBF(ctx->opcode); |
2497 | 7d08d856 | Aurelien Jarno | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
|
2498 | 7d08d856 | Aurelien Jarno | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2499 | 7d08d856 | Aurelien Jarno | return;
|
2500 | 7d08d856 | Aurelien Jarno | } |
2501 | 7d08d856 | Aurelien Jarno | sh = (8 * w) + 7 - bf; |
2502 | eb44b959 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2503 | eb44b959 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2504 | 7c58044c | j_mayer | gen_reset_fpstatus(); |
2505 | 7d08d856 | Aurelien Jarno | t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
|
2506 | af12906f | aurel32 | t1 = tcg_const_i32(1 << sh);
|
2507 | 8e703949 | Blue Swirl | gen_helper_store_fpscr(cpu_env, t0, t1); |
2508 | 0f2f39c2 | aurel32 | tcg_temp_free_i64(t0); |
2509 | 0f2f39c2 | aurel32 | tcg_temp_free_i32(t1); |
2510 | 7c58044c | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) { |
2511 | 30304420 | David Gibson | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
|
2512 | 30304420 | David Gibson | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); |
2513 | 7c58044c | j_mayer | } |
2514 | 7c58044c | j_mayer | /* We can raise a differed exception */
|
2515 | 8e703949 | Blue Swirl | gen_helper_float_check_status(cpu_env); |
2516 | 79aceca5 | bellard | } |
2517 | 79aceca5 | bellard | |
2518 | 76a66253 | j_mayer | /*** Addressing modes ***/
|
2519 | 76a66253 | j_mayer | /* Register indirect with immediate index : EA = (rA|0) + SIMM */
|
2520 | 636aa200 | Blue Swirl | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2521 | 636aa200 | Blue Swirl | target_long maskl) |
2522 | 76a66253 | j_mayer | { |
2523 | 76a66253 | j_mayer | target_long simm = SIMM(ctx->opcode); |
2524 | 76a66253 | j_mayer | |
2525 | be147d08 | j_mayer | simm &= ~maskl; |
2526 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2527 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
2528 | c791fe84 | Richard Henderson | simm = (uint32_t)simm; |
2529 | c791fe84 | Richard Henderson | } |
2530 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, simm); |
2531 | 76db3ba4 | aurel32 | } else if (likely(simm != 0)) { |
2532 | e2be8d8d | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
2533 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
2534 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2535 | 76db3ba4 | aurel32 | } |
2536 | 76db3ba4 | aurel32 | } else {
|
2537 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
2538 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2539 | c791fe84 | Richard Henderson | } else {
|
2540 | c791fe84 | Richard Henderson | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2541 | c791fe84 | Richard Henderson | } |
2542 | 76db3ba4 | aurel32 | } |
2543 | 76a66253 | j_mayer | } |
2544 | 76a66253 | j_mayer | |
2545 | 636aa200 | Blue Swirl | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
2546 | 76a66253 | j_mayer | { |
2547 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2548 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
2549 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2550 | c791fe84 | Richard Henderson | } else {
|
2551 | c791fe84 | Richard Henderson | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2552 | c791fe84 | Richard Henderson | } |
2553 | 76db3ba4 | aurel32 | } else {
|
2554 | e2be8d8d | aurel32 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2555 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
2556 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
2557 | 76db3ba4 | aurel32 | } |
2558 | 76db3ba4 | aurel32 | } |
2559 | 76a66253 | j_mayer | } |
2560 | 76a66253 | j_mayer | |
2561 | 636aa200 | Blue Swirl | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
2562 | 76a66253 | j_mayer | { |
2563 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
2564 | e2be8d8d | aurel32 | tcg_gen_movi_tl(EA, 0);
|
2565 | c791fe84 | Richard Henderson | } else if (NARROW_MODE(ctx)) { |
2566 | c791fe84 | Richard Henderson | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2567 | 76db3ba4 | aurel32 | } else {
|
2568 | c791fe84 | Richard Henderson | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2569 | 76db3ba4 | aurel32 | } |
2570 | 76db3ba4 | aurel32 | } |
2571 | 76db3ba4 | aurel32 | |
2572 | 636aa200 | Blue Swirl | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2573 | 636aa200 | Blue Swirl | target_long val) |
2574 | 76db3ba4 | aurel32 | { |
2575 | 76db3ba4 | aurel32 | tcg_gen_addi_tl(ret, arg1, val); |
2576 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
2577 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(ret, ret); |
2578 | 76db3ba4 | aurel32 | } |
2579 | 76a66253 | j_mayer | } |
2580 | 76a66253 | j_mayer | |
2581 | 636aa200 | Blue Swirl | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
2582 | cf360a32 | aurel32 | { |
2583 | cf360a32 | aurel32 | int l1 = gen_new_label();
|
2584 | cf360a32 | aurel32 | TCGv t0 = tcg_temp_new(); |
2585 | cf360a32 | aurel32 | TCGv_i32 t1, t2; |
2586 | cf360a32 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
2587 | cf360a32 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
2588 | cf360a32 | aurel32 | tcg_gen_andi_tl(t0, EA, mask); |
2589 | cf360a32 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
2590 | cf360a32 | aurel32 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); |
2591 | cf360a32 | aurel32 | t2 = tcg_const_i32(0);
|
2592 | e5f17ac6 | Blue Swirl | gen_helper_raise_exception_err(cpu_env, t1, t2); |
2593 | cf360a32 | aurel32 | tcg_temp_free_i32(t1); |
2594 | cf360a32 | aurel32 | tcg_temp_free_i32(t2); |
2595 | cf360a32 | aurel32 | gen_set_label(l1); |
2596 | cf360a32 | aurel32 | tcg_temp_free(t0); |
2597 | cf360a32 | aurel32 | } |
2598 | cf360a32 | aurel32 | |
2599 | 7863667f | j_mayer | /*** Integer load ***/
|
2600 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2601 | 76db3ba4 | aurel32 | { |
2602 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); |
2603 | 76db3ba4 | aurel32 | } |
2604 | 76db3ba4 | aurel32 | |
2605 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2606 | 76db3ba4 | aurel32 | { |
2607 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); |
2608 | 76db3ba4 | aurel32 | } |
2609 | 76db3ba4 | aurel32 | |
2610 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2611 | 76db3ba4 | aurel32 | { |
2612 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2613 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2614 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2615 | 76db3ba4 | aurel32 | } |
2616 | b61f2753 | aurel32 | } |
2617 | b61f2753 | aurel32 | |
2618 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2619 | b61f2753 | aurel32 | { |
2620 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2621 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2622 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
2623 | 76db3ba4 | aurel32 | tcg_gen_ext16s_tl(arg1, arg1); |
2624 | 76db3ba4 | aurel32 | } else {
|
2625 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); |
2626 | 76db3ba4 | aurel32 | } |
2627 | b61f2753 | aurel32 | } |
2628 | b61f2753 | aurel32 | |
2629 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2630 | b61f2753 | aurel32 | { |
2631 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2632 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2633 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2634 | 76db3ba4 | aurel32 | } |
2635 | b61f2753 | aurel32 | } |
2636 | b61f2753 | aurel32 | |
2637 | f976b09e | Alexander Graf | static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2638 | f976b09e | Alexander Graf | { |
2639 | f976b09e | Alexander Graf | TCGv tmp = tcg_temp_new(); |
2640 | f976b09e | Alexander Graf | gen_qemu_ld32u(ctx, tmp, addr); |
2641 | f976b09e | Alexander Graf | tcg_gen_extu_tl_i64(val, tmp); |
2642 | f976b09e | Alexander Graf | tcg_temp_free(tmp); |
2643 | f976b09e | Alexander Graf | } |
2644 | f976b09e | Alexander Graf | |
2645 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2646 | b61f2753 | aurel32 | { |
2647 | a457e7ee | blueswir1 | if (unlikely(ctx->le_mode)) {
|
2648 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2649 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
2650 | fa3966a3 | aurel32 | tcg_gen_ext32s_tl(arg1, arg1); |
2651 | b61f2753 | aurel32 | } else
|
2652 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
2653 | b61f2753 | aurel32 | } |
2654 | b61f2753 | aurel32 | |
2655 | cac7f0ba | Tom Musta | static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2656 | cac7f0ba | Tom Musta | { |
2657 | cac7f0ba | Tom Musta | TCGv tmp = tcg_temp_new(); |
2658 | cac7f0ba | Tom Musta | gen_qemu_ld32s(ctx, tmp, addr); |
2659 | cac7f0ba | Tom Musta | tcg_gen_ext_tl_i64(val, tmp); |
2660 | cac7f0ba | Tom Musta | tcg_temp_free(tmp); |
2661 | cac7f0ba | Tom Musta | } |
2662 | cac7f0ba | Tom Musta | |
2663 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2664 | b61f2753 | aurel32 | { |
2665 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2666 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2667 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(arg1, arg1); |
2668 | 76db3ba4 | aurel32 | } |
2669 | b61f2753 | aurel32 | } |
2670 | b61f2753 | aurel32 | |
2671 | 636aa200 | Blue Swirl | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2672 | b61f2753 | aurel32 | { |
2673 | 76db3ba4 | aurel32 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
2674 | b61f2753 | aurel32 | } |
2675 | b61f2753 | aurel32 | |
2676 | 636aa200 | Blue Swirl | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2677 | b61f2753 | aurel32 | { |
2678 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2679 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
2680 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
2681 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
2682 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2683 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2684 | 76db3ba4 | aurel32 | } else {
|
2685 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
2686 | 76db3ba4 | aurel32 | } |
2687 | b61f2753 | aurel32 | } |
2688 | b61f2753 | aurel32 | |
2689 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2690 | b61f2753 | aurel32 | { |
2691 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2692 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
2693 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
2694 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
2695 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2696 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
2697 | 76db3ba4 | aurel32 | } else {
|
2698 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
2699 | 76db3ba4 | aurel32 | } |
2700 | b61f2753 | aurel32 | } |
2701 | b61f2753 | aurel32 | |
2702 | f976b09e | Alexander Graf | static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2703 | f976b09e | Alexander Graf | { |
2704 | f976b09e | Alexander Graf | TCGv tmp = tcg_temp_new(); |
2705 | f976b09e | Alexander Graf | tcg_gen_trunc_i64_tl(tmp, val); |
2706 | f976b09e | Alexander Graf | gen_qemu_st32(ctx, tmp, addr); |
2707 | f976b09e | Alexander Graf | tcg_temp_free(tmp); |
2708 | f976b09e | Alexander Graf | } |
2709 | f976b09e | Alexander Graf | |
2710 | 636aa200 | Blue Swirl | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
2711 | b61f2753 | aurel32 | { |
2712 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2713 | a7812ae4 | pbrook | TCGv_i64 t0 = tcg_temp_new_i64(); |
2714 | 66896cb8 | aurel32 | tcg_gen_bswap64_i64(t0, arg1); |
2715 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
2716 | a7812ae4 | pbrook | tcg_temp_free_i64(t0); |
2717 | b61f2753 | aurel32 | } else
|
2718 | 76db3ba4 | aurel32 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
2719 | b61f2753 | aurel32 | } |
2720 | b61f2753 | aurel32 | |
2721 | 0c8aacd4 | aurel32 | #define GEN_LD(name, ldop, opc, type) \
|
2722 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2723 | 79aceca5 | bellard | { \ |
2724 | 76db3ba4 | aurel32 | TCGv EA; \ |
2725 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2726 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2727 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2728 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2729 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2730 | 79aceca5 | bellard | } |
2731 | 79aceca5 | bellard | |
2732 | 0c8aacd4 | aurel32 | #define GEN_LDU(name, ldop, opc, type) \
|
2733 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
2734 | 79aceca5 | bellard | { \ |
2735 | b61f2753 | aurel32 | TCGv EA; \ |
2736 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2737 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2738 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2739 | 9fddaa0c | bellard | return; \
|
2740 | 9a64fbe4 | bellard | } \ |
2741 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2742 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2743 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2744 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2745 | 9d53c753 | j_mayer | else \
|
2746 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2747 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2748 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2749 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2750 | 79aceca5 | bellard | } |
2751 | 79aceca5 | bellard | |
2752 | 0c8aacd4 | aurel32 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
2753 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2754 | 79aceca5 | bellard | { \ |
2755 | b61f2753 | aurel32 | TCGv EA; \ |
2756 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || \ |
2757 | 76a66253 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2758 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2759 | 9fddaa0c | bellard | return; \
|
2760 | 9a64fbe4 | bellard | } \ |
2761 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2762 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2763 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2764 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2765 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2766 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2767 | 79aceca5 | bellard | } |
2768 | 79aceca5 | bellard | |
2769 | cd6e9320 | Thomas Huth | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
|
2770 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2771 | 79aceca5 | bellard | { \ |
2772 | 76db3ba4 | aurel32 | TCGv EA; \ |
2773 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2774 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2775 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2776 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2777 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2778 | 79aceca5 | bellard | } |
2779 | cd6e9320 | Thomas Huth | #define GEN_LDX(name, ldop, opc2, opc3, type) \
|
2780 | cd6e9320 | Thomas Huth | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) |
2781 | 79aceca5 | bellard | |
2782 | 0c8aacd4 | aurel32 | #define GEN_LDS(name, ldop, op, type) \
|
2783 | 0c8aacd4 | aurel32 | GEN_LD(name, ldop, op | 0x20, type); \
|
2784 | 0c8aacd4 | aurel32 | GEN_LDU(name, ldop, op | 0x21, type); \
|
2785 | 0c8aacd4 | aurel32 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ |
2786 | 0c8aacd4 | aurel32 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
2787 | 79aceca5 | bellard | |
2788 | 79aceca5 | bellard | /* lbz lbzu lbzux lbzx */
|
2789 | 0c8aacd4 | aurel32 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
|
2790 | 79aceca5 | bellard | /* lha lhau lhaux lhax */
|
2791 | 0c8aacd4 | aurel32 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
|
2792 | 79aceca5 | bellard | /* lhz lhzu lhzux lhzx */
|
2793 | 0c8aacd4 | aurel32 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
|
2794 | 79aceca5 | bellard | /* lwz lwzu lwzux lwzx */
|
2795 | 0c8aacd4 | aurel32 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
|
2796 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2797 | d9bce9d9 | j_mayer | /* lwaux */
|
2798 | 0c8aacd4 | aurel32 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
2799 | d9bce9d9 | j_mayer | /* lwax */
|
2800 | 0c8aacd4 | aurel32 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
2801 | d9bce9d9 | j_mayer | /* ldux */
|
2802 | 0c8aacd4 | aurel32 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
2803 | d9bce9d9 | j_mayer | /* ldx */
|
2804 | 0c8aacd4 | aurel32 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
2805 | 99e300ef | Blue Swirl | |
2806 | 99e300ef | Blue Swirl | static void gen_ld(DisasContext *ctx) |
2807 | d9bce9d9 | j_mayer | { |
2808 | b61f2753 | aurel32 | TCGv EA; |
2809 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode)) {
|
2810 | d9bce9d9 | j_mayer | if (unlikely(rA(ctx->opcode) == 0 || |
2811 | d9bce9d9 | j_mayer | rA(ctx->opcode) == rD(ctx->opcode))) { |
2812 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2813 | d9bce9d9 | j_mayer | return;
|
2814 | d9bce9d9 | j_mayer | } |
2815 | d9bce9d9 | j_mayer | } |
2816 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2817 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2818 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2819 | d9bce9d9 | j_mayer | if (ctx->opcode & 0x02) { |
2820 | d9bce9d9 | j_mayer | /* lwa (lwau is undefined) */
|
2821 | 76db3ba4 | aurel32 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2822 | d9bce9d9 | j_mayer | } else {
|
2823 | d9bce9d9 | j_mayer | /* ld - ldu */
|
2824 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2825 | d9bce9d9 | j_mayer | } |
2826 | d9bce9d9 | j_mayer | if (Rc(ctx->opcode))
|
2827 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2828 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2829 | d9bce9d9 | j_mayer | } |
2830 | 99e300ef | Blue Swirl | |
2831 | 54623277 | Blue Swirl | /* lq */
|
2832 | 99e300ef | Blue Swirl | static void gen_lq(DisasContext *ctx) |
2833 | be147d08 | j_mayer | { |
2834 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2835 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2836 | be147d08 | j_mayer | #else
|
2837 | be147d08 | j_mayer | int ra, rd;
|
2838 | b61f2753 | aurel32 | TCGv EA; |
2839 | be147d08 | j_mayer | |
2840 | be147d08 | j_mayer | /* Restore CPU state */
|
2841 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2842 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2843 | be147d08 | j_mayer | return;
|
2844 | be147d08 | j_mayer | } |
2845 | be147d08 | j_mayer | ra = rA(ctx->opcode); |
2846 | be147d08 | j_mayer | rd = rD(ctx->opcode); |
2847 | be147d08 | j_mayer | if (unlikely((rd & 1) || rd == ra)) { |
2848 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2849 | be147d08 | j_mayer | return;
|
2850 | be147d08 | j_mayer | } |
2851 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2852 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2853 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2854 | be147d08 | j_mayer | return;
|
2855 | be147d08 | j_mayer | } |
2856 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2857 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2858 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x0F);
|
2859 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); |
2860 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2861 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
|
2862 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2863 | be147d08 | j_mayer | #endif
|
2864 | be147d08 | j_mayer | } |
2865 | d9bce9d9 | j_mayer | #endif
|
2866 | 79aceca5 | bellard | |
2867 | 79aceca5 | bellard | /*** Integer store ***/
|
2868 | 0c8aacd4 | aurel32 | #define GEN_ST(name, stop, opc, type) \
|
2869 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
2870 | 79aceca5 | bellard | { \ |
2871 | 76db3ba4 | aurel32 | TCGv EA; \ |
2872 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2873 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2874 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2875 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2876 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2877 | 79aceca5 | bellard | } |
2878 | 79aceca5 | bellard | |
2879 | 0c8aacd4 | aurel32 | #define GEN_STU(name, stop, opc, type) \
|
2880 | 99e300ef | Blue Swirl | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
2881 | 79aceca5 | bellard | { \ |
2882 | b61f2753 | aurel32 | TCGv EA; \ |
2883 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2884 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2885 | 9fddaa0c | bellard | return; \
|
2886 | 9a64fbe4 | bellard | } \ |
2887 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2888 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2889 | 9d53c753 | j_mayer | if (type == PPC_64B) \
|
2890 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03); \
|
2891 | 9d53c753 | j_mayer | else \
|
2892 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
2893 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2894 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2895 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2896 | 79aceca5 | bellard | } |
2897 | 79aceca5 | bellard | |
2898 | 0c8aacd4 | aurel32 | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
2899 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2900 | 79aceca5 | bellard | { \ |
2901 | b61f2753 | aurel32 | TCGv EA; \ |
2902 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2903 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2904 | 9fddaa0c | bellard | return; \
|
2905 | 9a64fbe4 | bellard | } \ |
2906 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2907 | 0c8aacd4 | aurel32 | EA = tcg_temp_new(); \ |
2908 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2909 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2910 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2911 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2912 | 79aceca5 | bellard | } |
2913 | 79aceca5 | bellard | |
2914 | cd6e9320 | Thomas Huth | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
|
2915 | cd6e9320 | Thomas Huth | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2916 | 79aceca5 | bellard | { \ |
2917 | 76db3ba4 | aurel32 | TCGv EA; \ |
2918 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
2919 | 76db3ba4 | aurel32 | EA = tcg_temp_new(); \ |
2920 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
2921 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2922 | b61f2753 | aurel32 | tcg_temp_free(EA); \ |
2923 | 79aceca5 | bellard | } |
2924 | cd6e9320 | Thomas Huth | #define GEN_STX(name, stop, opc2, opc3, type) \
|
2925 | cd6e9320 | Thomas Huth | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) |
2926 | 79aceca5 | bellard | |
2927 | 0c8aacd4 | aurel32 | #define GEN_STS(name, stop, op, type) \
|
2928 | 0c8aacd4 | aurel32 | GEN_ST(name, stop, op | 0x20, type); \
|
2929 | 0c8aacd4 | aurel32 | GEN_STU(name, stop, op | 0x21, type); \
|
2930 | 0c8aacd4 | aurel32 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ |
2931 | 0c8aacd4 | aurel32 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
2932 | 79aceca5 | bellard | |
2933 | 79aceca5 | bellard | /* stb stbu stbux stbx */
|
2934 | 0c8aacd4 | aurel32 | GEN_STS(stb, st8, 0x06, PPC_INTEGER);
|
2935 | 79aceca5 | bellard | /* sth sthu sthux sthx */
|
2936 | 0c8aacd4 | aurel32 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
|
2937 | 79aceca5 | bellard | /* stw stwu stwux stwx */
|
2938 | 0c8aacd4 | aurel32 | GEN_STS(stw, st32, 0x04, PPC_INTEGER);
|
2939 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
2940 | 0c8aacd4 | aurel32 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2941 | 0c8aacd4 | aurel32 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); |
2942 | 99e300ef | Blue Swirl | |
2943 | 99e300ef | Blue Swirl | static void gen_std(DisasContext *ctx) |
2944 | d9bce9d9 | j_mayer | { |
2945 | be147d08 | j_mayer | int rs;
|
2946 | b61f2753 | aurel32 | TCGv EA; |
2947 | be147d08 | j_mayer | |
2948 | be147d08 | j_mayer | rs = rS(ctx->opcode); |
2949 | be147d08 | j_mayer | if ((ctx->opcode & 0x3) == 0x2) { |
2950 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
2951 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2952 | be147d08 | j_mayer | #else
|
2953 | be147d08 | j_mayer | /* stq */
|
2954 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx == 0)) { |
2955 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2956 | be147d08 | j_mayer | return;
|
2957 | be147d08 | j_mayer | } |
2958 | be147d08 | j_mayer | if (unlikely(rs & 1)) { |
2959 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2960 | d9bce9d9 | j_mayer | return;
|
2961 | d9bce9d9 | j_mayer | } |
2962 | 76db3ba4 | aurel32 | if (unlikely(ctx->le_mode)) {
|
2963 | be147d08 | j_mayer | /* Little-endian mode is not handled */
|
2964 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
2965 | be147d08 | j_mayer | return;
|
2966 | be147d08 | j_mayer | } |
2967 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2968 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2969 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2970 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2971 | 76db3ba4 | aurel32 | gen_addr_add(ctx, EA, EA, 8);
|
2972 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
|
2973 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2974 | be147d08 | j_mayer | #endif
|
2975 | be147d08 | j_mayer | } else {
|
2976 | be147d08 | j_mayer | /* std / stdu */
|
2977 | be147d08 | j_mayer | if (Rc(ctx->opcode)) {
|
2978 | be147d08 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { |
2979 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2980 | be147d08 | j_mayer | return;
|
2981 | be147d08 | j_mayer | } |
2982 | be147d08 | j_mayer | } |
2983 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
2984 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
2985 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0x03);
|
2986 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); |
2987 | be147d08 | j_mayer | if (Rc(ctx->opcode))
|
2988 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2989 | b61f2753 | aurel32 | tcg_temp_free(EA); |
2990 | d9bce9d9 | j_mayer | } |
2991 | d9bce9d9 | j_mayer | } |
2992 | d9bce9d9 | j_mayer | #endif
|
2993 | 79aceca5 | bellard | /*** Integer load and store with byte reverse ***/
|
2994 | 79aceca5 | bellard | /* lhbrx */
|
2995 | 86178a57 | Juan Quintela | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2996 | b61f2753 | aurel32 | { |
2997 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
2998 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
2999 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(arg1, arg1); |
3000 | 76db3ba4 | aurel32 | } |
3001 | b61f2753 | aurel32 | } |
3002 | 0c8aacd4 | aurel32 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
3003 | b61f2753 | aurel32 | |
3004 | 79aceca5 | bellard | /* lwbrx */
|
3005 | 86178a57 | Juan Quintela | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
3006 | b61f2753 | aurel32 | { |
3007 | 76db3ba4 | aurel32 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
3008 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
3009 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(arg1, arg1); |
3010 | 76db3ba4 | aurel32 | } |
3011 | b61f2753 | aurel32 | } |
3012 | 0c8aacd4 | aurel32 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
3013 | b61f2753 | aurel32 | |
3014 | cd6e9320 | Thomas Huth | #if defined(TARGET_PPC64)
|
3015 | cd6e9320 | Thomas Huth | /* ldbrx */
|
3016 | cd6e9320 | Thomas Huth | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
3017 | cd6e9320 | Thomas Huth | { |
3018 | cd6e9320 | Thomas Huth | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
3019 | cd6e9320 | Thomas Huth | if (likely(!ctx->le_mode)) {
|
3020 | cd6e9320 | Thomas Huth | tcg_gen_bswap64_tl(arg1, arg1); |
3021 | cd6e9320 | Thomas Huth | } |
3022 | cd6e9320 | Thomas Huth | } |
3023 | cd6e9320 | Thomas Huth | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); |
3024 | cd6e9320 | Thomas Huth | #endif /* TARGET_PPC64 */ |
3025 | cd6e9320 | Thomas Huth | |
3026 | 79aceca5 | bellard | /* sthbrx */
|
3027 | 86178a57 | Juan Quintela | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
3028 | b61f2753 | aurel32 | { |
3029 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
3030 | 76db3ba4 | aurel32 | TCGv t0 = tcg_temp_new(); |
3031 | 76db3ba4 | aurel32 | tcg_gen_ext16u_tl(t0, arg1); |
3032 | fa3966a3 | aurel32 | tcg_gen_bswap16_tl(t0, t0); |
3033 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
3034 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
3035 | 76db3ba4 | aurel32 | } else {
|
3036 | 76db3ba4 | aurel32 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); |
3037 | 76db3ba4 | aurel32 | } |
3038 | b61f2753 | aurel32 | } |
3039 | 0c8aacd4 | aurel32 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
3040 | b61f2753 | aurel32 | |
3041 | 79aceca5 | bellard | /* stwbrx */
|
3042 | 86178a57 | Juan Quintela | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
3043 | b61f2753 | aurel32 | { |
3044 | 76db3ba4 | aurel32 | if (likely(!ctx->le_mode)) {
|
3045 | fa3966a3 | aurel32 | TCGv t0 = tcg_temp_new(); |
3046 | fa3966a3 | aurel32 | tcg_gen_ext32u_tl(t0, arg1); |
3047 | fa3966a3 | aurel32 | tcg_gen_bswap32_tl(t0, t0); |
3048 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
3049 | 76db3ba4 | aurel32 | tcg_temp_free(t0); |
3050 | 76db3ba4 | aurel32 | } else {
|
3051 | 76db3ba4 | aurel32 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); |
3052 | 76db3ba4 | aurel32 | } |
3053 | b61f2753 | aurel32 | } |
3054 | 0c8aacd4 | aurel32 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
3055 | 79aceca5 | bellard | |
3056 | cd6e9320 | Thomas Huth | #if defined(TARGET_PPC64)
|
3057 | cd6e9320 | Thomas Huth | /* stdbrx */
|
3058 | cd6e9320 | Thomas Huth | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
3059 | cd6e9320 | Thomas Huth | { |
3060 | cd6e9320 | Thomas Huth | if (likely(!ctx->le_mode)) {
|
3061 | cd6e9320 | Thomas Huth | TCGv t0 = tcg_temp_new(); |
3062 | cd6e9320 | Thomas Huth | tcg_gen_bswap64_tl(t0, arg1); |
3063 | cd6e9320 | Thomas Huth | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
3064 | cd6e9320 | Thomas Huth | tcg_temp_free(t0); |
3065 | cd6e9320 | Thomas Huth | } else {
|
3066 | cd6e9320 | Thomas Huth | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
3067 | cd6e9320 | Thomas Huth | } |
3068 | cd6e9320 | Thomas Huth | } |
3069 | cd6e9320 | Thomas Huth | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); |
3070 | cd6e9320 | Thomas Huth | #endif /* TARGET_PPC64 */ |
3071 | cd6e9320 | Thomas Huth | |
3072 | 79aceca5 | bellard | /*** Integer load and store multiple ***/
|
3073 | 99e300ef | Blue Swirl | |
3074 | 54623277 | Blue Swirl | /* lmw */
|
3075 | 99e300ef | Blue Swirl | static void gen_lmw(DisasContext *ctx) |
3076 | 79aceca5 | bellard | { |
3077 | 76db3ba4 | aurel32 | TCGv t0; |
3078 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
3079 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3080 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
3081 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
3082 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3083 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
3084 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
3085 | 2f5a189c | Blue Swirl | gen_helper_lmw(cpu_env, t0, t1); |
3086 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
3087 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
3088 | 79aceca5 | bellard | } |
3089 | 79aceca5 | bellard | |
3090 | 79aceca5 | bellard | /* stmw */
|
3091 | 99e300ef | Blue Swirl | static void gen_stmw(DisasContext *ctx) |
3092 | 79aceca5 | bellard | { |
3093 | 76db3ba4 | aurel32 | TCGv t0; |
3094 | 76db3ba4 | aurel32 | TCGv_i32 t1; |
3095 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3096 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
3097 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
3098 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3099 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rS(ctx->opcode)); |
3100 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
3101 | 2f5a189c | Blue Swirl | gen_helper_stmw(cpu_env, t0, t1); |
3102 | ff4a62cd | aurel32 | tcg_temp_free(t0); |
3103 | ff4a62cd | aurel32 | tcg_temp_free_i32(t1); |
3104 | 79aceca5 | bellard | } |
3105 | 79aceca5 | bellard | |
3106 | 79aceca5 | bellard | /*** Integer load and store strings ***/
|
3107 | 54623277 | Blue Swirl | |
3108 | 79aceca5 | bellard | /* lswi */
|
3109 | 3fc6c082 | bellard | /* PowerPC32 specification says we must generate an exception if
|
3110 | 9a64fbe4 | bellard | * rA is in the range of registers to be loaded.
|
3111 | 9a64fbe4 | bellard | * In an other hand, IBM says this is valid, but rA won't be loaded.
|
3112 | 9a64fbe4 | bellard | * For now, I'll follow the spec...
|
3113 | 9a64fbe4 | bellard | */
|
3114 | 99e300ef | Blue Swirl | static void gen_lswi(DisasContext *ctx) |
3115 | 79aceca5 | bellard | { |
3116 | dfbc799d | aurel32 | TCGv t0; |
3117 | dfbc799d | aurel32 | TCGv_i32 t1, t2; |
3118 | 79aceca5 | bellard | int nb = NB(ctx->opcode);
|
3119 | 79aceca5 | bellard | int start = rD(ctx->opcode);
|
3120 | 9a64fbe4 | bellard | int ra = rA(ctx->opcode);
|
3121 | 79aceca5 | bellard | int nr;
|
3122 | 79aceca5 | bellard | |
3123 | 79aceca5 | bellard | if (nb == 0) |
3124 | 79aceca5 | bellard | nb = 32;
|
3125 | 79aceca5 | bellard | nr = nb / 4;
|
3126 | 76a66253 | j_mayer | if (unlikely(((start + nr) > 32 && |
3127 | 76a66253 | j_mayer | start <= ra && (start + nr - 32) > ra) ||
|
3128 | 76a66253 | j_mayer | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
|
3129 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
3130 | 9fddaa0c | bellard | return;
|
3131 | 297d8e62 | bellard | } |
3132 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3133 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
3134 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
3135 | dfbc799d | aurel32 | t0 = tcg_temp_new(); |
3136 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
3137 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
3138 | dfbc799d | aurel32 | t2 = tcg_const_i32(start); |
3139 | 2f5a189c | Blue Swirl | gen_helper_lsw(cpu_env, t0, t1, t2); |
3140 | dfbc799d | aurel32 | tcg_temp_free(t0); |
3141 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
3142 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
3143 | 79aceca5 | bellard | } |
3144 | 79aceca5 | bellard | |
3145 | 79aceca5 | bellard | /* lswx */
|
3146 | 99e300ef | Blue Swirl | static void gen_lswx(DisasContext *ctx) |
3147 | 79aceca5 | bellard | { |
3148 | 76db3ba4 | aurel32 | TCGv t0; |
3149 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2, t3; |
3150 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3151 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
3152 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
3153 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3154 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3155 | 76db3ba4 | aurel32 | t1 = tcg_const_i32(rD(ctx->opcode)); |
3156 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rA(ctx->opcode)); |
3157 | 76db3ba4 | aurel32 | t3 = tcg_const_i32(rB(ctx->opcode)); |
3158 | 2f5a189c | Blue Swirl | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
3159 | dfbc799d | aurel32 | tcg_temp_free(t0); |
3160 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
3161 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
3162 | dfbc799d | aurel32 | tcg_temp_free_i32(t3); |
3163 | 79aceca5 | bellard | } |
3164 | 79aceca5 | bellard | |
3165 | 79aceca5 | bellard | /* stswi */
|
3166 | 99e300ef | Blue Swirl | static void gen_stswi(DisasContext *ctx) |
3167 | 79aceca5 | bellard | { |
3168 | 76db3ba4 | aurel32 | TCGv t0; |
3169 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
3170 | 4b3686fa | bellard | int nb = NB(ctx->opcode);
|
3171 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3172 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
3173 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
3174 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3175 | 76db3ba4 | aurel32 | gen_addr_register(ctx, t0); |
3176 | 4b3686fa | bellard | if (nb == 0) |
3177 | 4b3686fa | bellard | nb = 32;
|
3178 | dfbc799d | aurel32 | t1 = tcg_const_i32(nb); |
3179 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
3180 | 2f5a189c | Blue Swirl | gen_helper_stsw(cpu_env, t0, t1, t2); |
3181 | dfbc799d | aurel32 | tcg_temp_free(t0); |
3182 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
3183 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
3184 | 79aceca5 | bellard | } |
3185 | 79aceca5 | bellard | |
3186 | 79aceca5 | bellard | /* stswx */
|
3187 | 99e300ef | Blue Swirl | static void gen_stswx(DisasContext *ctx) |
3188 | 79aceca5 | bellard | { |
3189 | 76db3ba4 | aurel32 | TCGv t0; |
3190 | 76db3ba4 | aurel32 | TCGv_i32 t1, t2; |
3191 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); |
3192 | 8dd4983c | bellard | /* NIP cannot be restored if the memory exception comes from an helper */
|
3193 | 5fafdf24 | ths | gen_update_nip(ctx, ctx->nip - 4);
|
3194 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
3195 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
3196 | 76db3ba4 | aurel32 | t1 = tcg_temp_new_i32(); |
3197 | dfbc799d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3198 | dfbc799d | aurel32 | tcg_gen_andi_i32(t1, t1, 0x7F);
|
3199 | 76db3ba4 | aurel32 | t2 = tcg_const_i32(rS(ctx->opcode)); |
3200 | 2f5a189c | Blue Swirl | gen_helper_stsw(cpu_env, t0, t1, t2); |
3201 | dfbc799d | aurel32 | tcg_temp_free(t0); |
3202 | dfbc799d | aurel32 | tcg_temp_free_i32(t1); |
3203 | dfbc799d | aurel32 | tcg_temp_free_i32(t2); |
3204 | 79aceca5 | bellard | } |
3205 | 79aceca5 | bellard | |
3206 | 79aceca5 | bellard | /*** Memory synchronisation ***/
|
3207 | 79aceca5 | bellard | /* eieio */
|
3208 | 99e300ef | Blue Swirl | static void gen_eieio(DisasContext *ctx) |
3209 | 79aceca5 | bellard | { |
3210 | 79aceca5 | bellard | } |
3211 | 79aceca5 | bellard | |
3212 | 79aceca5 | bellard | /* isync */
|
3213 | 99e300ef | Blue Swirl | static void gen_isync(DisasContext *ctx) |
3214 | 79aceca5 | bellard | { |
3215 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
3216 | 79aceca5 | bellard | } |
3217 | 79aceca5 | bellard | |
3218 | 5c77a786 | Tom Musta | #define LARX(name, len, loadop) \
|
3219 | 5c77a786 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
3220 | 5c77a786 | Tom Musta | { \ |
3221 | 5c77a786 | Tom Musta | TCGv t0; \ |
3222 | 5c77a786 | Tom Musta | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ |
3223 | 5c77a786 | Tom Musta | gen_set_access_type(ctx, ACCESS_RES); \ |
3224 | 5c77a786 | Tom Musta | t0 = tcg_temp_local_new(); \ |
3225 | 5c77a786 | Tom Musta | gen_addr_reg_index(ctx, t0); \ |
3226 | 5c77a786 | Tom Musta | if ((len) > 1) { \ |
3227 | 5c77a786 | Tom Musta | gen_check_align(ctx, t0, (len)-1); \
|
3228 | 5c77a786 | Tom Musta | } \ |
3229 | 5c77a786 | Tom Musta | gen_qemu_##loadop(ctx, gpr, t0); \ |
3230 | 5c77a786 | Tom Musta | tcg_gen_mov_tl(cpu_reserve, t0); \ |
3231 | 5c77a786 | Tom Musta | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ |
3232 | 5c77a786 | Tom Musta | tcg_temp_free(t0); \ |
3233 | 79aceca5 | bellard | } |
3234 | 79aceca5 | bellard | |
3235 | 5c77a786 | Tom Musta | /* lwarx */
|
3236 | 5c77a786 | Tom Musta | LARX(lbarx, 1, ld8u);
|
3237 | 5c77a786 | Tom Musta | LARX(lharx, 2, ld16u);
|
3238 | 5c77a786 | Tom Musta | LARX(lwarx, 4, ld32u);
|
3239 | 5c77a786 | Tom Musta | |
3240 | 5c77a786 | Tom Musta | |
3241 | 4425265b | Nathan Froyd | #if defined(CONFIG_USER_ONLY)
|
3242 | 587c51f7 | Tom Musta | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3243 | 587c51f7 | Tom Musta | int reg, int size) |
3244 | 4425265b | Nathan Froyd | { |
3245 | 4425265b | Nathan Froyd | TCGv t0 = tcg_temp_new(); |
3246 | 4425265b | Nathan Froyd | uint32_t save_exception = ctx->exception; |
3247 | 4425265b | Nathan Froyd | |
3248 | 1328c2bf | Andreas Färber | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
3249 | 4425265b | Nathan Froyd | tcg_gen_movi_tl(t0, (size << 5) | reg);
|
3250 | 1328c2bf | Andreas Färber | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
3251 | 4425265b | Nathan Froyd | tcg_temp_free(t0); |
3252 | 4425265b | Nathan Froyd | gen_update_nip(ctx, ctx->nip-4);
|
3253 | 4425265b | Nathan Froyd | ctx->exception = POWERPC_EXCP_BRANCH; |
3254 | 4425265b | Nathan Froyd | gen_exception(ctx, POWERPC_EXCP_STCX); |
3255 | 4425265b | Nathan Froyd | ctx->exception = save_exception; |
3256 | 4425265b | Nathan Froyd | } |
3257 | 4425265b | Nathan Froyd | #else
|
3258 | 587c51f7 | Tom Musta | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3259 | 587c51f7 | Tom Musta | int reg, int size) |
3260 | 587c51f7 | Tom Musta | { |
3261 | 587c51f7 | Tom Musta | int l1;
|
3262 | 4425265b | Nathan Froyd | |
3263 | 587c51f7 | Tom Musta | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
|
3264 | 587c51f7 | Tom Musta | l1 = gen_new_label(); |
3265 | 587c51f7 | Tom Musta | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); |
3266 | 587c51f7 | Tom Musta | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); |
3267 | 587c51f7 | Tom Musta | #if defined(TARGET_PPC64)
|
3268 | 587c51f7 | Tom Musta | if (size == 8) { |
3269 | 587c51f7 | Tom Musta | gen_qemu_st64(ctx, cpu_gpr[reg], EA); |
3270 | 587c51f7 | Tom Musta | } else
|
3271 | 587c51f7 | Tom Musta | #endif
|
3272 | 587c51f7 | Tom Musta | if (size == 4) { |
3273 | 587c51f7 | Tom Musta | gen_qemu_st32(ctx, cpu_gpr[reg], EA); |
3274 | 587c51f7 | Tom Musta | } else if (size == 2) { |
3275 | 587c51f7 | Tom Musta | gen_qemu_st16(ctx, cpu_gpr[reg], EA); |
3276 | 587c51f7 | Tom Musta | } else {
|
3277 | 587c51f7 | Tom Musta | gen_qemu_st8(ctx, cpu_gpr[reg], EA); |
3278 | 4425265b | Nathan Froyd | } |
3279 | 587c51f7 | Tom Musta | gen_set_label(l1); |
3280 | 587c51f7 | Tom Musta | tcg_gen_movi_tl(cpu_reserve, -1);
|
3281 | 587c51f7 | Tom Musta | } |
3282 | 4425265b | Nathan Froyd | #endif
|
3283 | 587c51f7 | Tom Musta | |
3284 | 587c51f7 | Tom Musta | #define STCX(name, len) \
|
3285 | 587c51f7 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
3286 | 587c51f7 | Tom Musta | { \ |
3287 | 587c51f7 | Tom Musta | TCGv t0; \ |
3288 | 587c51f7 | Tom Musta | gen_set_access_type(ctx, ACCESS_RES); \ |
3289 | 587c51f7 | Tom Musta | t0 = tcg_temp_local_new(); \ |
3290 | 587c51f7 | Tom Musta | gen_addr_reg_index(ctx, t0); \ |
3291 | 587c51f7 | Tom Musta | if (len > 1) { \ |
3292 | 587c51f7 | Tom Musta | gen_check_align(ctx, t0, (len)-1); \
|
3293 | 587c51f7 | Tom Musta | } \ |
3294 | 587c51f7 | Tom Musta | gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \ |
3295 | 587c51f7 | Tom Musta | tcg_temp_free(t0); \ |
3296 | 79aceca5 | bellard | } |
3297 | 79aceca5 | bellard | |
3298 | 587c51f7 | Tom Musta | STCX(stbcx_, 1);
|
3299 | 587c51f7 | Tom Musta | STCX(sthcx_, 2);
|
3300 | 587c51f7 | Tom Musta | STCX(stwcx_, 4);
|
3301 | 587c51f7 | Tom Musta | |
3302 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3303 | 426613db | j_mayer | /* ldarx */
|
3304 | 5c77a786 | Tom Musta | LARX(ldarx, 8, ld64);
|
3305 | 426613db | j_mayer | |
3306 | 426613db | j_mayer | /* stdcx. */
|
3307 | 587c51f7 | Tom Musta | STCX(stdcx_, 8);
|
3308 | 426613db | j_mayer | #endif /* defined(TARGET_PPC64) */ |
3309 | 426613db | j_mayer | |
3310 | 79aceca5 | bellard | /* sync */
|
3311 | 99e300ef | Blue Swirl | static void gen_sync(DisasContext *ctx) |
3312 | 79aceca5 | bellard | { |
3313 | 79aceca5 | bellard | } |
3314 | 79aceca5 | bellard | |
3315 | 0db1b20e | j_mayer | /* wait */
|
3316 | 99e300ef | Blue Swirl | static void gen_wait(DisasContext *ctx) |
3317 | 0db1b20e | j_mayer | { |
3318 | 931ff272 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3319 | 259186a7 | Andreas Färber | tcg_gen_st_i32(t0, cpu_env, |
3320 | 259186a7 | Andreas Färber | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); |
3321 | 931ff272 | aurel32 | tcg_temp_free_i32(t0); |
3322 | 0db1b20e | j_mayer | /* Stop translation, as the CPU is supposed to sleep from now */
|
3323 | e06fcd75 | aurel32 | gen_exception_err(ctx, EXCP_HLT, 1);
|
3324 | 0db1b20e | j_mayer | } |
3325 | 0db1b20e | j_mayer | |
3326 | 79aceca5 | bellard | /*** Floating-point load ***/
|
3327 | a0d7d5a7 | aurel32 | #define GEN_LDF(name, ldop, opc, type) \
|
3328 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3329 | 79aceca5 | bellard | { \ |
3330 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3331 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3332 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3333 | 4ecc3190 | bellard | return; \
|
3334 | 4ecc3190 | bellard | } \ |
3335 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3336 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3337 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3338 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3339 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3340 | 79aceca5 | bellard | } |
3341 | 79aceca5 | bellard | |
3342 | a0d7d5a7 | aurel32 | #define GEN_LDUF(name, ldop, opc, type) \
|
3343 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3344 | 79aceca5 | bellard | { \ |
3345 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3346 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3347 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3348 | 4ecc3190 | bellard | return; \
|
3349 | 4ecc3190 | bellard | } \ |
3350 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3351 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3352 | 9fddaa0c | bellard | return; \
|
3353 | 9a64fbe4 | bellard | } \ |
3354 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3355 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3356 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3357 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3358 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3359 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3360 | 79aceca5 | bellard | } |
3361 | 79aceca5 | bellard | |
3362 | a0d7d5a7 | aurel32 | #define GEN_LDUXF(name, ldop, opc, type) \
|
3363 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3364 | 79aceca5 | bellard | { \ |
3365 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3366 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3367 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3368 | 4ecc3190 | bellard | return; \
|
3369 | 4ecc3190 | bellard | } \ |
3370 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3371 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3372 | 9fddaa0c | bellard | return; \
|
3373 | 9a64fbe4 | bellard | } \ |
3374 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3375 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3376 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3377 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3378 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3379 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3380 | 79aceca5 | bellard | } |
3381 | 79aceca5 | bellard | |
3382 | a0d7d5a7 | aurel32 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
3383 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3384 | 79aceca5 | bellard | { \ |
3385 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3386 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3387 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3388 | 4ecc3190 | bellard | return; \
|
3389 | 4ecc3190 | bellard | } \ |
3390 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3391 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3392 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3393 | 76db3ba4 | aurel32 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ |
3394 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3395 | 79aceca5 | bellard | } |
3396 | 79aceca5 | bellard | |
3397 | a0d7d5a7 | aurel32 | #define GEN_LDFS(name, ldop, op, type) \
|
3398 | a0d7d5a7 | aurel32 | GEN_LDF(name, ldop, op | 0x20, type); \
|
3399 | a0d7d5a7 | aurel32 | GEN_LDUF(name, ldop, op | 0x21, type); \
|
3400 | a0d7d5a7 | aurel32 | GEN_LDUXF(name, ldop, op | 0x01, type); \
|
3401 | a0d7d5a7 | aurel32 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
3402 | a0d7d5a7 | aurel32 | |
3403 | 636aa200 | Blue Swirl | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3404 | a0d7d5a7 | aurel32 | { |
3405 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3406 | a0d7d5a7 | aurel32 | TCGv_i32 t1 = tcg_temp_new_i32(); |
3407 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, arg2); |
3408 | a0d7d5a7 | aurel32 | tcg_gen_trunc_tl_i32(t1, t0); |
3409 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3410 | 8e703949 | Blue Swirl | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
3411 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t1); |
3412 | a0d7d5a7 | aurel32 | } |
3413 | 79aceca5 | bellard | |
3414 | a0d7d5a7 | aurel32 | /* lfd lfdu lfdux lfdx */
|
3415 | a0d7d5a7 | aurel32 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
|
3416 | a0d7d5a7 | aurel32 | /* lfs lfsu lfsux lfsx */
|
3417 | a0d7d5a7 | aurel32 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
3418 | 79aceca5 | bellard | |
3419 | 05050ee8 | Aurelien Jarno | /* lfdp */
|
3420 | 05050ee8 | Aurelien Jarno | static void gen_lfdp(DisasContext *ctx) |
3421 | 05050ee8 | Aurelien Jarno | { |
3422 | 05050ee8 | Aurelien Jarno | TCGv EA; |
3423 | 05050ee8 | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
3424 | 05050ee8 | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
3425 | 05050ee8 | Aurelien Jarno | return;
|
3426 | 05050ee8 | Aurelien Jarno | } |
3427 | 05050ee8 | Aurelien Jarno | gen_set_access_type(ctx, ACCESS_FLOAT); |
3428 | 05050ee8 | Aurelien Jarno | EA = tcg_temp_new(); |
3429 | 05050ee8 | Aurelien Jarno | gen_addr_imm_index(ctx, EA, 0); \
|
3430 | 05050ee8 | Aurelien Jarno | if (unlikely(ctx->le_mode)) {
|
3431 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3432 | 05050ee8 | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3433 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3434 | 05050ee8 | Aurelien Jarno | } else {
|
3435 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3436 | 05050ee8 | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3437 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3438 | 05050ee8 | Aurelien Jarno | } |
3439 | 05050ee8 | Aurelien Jarno | tcg_temp_free(EA); |
3440 | 05050ee8 | Aurelien Jarno | } |
3441 | 05050ee8 | Aurelien Jarno | |
3442 | 05050ee8 | Aurelien Jarno | /* lfdpx */
|
3443 | 05050ee8 | Aurelien Jarno | static void gen_lfdpx(DisasContext *ctx) |
3444 | 05050ee8 | Aurelien Jarno | { |
3445 | 05050ee8 | Aurelien Jarno | TCGv EA; |
3446 | 05050ee8 | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
3447 | 05050ee8 | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
3448 | 05050ee8 | Aurelien Jarno | return;
|
3449 | 05050ee8 | Aurelien Jarno | } |
3450 | 05050ee8 | Aurelien Jarno | gen_set_access_type(ctx, ACCESS_FLOAT); |
3451 | 05050ee8 | Aurelien Jarno | EA = tcg_temp_new(); |
3452 | 05050ee8 | Aurelien Jarno | gen_addr_reg_index(ctx, EA); |
3453 | 05050ee8 | Aurelien Jarno | if (unlikely(ctx->le_mode)) {
|
3454 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3455 | 05050ee8 | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3456 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3457 | 05050ee8 | Aurelien Jarno | } else {
|
3458 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3459 | 05050ee8 | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3460 | 05050ee8 | Aurelien Jarno | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3461 | 05050ee8 | Aurelien Jarno | } |
3462 | 05050ee8 | Aurelien Jarno | tcg_temp_free(EA); |
3463 | 05050ee8 | Aurelien Jarno | } |
3464 | 05050ee8 | Aurelien Jarno | |
3465 | 199f830d | Aurelien Jarno | /* lfiwax */
|
3466 | 199f830d | Aurelien Jarno | static void gen_lfiwax(DisasContext *ctx) |
3467 | 199f830d | Aurelien Jarno | { |
3468 | 199f830d | Aurelien Jarno | TCGv EA; |
3469 | 199f830d | Aurelien Jarno | TCGv t0; |
3470 | 199f830d | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
3471 | 199f830d | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
3472 | 199f830d | Aurelien Jarno | return;
|
3473 | 199f830d | Aurelien Jarno | } |
3474 | 199f830d | Aurelien Jarno | gen_set_access_type(ctx, ACCESS_FLOAT); |
3475 | 199f830d | Aurelien Jarno | EA = tcg_temp_new(); |
3476 | 199f830d | Aurelien Jarno | t0 = tcg_temp_new(); |
3477 | 199f830d | Aurelien Jarno | gen_addr_reg_index(ctx, EA); |
3478 | 909eedb7 | Aurelien Jarno | gen_qemu_ld32s(ctx, t0, EA); |
3479 | 199f830d | Aurelien Jarno | tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); |
3480 | 199f830d | Aurelien Jarno | tcg_temp_free(EA); |
3481 | 199f830d | Aurelien Jarno | tcg_temp_free(t0); |
3482 | 199f830d | Aurelien Jarno | } |
3483 | 199f830d | Aurelien Jarno | |
3484 | 79aceca5 | bellard | /*** Floating-point store ***/
|
3485 | a0d7d5a7 | aurel32 | #define GEN_STF(name, stop, opc, type) \
|
3486 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3487 | 79aceca5 | bellard | { \ |
3488 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3489 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3490 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3491 | 4ecc3190 | bellard | return; \
|
3492 | 4ecc3190 | bellard | } \ |
3493 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3494 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3495 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3496 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3497 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3498 | 79aceca5 | bellard | } |
3499 | 79aceca5 | bellard | |
3500 | a0d7d5a7 | aurel32 | #define GEN_STUF(name, stop, opc, type) \
|
3501 | 99e300ef | Blue Swirl | static void glue(gen_, name##u)(DisasContext *ctx) \ |
3502 | 79aceca5 | bellard | { \ |
3503 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3504 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3505 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3506 | 4ecc3190 | bellard | return; \
|
3507 | 4ecc3190 | bellard | } \ |
3508 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3509 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3510 | 9fddaa0c | bellard | return; \
|
3511 | 9a64fbe4 | bellard | } \ |
3512 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3513 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3514 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, EA, 0); \
|
3515 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3516 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3517 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3518 | 79aceca5 | bellard | } |
3519 | 79aceca5 | bellard | |
3520 | a0d7d5a7 | aurel32 | #define GEN_STUXF(name, stop, opc, type) \
|
3521 | 99e300ef | Blue Swirl | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
3522 | 79aceca5 | bellard | { \ |
3523 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3524 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3525 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3526 | 4ecc3190 | bellard | return; \
|
3527 | 4ecc3190 | bellard | } \ |
3528 | 76a66253 | j_mayer | if (unlikely(rA(ctx->opcode) == 0)) { \ |
3529 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
3530 | 9fddaa0c | bellard | return; \
|
3531 | 9a64fbe4 | bellard | } \ |
3532 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3533 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3534 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3535 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3536 | a0d7d5a7 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3537 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3538 | 79aceca5 | bellard | } |
3539 | 79aceca5 | bellard | |
3540 | a0d7d5a7 | aurel32 | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
3541 | 99e300ef | Blue Swirl | static void glue(gen_, name##x)(DisasContext *ctx) \ |
3542 | 79aceca5 | bellard | { \ |
3543 | a0d7d5a7 | aurel32 | TCGv EA; \ |
3544 | 76a66253 | j_mayer | if (unlikely(!ctx->fpu_enabled)) { \
|
3545 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3546 | 4ecc3190 | bellard | return; \
|
3547 | 4ecc3190 | bellard | } \ |
3548 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
3549 | a0d7d5a7 | aurel32 | EA = tcg_temp_new(); \ |
3550 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
3551 | 76db3ba4 | aurel32 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ |
3552 | a0d7d5a7 | aurel32 | tcg_temp_free(EA); \ |
3553 | 79aceca5 | bellard | } |
3554 | 79aceca5 | bellard | |
3555 | a0d7d5a7 | aurel32 | #define GEN_STFS(name, stop, op, type) \
|
3556 | a0d7d5a7 | aurel32 | GEN_STF(name, stop, op | 0x20, type); \
|
3557 | a0d7d5a7 | aurel32 | GEN_STUF(name, stop, op | 0x21, type); \
|
3558 | a0d7d5a7 | aurel32 | GEN_STUXF(name, stop, op | 0x01, type); \
|
3559 | a0d7d5a7 | aurel32 | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
3560 | a0d7d5a7 | aurel32 | |
3561 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3562 | a0d7d5a7 | aurel32 | { |
3563 | a0d7d5a7 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3564 | a0d7d5a7 | aurel32 | TCGv t1 = tcg_temp_new(); |
3565 | 8e703949 | Blue Swirl | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
3566 | a0d7d5a7 | aurel32 | tcg_gen_extu_i32_tl(t1, t0); |
3567 | a0d7d5a7 | aurel32 | tcg_temp_free_i32(t0); |
3568 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t1, arg2); |
3569 | a0d7d5a7 | aurel32 | tcg_temp_free(t1); |
3570 | a0d7d5a7 | aurel32 | } |
3571 | 79aceca5 | bellard | |
3572 | 79aceca5 | bellard | /* stfd stfdu stfdux stfdx */
|
3573 | a0d7d5a7 | aurel32 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
|
3574 | 79aceca5 | bellard | /* stfs stfsu stfsux stfsx */
|
3575 | a0d7d5a7 | aurel32 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
|
3576 | 79aceca5 | bellard | |
3577 | 44bc0c4d | Aurelien Jarno | /* stfdp */
|
3578 | 44bc0c4d | Aurelien Jarno | static void gen_stfdp(DisasContext *ctx) |
3579 | 44bc0c4d | Aurelien Jarno | { |
3580 | 44bc0c4d | Aurelien Jarno | TCGv EA; |
3581 | 44bc0c4d | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
3582 | 44bc0c4d | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
3583 | 44bc0c4d | Aurelien Jarno | return;
|
3584 | 44bc0c4d | Aurelien Jarno | } |
3585 | 44bc0c4d | Aurelien Jarno | gen_set_access_type(ctx, ACCESS_FLOAT); |
3586 | 44bc0c4d | Aurelien Jarno | EA = tcg_temp_new(); |
3587 | 44bc0c4d | Aurelien Jarno | gen_addr_imm_index(ctx, EA, 0); \
|
3588 | 44bc0c4d | Aurelien Jarno | if (unlikely(ctx->le_mode)) {
|
3589 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3590 | 44bc0c4d | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3591 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3592 | 44bc0c4d | Aurelien Jarno | } else {
|
3593 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3594 | 44bc0c4d | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3595 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3596 | 44bc0c4d | Aurelien Jarno | } |
3597 | 44bc0c4d | Aurelien Jarno | tcg_temp_free(EA); |
3598 | 44bc0c4d | Aurelien Jarno | } |
3599 | 44bc0c4d | Aurelien Jarno | |
3600 | 44bc0c4d | Aurelien Jarno | /* stfdpx */
|
3601 | 44bc0c4d | Aurelien Jarno | static void gen_stfdpx(DisasContext *ctx) |
3602 | 44bc0c4d | Aurelien Jarno | { |
3603 | 44bc0c4d | Aurelien Jarno | TCGv EA; |
3604 | 44bc0c4d | Aurelien Jarno | if (unlikely(!ctx->fpu_enabled)) {
|
3605 | 44bc0c4d | Aurelien Jarno | gen_exception(ctx, POWERPC_EXCP_FPU); |
3606 | 44bc0c4d | Aurelien Jarno | return;
|
3607 | 44bc0c4d | Aurelien Jarno | } |
3608 | 44bc0c4d | Aurelien Jarno | gen_set_access_type(ctx, ACCESS_FLOAT); |
3609 | 44bc0c4d | Aurelien Jarno | EA = tcg_temp_new(); |
3610 | 44bc0c4d | Aurelien Jarno | gen_addr_reg_index(ctx, EA); |
3611 | 44bc0c4d | Aurelien Jarno | if (unlikely(ctx->le_mode)) {
|
3612 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3613 | 44bc0c4d | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3614 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3615 | 44bc0c4d | Aurelien Jarno | } else {
|
3616 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); |
3617 | 44bc0c4d | Aurelien Jarno | tcg_gen_addi_tl(EA, EA, 8);
|
3618 | 44bc0c4d | Aurelien Jarno | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
3619 | 44bc0c4d | Aurelien Jarno | } |
3620 | 44bc0c4d | Aurelien Jarno | tcg_temp_free(EA); |
3621 | 44bc0c4d | Aurelien Jarno | } |
3622 | 44bc0c4d | Aurelien Jarno | |
3623 | 79aceca5 | bellard | /* Optional: */
|
3624 | 636aa200 | Blue Swirl | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
3625 | a0d7d5a7 | aurel32 | { |
3626 | a0d7d5a7 | aurel32 | TCGv t0 = tcg_temp_new(); |
3627 | a0d7d5a7 | aurel32 | tcg_gen_trunc_i64_tl(t0, arg1), |
3628 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, arg2); |
3629 | a0d7d5a7 | aurel32 | tcg_temp_free(t0); |
3630 | a0d7d5a7 | aurel32 | } |
3631 | 79aceca5 | bellard | /* stfiwx */
|
3632 | a0d7d5a7 | aurel32 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
3633 | 79aceca5 | bellard | |
3634 | 697ab892 | David Gibson | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3635 | 697ab892 | David Gibson | { |
3636 | 697ab892 | David Gibson | #if defined(TARGET_PPC64)
|
3637 | 697ab892 | David Gibson | if (ctx->has_cfar)
|
3638 | 697ab892 | David Gibson | tcg_gen_movi_tl(cpu_cfar, nip); |
3639 | 697ab892 | David Gibson | #endif
|
3640 | 697ab892 | David Gibson | } |
3641 | 697ab892 | David Gibson | |
3642 | 79aceca5 | bellard | /*** Branch ***/
|
3643 | 636aa200 | Blue Swirl | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
3644 | c1942362 | bellard | { |
3645 | c1942362 | bellard | TranslationBlock *tb; |
3646 | c1942362 | bellard | tb = ctx->tb; |
3647 | e0c8f9ce | Richard Henderson | if (NARROW_MODE(ctx)) {
|
3648 | a2ffb812 | aurel32 | dest = (uint32_t) dest; |
3649 | e0c8f9ce | Richard Henderson | } |
3650 | 57fec1fe | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
3651 | 8cbcb4fa | aurel32 | likely(!ctx->singlestep_enabled)) { |
3652 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
3653 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3654 | 8cfd0495 | Richard Henderson | tcg_gen_exit_tb((uintptr_t)tb + n); |
3655 | c1942362 | bellard | } else {
|
3656 | a2ffb812 | aurel32 | tcg_gen_movi_tl(cpu_nip, dest & ~3);
|
3657 | 8cbcb4fa | aurel32 | if (unlikely(ctx->singlestep_enabled)) {
|
3658 | 8cbcb4fa | aurel32 | if ((ctx->singlestep_enabled &
|
3659 | bdc4e053 | aurel32 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
3660 | f0cc4aa8 | Julio Guerra | (ctx->exception == POWERPC_EXCP_BRANCH || |
3661 | f0cc4aa8 | Julio Guerra | ctx->exception == POWERPC_EXCP_TRACE)) { |
3662 | 8cbcb4fa | aurel32 | target_ulong tmp = ctx->nip; |
3663 | 8cbcb4fa | aurel32 | ctx->nip = dest; |
3664 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
3665 | 8cbcb4fa | aurel32 | ctx->nip = tmp; |
3666 | 8cbcb4fa | aurel32 | } |
3667 | 8cbcb4fa | aurel32 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
|
3668 | e06fcd75 | aurel32 | gen_debug_exception(ctx); |
3669 | 8cbcb4fa | aurel32 | } |
3670 | 8cbcb4fa | aurel32 | } |
3671 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3672 | c1942362 | bellard | } |
3673 | c53be334 | bellard | } |
3674 | c53be334 | bellard | |
3675 | 636aa200 | Blue Swirl | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
3676 | e1833e1f | j_mayer | { |
3677 | e0c8f9ce | Richard Henderson | if (NARROW_MODE(ctx)) {
|
3678 | e0c8f9ce | Richard Henderson | nip = (uint32_t)nip; |
3679 | e0c8f9ce | Richard Henderson | } |
3680 | e0c8f9ce | Richard Henderson | tcg_gen_movi_tl(cpu_lr, nip); |
3681 | e1833e1f | j_mayer | } |
3682 | e1833e1f | j_mayer | |
3683 | 79aceca5 | bellard | /* b ba bl bla */
|
3684 | 99e300ef | Blue Swirl | static void gen_b(DisasContext *ctx) |
3685 | 79aceca5 | bellard | { |
3686 | 76a66253 | j_mayer | target_ulong li, target; |
3687 | 38a64f9d | bellard | |
3688 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3689 | 38a64f9d | bellard | /* sign extend LI */
|
3690 | e0c8f9ce | Richard Henderson | li = LI(ctx->opcode); |
3691 | e0c8f9ce | Richard Henderson | li = (li ^ 0x02000000) - 0x02000000; |
3692 | e0c8f9ce | Richard Henderson | if (likely(AA(ctx->opcode) == 0)) { |
3693 | 046d6672 | bellard | target = ctx->nip + li - 4;
|
3694 | e0c8f9ce | Richard Henderson | } else {
|
3695 | 9a64fbe4 | bellard | target = li; |
3696 | e0c8f9ce | Richard Henderson | } |
3697 | e0c8f9ce | Richard Henderson | if (LK(ctx->opcode)) {
|
3698 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3699 | e0c8f9ce | Richard Henderson | } |
3700 | 697ab892 | David Gibson | gen_update_cfar(ctx, ctx->nip); |
3701 | c1942362 | bellard | gen_goto_tb(ctx, 0, target);
|
3702 | 79aceca5 | bellard | } |
3703 | 79aceca5 | bellard | |
3704 | e98a6e40 | bellard | #define BCOND_IM 0 |
3705 | e98a6e40 | bellard | #define BCOND_LR 1 |
3706 | e98a6e40 | bellard | #define BCOND_CTR 2 |
3707 | e98a6e40 | bellard | |
3708 | 636aa200 | Blue Swirl | static inline void gen_bcond(DisasContext *ctx, int type) |
3709 | d9bce9d9 | j_mayer | { |
3710 | d9bce9d9 | j_mayer | uint32_t bo = BO(ctx->opcode); |
3711 | 05f92404 | Blue Swirl | int l1;
|
3712 | a2ffb812 | aurel32 | TCGv target; |
3713 | e98a6e40 | bellard | |
3714 | 8cbcb4fa | aurel32 | ctx->exception = POWERPC_EXCP_BRANCH; |
3715 | a2ffb812 | aurel32 | if (type == BCOND_LR || type == BCOND_CTR) {
|
3716 | a7812ae4 | pbrook | target = tcg_temp_local_new(); |
3717 | a2ffb812 | aurel32 | if (type == BCOND_CTR)
|
3718 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_ctr); |
3719 | a2ffb812 | aurel32 | else
|
3720 | a2ffb812 | aurel32 | tcg_gen_mov_tl(target, cpu_lr); |
3721 | d2e9fd8f | malc | } else {
|
3722 | d2e9fd8f | malc | TCGV_UNUSED(target); |
3723 | e98a6e40 | bellard | } |
3724 | e1833e1f | j_mayer | if (LK(ctx->opcode))
|
3725 | e1833e1f | j_mayer | gen_setlr(ctx, ctx->nip); |
3726 | a2ffb812 | aurel32 | l1 = gen_new_label(); |
3727 | a2ffb812 | aurel32 | if ((bo & 0x4) == 0) { |
3728 | a2ffb812 | aurel32 | /* Decrement and test CTR */
|
3729 | a7812ae4 | pbrook | TCGv temp = tcg_temp_new(); |
3730 | a2ffb812 | aurel32 | if (unlikely(type == BCOND_CTR)) {
|
3731 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3732 | a2ffb812 | aurel32 | return;
|
3733 | a2ffb812 | aurel32 | } |
3734 | a2ffb812 | aurel32 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
|
3735 | e0c8f9ce | Richard Henderson | if (NARROW_MODE(ctx)) {
|
3736 | a2ffb812 | aurel32 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
3737 | e0c8f9ce | Richard Henderson | } else {
|
3738 | a2ffb812 | aurel32 | tcg_gen_mov_tl(temp, cpu_ctr); |
3739 | e0c8f9ce | Richard Henderson | } |
3740 | a2ffb812 | aurel32 | if (bo & 0x2) { |
3741 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
|
3742 | a2ffb812 | aurel32 | } else {
|
3743 | a2ffb812 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
|
3744 | e98a6e40 | bellard | } |
3745 | a7812ae4 | pbrook | tcg_temp_free(temp); |
3746 | a2ffb812 | aurel32 | } |
3747 | a2ffb812 | aurel32 | if ((bo & 0x10) == 0) { |
3748 | a2ffb812 | aurel32 | /* Test CR */
|
3749 | a2ffb812 | aurel32 | uint32_t bi = BI(ctx->opcode); |
3750 | a2ffb812 | aurel32 | uint32_t mask = 1 << (3 - (bi & 0x03)); |
3751 | a7812ae4 | pbrook | TCGv_i32 temp = tcg_temp_new_i32(); |
3752 | a2ffb812 | aurel32 | |
3753 | d9bce9d9 | j_mayer | if (bo & 0x8) { |
3754 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3755 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
|
3756 | d9bce9d9 | j_mayer | } else {
|
3757 | a2ffb812 | aurel32 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
|
3758 | a2ffb812 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
|
3759 | d9bce9d9 | j_mayer | } |
3760 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
3761 | d9bce9d9 | j_mayer | } |
3762 | 697ab892 | David Gibson | gen_update_cfar(ctx, ctx->nip); |
3763 | e98a6e40 | bellard | if (type == BCOND_IM) {
|
3764 | a2ffb812 | aurel32 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3765 | a2ffb812 | aurel32 | if (likely(AA(ctx->opcode) == 0)) { |
3766 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); |
3767 | a2ffb812 | aurel32 | } else {
|
3768 | a2ffb812 | aurel32 | gen_goto_tb(ctx, 0, li);
|
3769 | a2ffb812 | aurel32 | } |
3770 | c53be334 | bellard | gen_set_label(l1); |
3771 | c1942362 | bellard | gen_goto_tb(ctx, 1, ctx->nip);
|
3772 | e98a6e40 | bellard | } else {
|
3773 | e0c8f9ce | Richard Henderson | if (NARROW_MODE(ctx)) {
|
3774 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
|
3775 | e0c8f9ce | Richard Henderson | } else {
|
3776 | a2ffb812 | aurel32 | tcg_gen_andi_tl(cpu_nip, target, ~3);
|
3777 | e0c8f9ce | Richard Henderson | } |
3778 | a2ffb812 | aurel32 | tcg_gen_exit_tb(0);
|
3779 | a2ffb812 | aurel32 | gen_set_label(l1); |
3780 | e0c8f9ce | Richard Henderson | gen_update_nip(ctx, ctx->nip); |
3781 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3782 | 08e46e54 | j_mayer | } |
3783 | e98a6e40 | bellard | } |
3784 | e98a6e40 | bellard | |
3785 | 99e300ef | Blue Swirl | static void gen_bc(DisasContext *ctx) |
3786 | 3b46e624 | ths | { |
3787 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_IM); |
3788 | e98a6e40 | bellard | } |
3789 | e98a6e40 | bellard | |
3790 | 99e300ef | Blue Swirl | static void gen_bcctr(DisasContext *ctx) |
3791 | 3b46e624 | ths | { |
3792 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_CTR); |
3793 | e98a6e40 | bellard | } |
3794 | e98a6e40 | bellard | |
3795 | 99e300ef | Blue Swirl | static void gen_bclr(DisasContext *ctx) |
3796 | 3b46e624 | ths | { |
3797 | e98a6e40 | bellard | gen_bcond(ctx, BCOND_LR); |
3798 | e98a6e40 | bellard | } |
3799 | 79aceca5 | bellard | |
3800 | 79aceca5 | bellard | /*** Condition register logical ***/
|
3801 | e1571908 | aurel32 | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
3802 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
3803 | 79aceca5 | bellard | { \ |
3804 | fc0d441e | j_mayer | uint8_t bitmask; \ |
3805 | fc0d441e | j_mayer | int sh; \
|
3806 | a7812ae4 | pbrook | TCGv_i32 t0, t1; \ |
3807 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3808 | a7812ae4 | pbrook | t0 = tcg_temp_new_i32(); \ |
3809 | fc0d441e | j_mayer | if (sh > 0) \ |
3810 | fea0c503 | aurel32 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
|
3811 | fc0d441e | j_mayer | else if (sh < 0) \ |
3812 | fea0c503 | aurel32 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
|
3813 | e1571908 | aurel32 | else \
|
3814 | fea0c503 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
|
3815 | a7812ae4 | pbrook | t1 = tcg_temp_new_i32(); \ |
3816 | fc0d441e | j_mayer | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3817 | fc0d441e | j_mayer | if (sh > 0) \ |
3818 | fea0c503 | aurel32 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
|
3819 | fc0d441e | j_mayer | else if (sh < 0) \ |
3820 | fea0c503 | aurel32 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
|
3821 | e1571908 | aurel32 | else \
|
3822 | fea0c503 | aurel32 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
|
3823 | fea0c503 | aurel32 | tcg_op(t0, t0, t1); \ |
3824 | fc0d441e | j_mayer | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
3825 | fea0c503 | aurel32 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3826 | fea0c503 | aurel32 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
|
3827 | fea0c503 | aurel32 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
|
3828 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
3829 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
3830 | 79aceca5 | bellard | } |
3831 | 79aceca5 | bellard | |
3832 | 79aceca5 | bellard | /* crand */
|
3833 | e1571908 | aurel32 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
|
3834 | 79aceca5 | bellard | /* crandc */
|
3835 | e1571908 | aurel32 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
|
3836 | 79aceca5 | bellard | /* creqv */
|
3837 | e1571908 | aurel32 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
|
3838 | 79aceca5 | bellard | /* crnand */
|
3839 | e1571908 | aurel32 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
|
3840 | 79aceca5 | bellard | /* crnor */
|
3841 | e1571908 | aurel32 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
|
3842 | 79aceca5 | bellard | /* cror */
|
3843 | e1571908 | aurel32 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
|
3844 | 79aceca5 | bellard | /* crorc */
|
3845 | e1571908 | aurel32 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
|
3846 | 79aceca5 | bellard | /* crxor */
|
3847 | e1571908 | aurel32 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
|
3848 | 99e300ef | Blue Swirl | |
3849 | 54623277 | Blue Swirl | /* mcrf */
|
3850 | 99e300ef | Blue Swirl | static void gen_mcrf(DisasContext *ctx) |
3851 | 79aceca5 | bellard | { |
3852 | 47e4661c | aurel32 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
3853 | 79aceca5 | bellard | } |
3854 | 79aceca5 | bellard | |
3855 | 79aceca5 | bellard | /*** System linkage ***/
|
3856 | 99e300ef | Blue Swirl | |
3857 | 54623277 | Blue Swirl | /* rfi (mem_idx only) */
|
3858 | 99e300ef | Blue Swirl | static void gen_rfi(DisasContext *ctx) |
3859 | 79aceca5 | bellard | { |
3860 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
3861 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3862 | 9a64fbe4 | bellard | #else
|
3863 | 9a64fbe4 | bellard | /* Restore CPU state */
|
3864 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3865 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3866 | 9fddaa0c | bellard | return;
|
3867 | 9a64fbe4 | bellard | } |
3868 | 697ab892 | David Gibson | gen_update_cfar(ctx, ctx->nip); |
3869 | e5f17ac6 | Blue Swirl | gen_helper_rfi(cpu_env); |
3870 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3871 | 9a64fbe4 | bellard | #endif
|
3872 | 79aceca5 | bellard | } |
3873 | 79aceca5 | bellard | |
3874 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
3875 | 99e300ef | Blue Swirl | static void gen_rfid(DisasContext *ctx) |
3876 | 426613db | j_mayer | { |
3877 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3878 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3879 | 426613db | j_mayer | #else
|
3880 | 426613db | j_mayer | /* Restore CPU state */
|
3881 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
3882 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3883 | 426613db | j_mayer | return;
|
3884 | 426613db | j_mayer | } |
3885 | 697ab892 | David Gibson | gen_update_cfar(ctx, ctx->nip); |
3886 | e5f17ac6 | Blue Swirl | gen_helper_rfid(cpu_env); |
3887 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3888 | 426613db | j_mayer | #endif
|
3889 | 426613db | j_mayer | } |
3890 | 426613db | j_mayer | |
3891 | 99e300ef | Blue Swirl | static void gen_hrfid(DisasContext *ctx) |
3892 | be147d08 | j_mayer | { |
3893 | be147d08 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3894 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3895 | be147d08 | j_mayer | #else
|
3896 | be147d08 | j_mayer | /* Restore CPU state */
|
3897 | 76db3ba4 | aurel32 | if (unlikely(ctx->mem_idx <= 1)) { |
3898 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
3899 | be147d08 | j_mayer | return;
|
3900 | be147d08 | j_mayer | } |
3901 | e5f17ac6 | Blue Swirl | gen_helper_hrfid(cpu_env); |
3902 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
3903 | be147d08 | j_mayer | #endif
|
3904 | be147d08 | j_mayer | } |
3905 | be147d08 | j_mayer | #endif
|
3906 | be147d08 | j_mayer | |
3907 | 79aceca5 | bellard | /* sc */
|
3908 | 417bf010 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
3909 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
|
3910 | 417bf010 | j_mayer | #else
|
3911 | 417bf010 | j_mayer | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
|
3912 | 417bf010 | j_mayer | #endif
|
3913 | 99e300ef | Blue Swirl | static void gen_sc(DisasContext *ctx) |
3914 | 79aceca5 | bellard | { |
3915 | e1833e1f | j_mayer | uint32_t lev; |
3916 | e1833e1f | j_mayer | |
3917 | e1833e1f | j_mayer | lev = (ctx->opcode >> 5) & 0x7F; |
3918 | e06fcd75 | aurel32 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
3919 | 79aceca5 | bellard | } |
3920 | 79aceca5 | bellard | |
3921 | 79aceca5 | bellard | /*** Trap ***/
|
3922 | 99e300ef | Blue Swirl | |
3923 | 54623277 | Blue Swirl | /* tw */
|
3924 | 99e300ef | Blue Swirl | static void gen_tw(DisasContext *ctx) |
3925 | 79aceca5 | bellard | { |
3926 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3927 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3928 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3929 | e5f17ac6 | Blue Swirl | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3930 | e5f17ac6 | Blue Swirl | t0); |
3931 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3932 | 79aceca5 | bellard | } |
3933 | 79aceca5 | bellard | |
3934 | 79aceca5 | bellard | /* twi */
|
3935 | 99e300ef | Blue Swirl | static void gen_twi(DisasContext *ctx) |
3936 | 79aceca5 | bellard | { |
3937 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3938 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3939 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3940 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3941 | e5f17ac6 | Blue Swirl | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
3942 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3943 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3944 | 79aceca5 | bellard | } |
3945 | 79aceca5 | bellard | |
3946 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
3947 | d9bce9d9 | j_mayer | /* td */
|
3948 | 99e300ef | Blue Swirl | static void gen_td(DisasContext *ctx) |
3949 | d9bce9d9 | j_mayer | { |
3950 | cab3bee2 | aurel32 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
3951 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3952 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3953 | e5f17ac6 | Blue Swirl | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3954 | e5f17ac6 | Blue Swirl | t0); |
3955 | cab3bee2 | aurel32 | tcg_temp_free_i32(t0); |
3956 | d9bce9d9 | j_mayer | } |
3957 | d9bce9d9 | j_mayer | |
3958 | d9bce9d9 | j_mayer | /* tdi */
|
3959 | 99e300ef | Blue Swirl | static void gen_tdi(DisasContext *ctx) |
3960 | d9bce9d9 | j_mayer | { |
3961 | cab3bee2 | aurel32 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3962 | cab3bee2 | aurel32 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); |
3963 | db9a231d | Aurelien Jarno | /* Update the nip since this might generate a trap exception */
|
3964 | db9a231d | Aurelien Jarno | gen_update_nip(ctx, ctx->nip); |
3965 | e5f17ac6 | Blue Swirl | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
3966 | cab3bee2 | aurel32 | tcg_temp_free(t0); |
3967 | cab3bee2 | aurel32 | tcg_temp_free_i32(t1); |
3968 | d9bce9d9 | j_mayer | } |
3969 | d9bce9d9 | j_mayer | #endif
|
3970 | d9bce9d9 | j_mayer | |
3971 | 79aceca5 | bellard | /*** Processor control ***/
|
3972 | 99e300ef | Blue Swirl | |
3973 | da91a00f | Richard Henderson | static void gen_read_xer(TCGv dst) |
3974 | da91a00f | Richard Henderson | { |
3975 | da91a00f | Richard Henderson | TCGv t0 = tcg_temp_new(); |
3976 | da91a00f | Richard Henderson | TCGv t1 = tcg_temp_new(); |
3977 | da91a00f | Richard Henderson | TCGv t2 = tcg_temp_new(); |
3978 | da91a00f | Richard Henderson | tcg_gen_mov_tl(dst, cpu_xer); |
3979 | da91a00f | Richard Henderson | tcg_gen_shli_tl(t0, cpu_so, XER_SO); |
3980 | da91a00f | Richard Henderson | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); |
3981 | da91a00f | Richard Henderson | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); |
3982 | da91a00f | Richard Henderson | tcg_gen_or_tl(t0, t0, t1); |
3983 | da91a00f | Richard Henderson | tcg_gen_or_tl(dst, dst, t2); |
3984 | da91a00f | Richard Henderson | tcg_gen_or_tl(dst, dst, t0); |
3985 | da91a00f | Richard Henderson | tcg_temp_free(t0); |
3986 | da91a00f | Richard Henderson | tcg_temp_free(t1); |
3987 | da91a00f | Richard Henderson | tcg_temp_free(t2); |
3988 | da91a00f | Richard Henderson | } |
3989 | da91a00f | Richard Henderson | |
3990 | da91a00f | Richard Henderson | static void gen_write_xer(TCGv src) |
3991 | da91a00f | Richard Henderson | { |
3992 | da91a00f | Richard Henderson | tcg_gen_andi_tl(cpu_xer, src, |
3993 | da91a00f | Richard Henderson | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); |
3994 | da91a00f | Richard Henderson | tcg_gen_shri_tl(cpu_so, src, XER_SO); |
3995 | da91a00f | Richard Henderson | tcg_gen_shri_tl(cpu_ov, src, XER_OV); |
3996 | da91a00f | Richard Henderson | tcg_gen_shri_tl(cpu_ca, src, XER_CA); |
3997 | da91a00f | Richard Henderson | tcg_gen_andi_tl(cpu_so, cpu_so, 1);
|
3998 | da91a00f | Richard Henderson | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
|
3999 | da91a00f | Richard Henderson | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
|
4000 | da91a00f | Richard Henderson | } |
4001 | da91a00f | Richard Henderson | |
4002 | 54623277 | Blue Swirl | /* mcrxr */
|
4003 | 99e300ef | Blue Swirl | static void gen_mcrxr(DisasContext *ctx) |
4004 | 79aceca5 | bellard | { |
4005 | da91a00f | Richard Henderson | TCGv_i32 t0 = tcg_temp_new_i32(); |
4006 | da91a00f | Richard Henderson | TCGv_i32 t1 = tcg_temp_new_i32(); |
4007 | da91a00f | Richard Henderson | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; |
4008 | da91a00f | Richard Henderson | |
4009 | da91a00f | Richard Henderson | tcg_gen_trunc_tl_i32(t0, cpu_so); |
4010 | da91a00f | Richard Henderson | tcg_gen_trunc_tl_i32(t1, cpu_ov); |
4011 | da91a00f | Richard Henderson | tcg_gen_trunc_tl_i32(dst, cpu_ca); |
4012 | da91a00f | Richard Henderson | tcg_gen_shri_i32(t0, t0, 2);
|
4013 | da91a00f | Richard Henderson | tcg_gen_shri_i32(t1, t1, 1);
|
4014 | da91a00f | Richard Henderson | tcg_gen_or_i32(dst, dst, t0); |
4015 | da91a00f | Richard Henderson | tcg_gen_or_i32(dst, dst, t1); |
4016 | da91a00f | Richard Henderson | tcg_temp_free_i32(t0); |
4017 | da91a00f | Richard Henderson | tcg_temp_free_i32(t1); |
4018 | da91a00f | Richard Henderson | |
4019 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 0);
|
4020 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
4021 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 0);
|
4022 | 79aceca5 | bellard | } |
4023 | 79aceca5 | bellard | |
4024 | 0cfe11ea | aurel32 | /* mfcr mfocrf */
|
4025 | 99e300ef | Blue Swirl | static void gen_mfcr(DisasContext *ctx) |
4026 | 79aceca5 | bellard | { |
4027 | 76a66253 | j_mayer | uint32_t crm, crn; |
4028 | 3b46e624 | ths | |
4029 | 76a66253 | j_mayer | if (likely(ctx->opcode & 0x00100000)) { |
4030 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
4031 | 8dd640e4 | malc | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
4032 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
4033 | e1571908 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
|
4034 | 0497d2f4 | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4035 | 0497d2f4 | aurel32 | cpu_gpr[rD(ctx->opcode)], crn * 4);
|
4036 | 76a66253 | j_mayer | } |
4037 | d9bce9d9 | j_mayer | } else {
|
4038 | 651721b2 | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4039 | 651721b2 | aurel32 | tcg_gen_mov_i32(t0, cpu_crf[0]);
|
4040 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4041 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[1]);
|
4042 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4043 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[2]);
|
4044 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4045 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[3]);
|
4046 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4047 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[4]);
|
4048 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4049 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[5]);
|
4050 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4051 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[6]);
|
4052 | 651721b2 | aurel32 | tcg_gen_shli_i32(t0, t0, 4);
|
4053 | 651721b2 | aurel32 | tcg_gen_or_i32(t0, t0, cpu_crf[7]);
|
4054 | 651721b2 | aurel32 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4055 | 651721b2 | aurel32 | tcg_temp_free_i32(t0); |
4056 | d9bce9d9 | j_mayer | } |
4057 | 79aceca5 | bellard | } |
4058 | 79aceca5 | bellard | |
4059 | 79aceca5 | bellard | /* mfmsr */
|
4060 | 99e300ef | Blue Swirl | static void gen_mfmsr(DisasContext *ctx) |
4061 | 79aceca5 | bellard | { |
4062 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4063 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4064 | 9a64fbe4 | bellard | #else
|
4065 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4066 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4067 | 9fddaa0c | bellard | return;
|
4068 | 9a64fbe4 | bellard | } |
4069 | 6527f6ea | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
4070 | 9a64fbe4 | bellard | #endif
|
4071 | 79aceca5 | bellard | } |
4072 | 79aceca5 | bellard | |
4073 | 7b13448f | Blue Swirl | static void spr_noaccess(void *opaque, int gprn, int sprn) |
4074 | 3fc6c082 | bellard | { |
4075 | 7b13448f | Blue Swirl | #if 0
|
4076 | 3fc6c082 | bellard | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
|
4077 | 3fc6c082 | bellard | printf("ERROR: try to access SPR %d !\n", sprn);
|
4078 | 7b13448f | Blue Swirl | #endif
|
4079 | 3fc6c082 | bellard | } |
4080 | 3fc6c082 | bellard | #define SPR_NOACCESS (&spr_noaccess)
|
4081 | 3fc6c082 | bellard | |
4082 | 79aceca5 | bellard | /* mfspr */
|
4083 | 636aa200 | Blue Swirl | static inline void gen_op_mfspr(DisasContext *ctx) |
4084 | 79aceca5 | bellard | { |
4085 | 45d827d2 | aurel32 | void (*read_cb)(void *opaque, int gprn, int sprn); |
4086 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
4087 | 79aceca5 | bellard | |
4088 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
4089 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
4090 | be147d08 | j_mayer | read_cb = ctx->spr_cb[sprn].hea_read; |
4091 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
4092 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].oea_read; |
4093 | 3fc6c082 | bellard | else
|
4094 | 9a64fbe4 | bellard | #endif
|
4095 | 3fc6c082 | bellard | read_cb = ctx->spr_cb[sprn].uea_read; |
4096 | 76a66253 | j_mayer | if (likely(read_cb != NULL)) { |
4097 | 76a66253 | j_mayer | if (likely(read_cb != SPR_NOACCESS)) {
|
4098 | 45d827d2 | aurel32 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
4099 | 3fc6c082 | bellard | } else {
|
4100 | 3fc6c082 | bellard | /* Privilege exception */
|
4101 | 9fceefa7 | j_mayer | /* This is a hack to avoid warnings when running Linux:
|
4102 | 9fceefa7 | j_mayer | * this OS breaks the PowerPC virtualisation model,
|
4103 | 9fceefa7 | j_mayer | * allowing userland application to read the PVR
|
4104 | 9fceefa7 | j_mayer | */
|
4105 | 9fceefa7 | j_mayer | if (sprn != SPR_PVR) {
|
4106 | c05541ee | Anton Blanchard | qemu_log("Trying to read privileged spr %d (0x%03x) at "
|
4107 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4108 | c05541ee | Anton Blanchard | printf("Trying to read privileged spr %d (0x%03x) at "
|
4109 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4110 | f24e5695 | bellard | } |
4111 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4112 | 79aceca5 | bellard | } |
4113 | 3fc6c082 | bellard | } else {
|
4114 | 3fc6c082 | bellard | /* Not defined */
|
4115 | c05541ee | Anton Blanchard | qemu_log("Trying to read invalid spr %d (0x%03x) at "
|
4116 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4117 | c05541ee | Anton Blanchard | printf("Trying to read invalid spr %d (0x%03x) at "
|
4118 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4119 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
4120 | 79aceca5 | bellard | } |
4121 | 79aceca5 | bellard | } |
4122 | 79aceca5 | bellard | |
4123 | 99e300ef | Blue Swirl | static void gen_mfspr(DisasContext *ctx) |
4124 | 79aceca5 | bellard | { |
4125 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
4126 | 76a66253 | j_mayer | } |
4127 | 3fc6c082 | bellard | |
4128 | 3fc6c082 | bellard | /* mftb */
|
4129 | 99e300ef | Blue Swirl | static void gen_mftb(DisasContext *ctx) |
4130 | 3fc6c082 | bellard | { |
4131 | 3fc6c082 | bellard | gen_op_mfspr(ctx); |
4132 | 79aceca5 | bellard | } |
4133 | 79aceca5 | bellard | |
4134 | 0cfe11ea | aurel32 | /* mtcrf mtocrf*/
|
4135 | 99e300ef | Blue Swirl | static void gen_mtcrf(DisasContext *ctx) |
4136 | 79aceca5 | bellard | { |
4137 | 76a66253 | j_mayer | uint32_t crm, crn; |
4138 | 3b46e624 | ths | |
4139 | 76a66253 | j_mayer | crm = CRM(ctx->opcode); |
4140 | 8dd640e4 | malc | if (likely((ctx->opcode & 0x00100000))) { |
4141 | 8dd640e4 | malc | if (crm && ((crm & (crm - 1)) == 0)) { |
4142 | 8dd640e4 | malc | TCGv_i32 temp = tcg_temp_new_i32(); |
4143 | 0cfe11ea | aurel32 | crn = ctz32 (crm); |
4144 | 8dd640e4 | malc | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
4145 | 0cfe11ea | aurel32 | tcg_gen_shri_i32(temp, temp, crn * 4);
|
4146 | 0cfe11ea | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); |
4147 | 8dd640e4 | malc | tcg_temp_free_i32(temp); |
4148 | 8dd640e4 | malc | } |
4149 | 76a66253 | j_mayer | } else {
|
4150 | 651721b2 | aurel32 | TCGv_i32 temp = tcg_temp_new_i32(); |
4151 | 651721b2 | aurel32 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
4152 | 651721b2 | aurel32 | for (crn = 0 ; crn < 8 ; crn++) { |
4153 | 651721b2 | aurel32 | if (crm & (1 << crn)) { |
4154 | 651721b2 | aurel32 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); |
4155 | 651721b2 | aurel32 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
4156 | 651721b2 | aurel32 | } |
4157 | 651721b2 | aurel32 | } |
4158 | a7812ae4 | pbrook | tcg_temp_free_i32(temp); |
4159 | 76a66253 | j_mayer | } |
4160 | 79aceca5 | bellard | } |
4161 | 79aceca5 | bellard | |
4162 | 79aceca5 | bellard | /* mtmsr */
|
4163 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
4164 | 99e300ef | Blue Swirl | static void gen_mtmsrd(DisasContext *ctx) |
4165 | 426613db | j_mayer | { |
4166 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4167 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4168 | 426613db | j_mayer | #else
|
4169 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4170 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4171 | 426613db | j_mayer | return;
|
4172 | 426613db | j_mayer | } |
4173 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
4174 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
4175 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
4176 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
4177 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
4178 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4179 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
4180 | be147d08 | j_mayer | } else {
|
4181 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
4182 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
4183 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
4184 | 056b05f8 | j_mayer | */
|
4185 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
4186 | e5f17ac6 | Blue Swirl | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
4187 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
4188 | be147d08 | j_mayer | /* Note that mtmsr is not always defined as context-synchronizing */
|
4189 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
4190 | be147d08 | j_mayer | } |
4191 | 426613db | j_mayer | #endif
|
4192 | 426613db | j_mayer | } |
4193 | 426613db | j_mayer | #endif
|
4194 | 426613db | j_mayer | |
4195 | 99e300ef | Blue Swirl | static void gen_mtmsr(DisasContext *ctx) |
4196 | 79aceca5 | bellard | { |
4197 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4198 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4199 | 9a64fbe4 | bellard | #else
|
4200 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4201 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4202 | 9fddaa0c | bellard | return;
|
4203 | 9a64fbe4 | bellard | } |
4204 | be147d08 | j_mayer | if (ctx->opcode & 0x00010000) { |
4205 | be147d08 | j_mayer | /* Special form that does not need any synchronisation */
|
4206 | 6527f6ea | aurel32 | TCGv t0 = tcg_temp_new(); |
4207 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); |
4208 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); |
4209 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4210 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
4211 | be147d08 | j_mayer | } else {
|
4212 | 8018dc63 | Alexander Graf | TCGv msr = tcg_temp_new(); |
4213 | 8018dc63 | Alexander Graf | |
4214 | 056b05f8 | j_mayer | /* XXX: we need to update nip before the store
|
4215 | 056b05f8 | j_mayer | * if we enter power saving mode, we will exit the loop
|
4216 | 056b05f8 | j_mayer | * directly from ppc_store_msr
|
4217 | 056b05f8 | j_mayer | */
|
4218 | be147d08 | j_mayer | gen_update_nip(ctx, ctx->nip); |
4219 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
4220 | 8018dc63 | Alexander Graf | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4221 | 8018dc63 | Alexander Graf | #else
|
4222 | 8018dc63 | Alexander Graf | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); |
4223 | d9bce9d9 | j_mayer | #endif
|
4224 | e5f17ac6 | Blue Swirl | gen_helper_store_msr(cpu_env, msr); |
4225 | be147d08 | j_mayer | /* Must stop the translation as machine state (may have) changed */
|
4226 | 6527f6ea | aurel32 | /* Note that mtmsr is not always defined as context-synchronizing */
|
4227 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
4228 | be147d08 | j_mayer | } |
4229 | 9a64fbe4 | bellard | #endif
|
4230 | 79aceca5 | bellard | } |
4231 | 79aceca5 | bellard | |
4232 | 79aceca5 | bellard | /* mtspr */
|
4233 | 99e300ef | Blue Swirl | static void gen_mtspr(DisasContext *ctx) |
4234 | 79aceca5 | bellard | { |
4235 | 45d827d2 | aurel32 | void (*write_cb)(void *opaque, int sprn, int gprn); |
4236 | 79aceca5 | bellard | uint32_t sprn = SPR(ctx->opcode); |
4237 | 79aceca5 | bellard | |
4238 | 3fc6c082 | bellard | #if !defined(CONFIG_USER_ONLY)
|
4239 | 76db3ba4 | aurel32 | if (ctx->mem_idx == 2) |
4240 | be147d08 | j_mayer | write_cb = ctx->spr_cb[sprn].hea_write; |
4241 | 76db3ba4 | aurel32 | else if (ctx->mem_idx) |
4242 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].oea_write; |
4243 | 3fc6c082 | bellard | else
|
4244 | 9a64fbe4 | bellard | #endif
|
4245 | 3fc6c082 | bellard | write_cb = ctx->spr_cb[sprn].uea_write; |
4246 | 76a66253 | j_mayer | if (likely(write_cb != NULL)) { |
4247 | 76a66253 | j_mayer | if (likely(write_cb != SPR_NOACCESS)) {
|
4248 | 45d827d2 | aurel32 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
4249 | 3fc6c082 | bellard | } else {
|
4250 | 3fc6c082 | bellard | /* Privilege exception */
|
4251 | c05541ee | Anton Blanchard | qemu_log("Trying to write privileged spr %d (0x%03x) at "
|
4252 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4253 | c05541ee | Anton Blanchard | printf("Trying to write privileged spr %d (0x%03x) at "
|
4254 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4255 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4256 | 76a66253 | j_mayer | } |
4257 | 3fc6c082 | bellard | } else {
|
4258 | 3fc6c082 | bellard | /* Not defined */
|
4259 | c05541ee | Anton Blanchard | qemu_log("Trying to write invalid spr %d (0x%03x) at "
|
4260 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4261 | c05541ee | Anton Blanchard | printf("Trying to write invalid spr %d (0x%03x) at "
|
4262 | c05541ee | Anton Blanchard | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); |
4263 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
4264 | 79aceca5 | bellard | } |
4265 | 79aceca5 | bellard | } |
4266 | 79aceca5 | bellard | |
4267 | 79aceca5 | bellard | /*** Cache management ***/
|
4268 | 99e300ef | Blue Swirl | |
4269 | 54623277 | Blue Swirl | /* dcbf */
|
4270 | 99e300ef | Blue Swirl | static void gen_dcbf(DisasContext *ctx) |
4271 | 79aceca5 | bellard | { |
4272 | dac454af | j_mayer | /* XXX: specification says this is treated as a load by the MMU */
|
4273 | 76db3ba4 | aurel32 | TCGv t0; |
4274 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4275 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4276 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4277 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
4278 | fea0c503 | aurel32 | tcg_temp_free(t0); |
4279 | 79aceca5 | bellard | } |
4280 | 79aceca5 | bellard | |
4281 | 79aceca5 | bellard | /* dcbi (Supervisor only) */
|
4282 | 99e300ef | Blue Swirl | static void gen_dcbi(DisasContext *ctx) |
4283 | 79aceca5 | bellard | { |
4284 | a541f297 | bellard | #if defined(CONFIG_USER_ONLY)
|
4285 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4286 | a541f297 | bellard | #else
|
4287 | b61f2753 | aurel32 | TCGv EA, val; |
4288 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4289 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4290 | 9fddaa0c | bellard | return;
|
4291 | 9a64fbe4 | bellard | } |
4292 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
4293 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4294 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
4295 | a7812ae4 | pbrook | val = tcg_temp_new(); |
4296 | 76a66253 | j_mayer | /* XXX: specification says this should be treated as a store by the MMU */
|
4297 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, val, EA); |
4298 | 76db3ba4 | aurel32 | gen_qemu_st8(ctx, val, EA); |
4299 | b61f2753 | aurel32 | tcg_temp_free(val); |
4300 | b61f2753 | aurel32 | tcg_temp_free(EA); |
4301 | a541f297 | bellard | #endif
|
4302 | 79aceca5 | bellard | } |
4303 | 79aceca5 | bellard | |
4304 | 79aceca5 | bellard | /* dcdst */
|
4305 | 99e300ef | Blue Swirl | static void gen_dcbst(DisasContext *ctx) |
4306 | 79aceca5 | bellard | { |
4307 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU */
|
4308 | 76db3ba4 | aurel32 | TCGv t0; |
4309 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4310 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4311 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4312 | 76db3ba4 | aurel32 | gen_qemu_ld8u(ctx, t0, t0); |
4313 | fea0c503 | aurel32 | tcg_temp_free(t0); |
4314 | 79aceca5 | bellard | } |
4315 | 79aceca5 | bellard | |
4316 | 79aceca5 | bellard | /* dcbt */
|
4317 | 99e300ef | Blue Swirl | static void gen_dcbt(DisasContext *ctx) |
4318 | 79aceca5 | bellard | { |
4319 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4320 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
4321 | 76a66253 | j_mayer | * but does not generate any exception
|
4322 | 76a66253 | j_mayer | */
|
4323 | 79aceca5 | bellard | } |
4324 | 79aceca5 | bellard | |
4325 | 79aceca5 | bellard | /* dcbtst */
|
4326 | 99e300ef | Blue Swirl | static void gen_dcbtst(DisasContext *ctx) |
4327 | 79aceca5 | bellard | { |
4328 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4329 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
4330 | 76a66253 | j_mayer | * but does not generate any exception
|
4331 | 76a66253 | j_mayer | */
|
4332 | 79aceca5 | bellard | } |
4333 | 79aceca5 | bellard | |
4334 | 79aceca5 | bellard | /* dcbz */
|
4335 | 99e300ef | Blue Swirl | static void gen_dcbz(DisasContext *ctx) |
4336 | 79aceca5 | bellard | { |
4337 | 8e33944f | Alexander Graf | TCGv tcgv_addr; |
4338 | 8e33944f | Alexander Graf | TCGv_i32 tcgv_is_dcbzl; |
4339 | 8e33944f | Alexander Graf | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; |
4340 | d63001d1 | j_mayer | |
4341 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4342 | 799a8c8d | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
4343 | 799a8c8d | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
4344 | 8e33944f | Alexander Graf | tcgv_addr = tcg_temp_new(); |
4345 | 8e33944f | Alexander Graf | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); |
4346 | 8e33944f | Alexander Graf | |
4347 | 8e33944f | Alexander Graf | gen_addr_reg_index(ctx, tcgv_addr); |
4348 | 8e33944f | Alexander Graf | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); |
4349 | 8e33944f | Alexander Graf | |
4350 | 8e33944f | Alexander Graf | tcg_temp_free(tcgv_addr); |
4351 | 8e33944f | Alexander Graf | tcg_temp_free_i32(tcgv_is_dcbzl); |
4352 | 79aceca5 | bellard | } |
4353 | 79aceca5 | bellard | |
4354 | ae1c1a3d | aurel32 | /* dst / dstt */
|
4355 | 99e300ef | Blue Swirl | static void gen_dst(DisasContext *ctx) |
4356 | ae1c1a3d | aurel32 | { |
4357 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
4358 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
4359 | ae1c1a3d | aurel32 | } else {
|
4360 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4361 | ae1c1a3d | aurel32 | } |
4362 | ae1c1a3d | aurel32 | } |
4363 | ae1c1a3d | aurel32 | |
4364 | ae1c1a3d | aurel32 | /* dstst /dststt */
|
4365 | 99e300ef | Blue Swirl | static void gen_dstst(DisasContext *ctx) |
4366 | ae1c1a3d | aurel32 | { |
4367 | ae1c1a3d | aurel32 | if (rA(ctx->opcode) == 0) { |
4368 | ae1c1a3d | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
4369 | ae1c1a3d | aurel32 | } else {
|
4370 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4371 | ae1c1a3d | aurel32 | } |
4372 | ae1c1a3d | aurel32 | |
4373 | ae1c1a3d | aurel32 | } |
4374 | ae1c1a3d | aurel32 | |
4375 | ae1c1a3d | aurel32 | /* dss / dssall */
|
4376 | 99e300ef | Blue Swirl | static void gen_dss(DisasContext *ctx) |
4377 | ae1c1a3d | aurel32 | { |
4378 | ae1c1a3d | aurel32 | /* interpreted as no-op */
|
4379 | ae1c1a3d | aurel32 | } |
4380 | ae1c1a3d | aurel32 | |
4381 | 79aceca5 | bellard | /* icbi */
|
4382 | 99e300ef | Blue Swirl | static void gen_icbi(DisasContext *ctx) |
4383 | 79aceca5 | bellard | { |
4384 | 76db3ba4 | aurel32 | TCGv t0; |
4385 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
4386 | 30032c94 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4387 | 30032c94 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4388 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4389 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4390 | 2f5a189c | Blue Swirl | gen_helper_icbi(cpu_env, t0); |
4391 | 37d269df | aurel32 | tcg_temp_free(t0); |
4392 | 79aceca5 | bellard | } |
4393 | 79aceca5 | bellard | |
4394 | 79aceca5 | bellard | /* Optional: */
|
4395 | 79aceca5 | bellard | /* dcba */
|
4396 | 99e300ef | Blue Swirl | static void gen_dcba(DisasContext *ctx) |
4397 | 79aceca5 | bellard | { |
4398 | 0db1b20e | j_mayer | /* interpreted as no-op */
|
4399 | 0db1b20e | j_mayer | /* XXX: specification say this is treated as a store by the MMU
|
4400 | 0db1b20e | j_mayer | * but does not generate any exception
|
4401 | 0db1b20e | j_mayer | */
|
4402 | 79aceca5 | bellard | } |
4403 | 79aceca5 | bellard | |
4404 | 79aceca5 | bellard | /*** Segment register manipulation ***/
|
4405 | 79aceca5 | bellard | /* Supervisor only: */
|
4406 | 99e300ef | Blue Swirl | |
4407 | 54623277 | Blue Swirl | /* mfsr */
|
4408 | 99e300ef | Blue Swirl | static void gen_mfsr(DisasContext *ctx) |
4409 | 79aceca5 | bellard | { |
4410 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4411 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4412 | 9a64fbe4 | bellard | #else
|
4413 | 74d37793 | aurel32 | TCGv t0; |
4414 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4415 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4416 | 9fddaa0c | bellard | return;
|
4417 | 9a64fbe4 | bellard | } |
4418 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4419 | c6c7cf05 | Blue Swirl | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4420 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4421 | 9a64fbe4 | bellard | #endif
|
4422 | 79aceca5 | bellard | } |
4423 | 79aceca5 | bellard | |
4424 | 79aceca5 | bellard | /* mfsrin */
|
4425 | 99e300ef | Blue Swirl | static void gen_mfsrin(DisasContext *ctx) |
4426 | 79aceca5 | bellard | { |
4427 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4428 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4429 | 9a64fbe4 | bellard | #else
|
4430 | 74d37793 | aurel32 | TCGv t0; |
4431 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4432 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4433 | 9fddaa0c | bellard | return;
|
4434 | 9a64fbe4 | bellard | } |
4435 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4436 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4437 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4438 | c6c7cf05 | Blue Swirl | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4439 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4440 | 9a64fbe4 | bellard | #endif
|
4441 | 79aceca5 | bellard | } |
4442 | 79aceca5 | bellard | |
4443 | 79aceca5 | bellard | /* mtsr */
|
4444 | 99e300ef | Blue Swirl | static void gen_mtsr(DisasContext *ctx) |
4445 | 79aceca5 | bellard | { |
4446 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4447 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4448 | 9a64fbe4 | bellard | #else
|
4449 | 74d37793 | aurel32 | TCGv t0; |
4450 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4451 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4452 | 9fddaa0c | bellard | return;
|
4453 | 9a64fbe4 | bellard | } |
4454 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4455 | c6c7cf05 | Blue Swirl | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
4456 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4457 | 9a64fbe4 | bellard | #endif
|
4458 | 79aceca5 | bellard | } |
4459 | 79aceca5 | bellard | |
4460 | 79aceca5 | bellard | /* mtsrin */
|
4461 | 99e300ef | Blue Swirl | static void gen_mtsrin(DisasContext *ctx) |
4462 | 79aceca5 | bellard | { |
4463 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4464 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4465 | 9a64fbe4 | bellard | #else
|
4466 | 74d37793 | aurel32 | TCGv t0; |
4467 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4468 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4469 | 9fddaa0c | bellard | return;
|
4470 | 9a64fbe4 | bellard | } |
4471 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4472 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4473 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4474 | c6c7cf05 | Blue Swirl | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
4475 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4476 | 9a64fbe4 | bellard | #endif
|
4477 | 79aceca5 | bellard | } |
4478 | 79aceca5 | bellard | |
4479 | 12de9a39 | j_mayer | #if defined(TARGET_PPC64)
|
4480 | 12de9a39 | j_mayer | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
|
4481 | e8eaa2c0 | Blue Swirl | |
4482 | 54623277 | Blue Swirl | /* mfsr */
|
4483 | e8eaa2c0 | Blue Swirl | static void gen_mfsr_64b(DisasContext *ctx) |
4484 | 12de9a39 | j_mayer | { |
4485 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4486 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4487 | 12de9a39 | j_mayer | #else
|
4488 | 74d37793 | aurel32 | TCGv t0; |
4489 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4490 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4491 | 12de9a39 | j_mayer | return;
|
4492 | 12de9a39 | j_mayer | } |
4493 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4494 | c6c7cf05 | Blue Swirl | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4495 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4496 | 12de9a39 | j_mayer | #endif
|
4497 | 12de9a39 | j_mayer | } |
4498 | 12de9a39 | j_mayer | |
4499 | 12de9a39 | j_mayer | /* mfsrin */
|
4500 | e8eaa2c0 | Blue Swirl | static void gen_mfsrin_64b(DisasContext *ctx) |
4501 | 12de9a39 | j_mayer | { |
4502 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4503 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4504 | 12de9a39 | j_mayer | #else
|
4505 | 74d37793 | aurel32 | TCGv t0; |
4506 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4507 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4508 | 12de9a39 | j_mayer | return;
|
4509 | 12de9a39 | j_mayer | } |
4510 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4511 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4512 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4513 | c6c7cf05 | Blue Swirl | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4514 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4515 | 12de9a39 | j_mayer | #endif
|
4516 | 12de9a39 | j_mayer | } |
4517 | 12de9a39 | j_mayer | |
4518 | 12de9a39 | j_mayer | /* mtsr */
|
4519 | e8eaa2c0 | Blue Swirl | static void gen_mtsr_64b(DisasContext *ctx) |
4520 | 12de9a39 | j_mayer | { |
4521 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4522 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4523 | 12de9a39 | j_mayer | #else
|
4524 | 74d37793 | aurel32 | TCGv t0; |
4525 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4526 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4527 | 12de9a39 | j_mayer | return;
|
4528 | 12de9a39 | j_mayer | } |
4529 | 74d37793 | aurel32 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4530 | c6c7cf05 | Blue Swirl | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
4531 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4532 | 12de9a39 | j_mayer | #endif
|
4533 | 12de9a39 | j_mayer | } |
4534 | 12de9a39 | j_mayer | |
4535 | 12de9a39 | j_mayer | /* mtsrin */
|
4536 | e8eaa2c0 | Blue Swirl | static void gen_mtsrin_64b(DisasContext *ctx) |
4537 | 12de9a39 | j_mayer | { |
4538 | 12de9a39 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4539 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4540 | 12de9a39 | j_mayer | #else
|
4541 | 74d37793 | aurel32 | TCGv t0; |
4542 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4543 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4544 | 12de9a39 | j_mayer | return;
|
4545 | 12de9a39 | j_mayer | } |
4546 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
4547 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
|
4548 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
4549 | c6c7cf05 | Blue Swirl | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
4550 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4551 | 12de9a39 | j_mayer | #endif
|
4552 | 12de9a39 | j_mayer | } |
4553 | f6b868fc | blueswir1 | |
4554 | f6b868fc | blueswir1 | /* slbmte */
|
4555 | e8eaa2c0 | Blue Swirl | static void gen_slbmte(DisasContext *ctx) |
4556 | f6b868fc | blueswir1 | { |
4557 | f6b868fc | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4558 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4559 | f6b868fc | blueswir1 | #else
|
4560 | f6b868fc | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4561 | f6b868fc | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4562 | f6b868fc | blueswir1 | return;
|
4563 | f6b868fc | blueswir1 | } |
4564 | c6c7cf05 | Blue Swirl | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4565 | c6c7cf05 | Blue Swirl | cpu_gpr[rS(ctx->opcode)]); |
4566 | f6b868fc | blueswir1 | #endif
|
4567 | f6b868fc | blueswir1 | } |
4568 | f6b868fc | blueswir1 | |
4569 | efdef95f | David Gibson | static void gen_slbmfee(DisasContext *ctx) |
4570 | efdef95f | David Gibson | { |
4571 | efdef95f | David Gibson | #if defined(CONFIG_USER_ONLY)
|
4572 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4573 | efdef95f | David Gibson | #else
|
4574 | efdef95f | David Gibson | if (unlikely(!ctx->mem_idx)) {
|
4575 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4576 | efdef95f | David Gibson | return;
|
4577 | efdef95f | David Gibson | } |
4578 | c6c7cf05 | Blue Swirl | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
4579 | efdef95f | David Gibson | cpu_gpr[rB(ctx->opcode)]); |
4580 | efdef95f | David Gibson | #endif
|
4581 | efdef95f | David Gibson | } |
4582 | efdef95f | David Gibson | |
4583 | efdef95f | David Gibson | static void gen_slbmfev(DisasContext *ctx) |
4584 | efdef95f | David Gibson | { |
4585 | efdef95f | David Gibson | #if defined(CONFIG_USER_ONLY)
|
4586 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4587 | efdef95f | David Gibson | #else
|
4588 | efdef95f | David Gibson | if (unlikely(!ctx->mem_idx)) {
|
4589 | efdef95f | David Gibson | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4590 | efdef95f | David Gibson | return;
|
4591 | efdef95f | David Gibson | } |
4592 | c6c7cf05 | Blue Swirl | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
4593 | efdef95f | David Gibson | cpu_gpr[rB(ctx->opcode)]); |
4594 | efdef95f | David Gibson | #endif
|
4595 | efdef95f | David Gibson | } |
4596 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
4597 | 12de9a39 | j_mayer | |
4598 | 79aceca5 | bellard | /*** Lookaside buffer management ***/
|
4599 | 76db3ba4 | aurel32 | /* Optional & mem_idx only: */
|
4600 | 99e300ef | Blue Swirl | |
4601 | 54623277 | Blue Swirl | /* tlbia */
|
4602 | 99e300ef | Blue Swirl | static void gen_tlbia(DisasContext *ctx) |
4603 | 79aceca5 | bellard | { |
4604 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4605 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4606 | 9a64fbe4 | bellard | #else
|
4607 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4608 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4609 | 9fddaa0c | bellard | return;
|
4610 | 9a64fbe4 | bellard | } |
4611 | c6c7cf05 | Blue Swirl | gen_helper_tlbia(cpu_env); |
4612 | 9a64fbe4 | bellard | #endif
|
4613 | 79aceca5 | bellard | } |
4614 | 79aceca5 | bellard | |
4615 | bf14b1ce | blueswir1 | /* tlbiel */
|
4616 | 99e300ef | Blue Swirl | static void gen_tlbiel(DisasContext *ctx) |
4617 | bf14b1ce | blueswir1 | { |
4618 | bf14b1ce | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4619 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4620 | bf14b1ce | blueswir1 | #else
|
4621 | bf14b1ce | blueswir1 | if (unlikely(!ctx->mem_idx)) {
|
4622 | bf14b1ce | blueswir1 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4623 | bf14b1ce | blueswir1 | return;
|
4624 | bf14b1ce | blueswir1 | } |
4625 | c6c7cf05 | Blue Swirl | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
4626 | bf14b1ce | blueswir1 | #endif
|
4627 | bf14b1ce | blueswir1 | } |
4628 | bf14b1ce | blueswir1 | |
4629 | 79aceca5 | bellard | /* tlbie */
|
4630 | 99e300ef | Blue Swirl | static void gen_tlbie(DisasContext *ctx) |
4631 | 79aceca5 | bellard | { |
4632 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4633 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4634 | 9a64fbe4 | bellard | #else
|
4635 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4636 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4637 | 9fddaa0c | bellard | return;
|
4638 | 9a64fbe4 | bellard | } |
4639 | 9ca3f7f3 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
4640 | 74d37793 | aurel32 | TCGv t0 = tcg_temp_new(); |
4641 | 74d37793 | aurel32 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
4642 | c6c7cf05 | Blue Swirl | gen_helper_tlbie(cpu_env, t0); |
4643 | 74d37793 | aurel32 | tcg_temp_free(t0); |
4644 | 9ca3f7f3 | Richard Henderson | } else {
|
4645 | c6c7cf05 | Blue Swirl | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
4646 | 9ca3f7f3 | Richard Henderson | } |
4647 | 9a64fbe4 | bellard | #endif
|
4648 | 79aceca5 | bellard | } |
4649 | 79aceca5 | bellard | |
4650 | 79aceca5 | bellard | /* tlbsync */
|
4651 | 99e300ef | Blue Swirl | static void gen_tlbsync(DisasContext *ctx) |
4652 | 79aceca5 | bellard | { |
4653 | 9a64fbe4 | bellard | #if defined(CONFIG_USER_ONLY)
|
4654 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4655 | 9a64fbe4 | bellard | #else
|
4656 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4657 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4658 | 9fddaa0c | bellard | return;
|
4659 | 9a64fbe4 | bellard | } |
4660 | 9a64fbe4 | bellard | /* This has no effect: it should ensure that all previous
|
4661 | 9a64fbe4 | bellard | * tlbie have completed
|
4662 | 9a64fbe4 | bellard | */
|
4663 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
4664 | 9a64fbe4 | bellard | #endif
|
4665 | 79aceca5 | bellard | } |
4666 | 79aceca5 | bellard | |
4667 | 426613db | j_mayer | #if defined(TARGET_PPC64)
|
4668 | 426613db | j_mayer | /* slbia */
|
4669 | 99e300ef | Blue Swirl | static void gen_slbia(DisasContext *ctx) |
4670 | 426613db | j_mayer | { |
4671 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4672 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4673 | 426613db | j_mayer | #else
|
4674 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4675 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4676 | 426613db | j_mayer | return;
|
4677 | 426613db | j_mayer | } |
4678 | c6c7cf05 | Blue Swirl | gen_helper_slbia(cpu_env); |
4679 | 426613db | j_mayer | #endif
|
4680 | 426613db | j_mayer | } |
4681 | 426613db | j_mayer | |
4682 | 426613db | j_mayer | /* slbie */
|
4683 | 99e300ef | Blue Swirl | static void gen_slbie(DisasContext *ctx) |
4684 | 426613db | j_mayer | { |
4685 | 426613db | j_mayer | #if defined(CONFIG_USER_ONLY)
|
4686 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4687 | 426613db | j_mayer | #else
|
4688 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
4689 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
4690 | 426613db | j_mayer | return;
|
4691 | 426613db | j_mayer | } |
4692 | c6c7cf05 | Blue Swirl | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
4693 | 426613db | j_mayer | #endif
|
4694 | 426613db | j_mayer | } |
4695 | 426613db | j_mayer | #endif
|
4696 | 426613db | j_mayer | |
4697 | 79aceca5 | bellard | /*** External control ***/
|
4698 | 79aceca5 | bellard | /* Optional: */
|
4699 | 99e300ef | Blue Swirl | |
4700 | 54623277 | Blue Swirl | /* eciwx */
|
4701 | 99e300ef | Blue Swirl | static void gen_eciwx(DisasContext *ctx) |
4702 | 79aceca5 | bellard | { |
4703 | 76db3ba4 | aurel32 | TCGv t0; |
4704 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4705 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4706 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4707 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4708 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4709 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4710 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4711 | 76a66253 | j_mayer | } |
4712 | 76a66253 | j_mayer | |
4713 | 76a66253 | j_mayer | /* ecowx */
|
4714 | 99e300ef | Blue Swirl | static void gen_ecowx(DisasContext *ctx) |
4715 | 76a66253 | j_mayer | { |
4716 | 76db3ba4 | aurel32 | TCGv t0; |
4717 | fa407c03 | aurel32 | /* Should check EAR[E] ! */
|
4718 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_EXT); |
4719 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
4720 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4721 | fa407c03 | aurel32 | gen_check_align(ctx, t0, 0x03);
|
4722 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
4723 | fa407c03 | aurel32 | tcg_temp_free(t0); |
4724 | 76a66253 | j_mayer | } |
4725 | 76a66253 | j_mayer | |
4726 | 76a66253 | j_mayer | /* PowerPC 601 specific instructions */
|
4727 | 99e300ef | Blue Swirl | |
4728 | 54623277 | Blue Swirl | /* abs - abs. */
|
4729 | 99e300ef | Blue Swirl | static void gen_abs(DisasContext *ctx) |
4730 | 76a66253 | j_mayer | { |
4731 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4732 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4733 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4734 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4735 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4736 | 22e0e173 | aurel32 | gen_set_label(l1); |
4737 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4738 | 22e0e173 | aurel32 | gen_set_label(l2); |
4739 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4740 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4741 | 76a66253 | j_mayer | } |
4742 | 76a66253 | j_mayer | |
4743 | 76a66253 | j_mayer | /* abso - abso. */
|
4744 | 99e300ef | Blue Swirl | static void gen_abso(DisasContext *ctx) |
4745 | 76a66253 | j_mayer | { |
4746 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4747 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4748 | 22e0e173 | aurel32 | int l3 = gen_new_label();
|
4749 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4750 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
4751 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
|
4752 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
|
4753 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 1);
|
4754 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 1);
|
4755 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4756 | 22e0e173 | aurel32 | gen_set_label(l1); |
4757 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4758 | 22e0e173 | aurel32 | tcg_gen_br(l3); |
4759 | 22e0e173 | aurel32 | gen_set_label(l2); |
4760 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4761 | 22e0e173 | aurel32 | gen_set_label(l3); |
4762 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4763 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4764 | 76a66253 | j_mayer | } |
4765 | 76a66253 | j_mayer | |
4766 | 76a66253 | j_mayer | /* clcs */
|
4767 | 99e300ef | Blue Swirl | static void gen_clcs(DisasContext *ctx) |
4768 | 76a66253 | j_mayer | { |
4769 | 22e0e173 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
4770 | d523dd00 | Blue Swirl | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4771 | 22e0e173 | aurel32 | tcg_temp_free_i32(t0); |
4772 | c7697e1f | j_mayer | /* Rc=1 sets CR0 to an undefined state */
|
4773 | 76a66253 | j_mayer | } |
4774 | 76a66253 | j_mayer | |
4775 | 76a66253 | j_mayer | /* div - div. */
|
4776 | 99e300ef | Blue Swirl | static void gen_div(DisasContext *ctx) |
4777 | 76a66253 | j_mayer | { |
4778 | d15f74fb | Blue Swirl | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4779 | d15f74fb | Blue Swirl | cpu_gpr[rB(ctx->opcode)]); |
4780 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4781 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4782 | 76a66253 | j_mayer | } |
4783 | 76a66253 | j_mayer | |
4784 | 76a66253 | j_mayer | /* divo - divo. */
|
4785 | 99e300ef | Blue Swirl | static void gen_divo(DisasContext *ctx) |
4786 | 76a66253 | j_mayer | { |
4787 | d15f74fb | Blue Swirl | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4788 | d15f74fb | Blue Swirl | cpu_gpr[rB(ctx->opcode)]); |
4789 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4790 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4791 | 76a66253 | j_mayer | } |
4792 | 76a66253 | j_mayer | |
4793 | 76a66253 | j_mayer | /* divs - divs. */
|
4794 | 99e300ef | Blue Swirl | static void gen_divs(DisasContext *ctx) |
4795 | 76a66253 | j_mayer | { |
4796 | d15f74fb | Blue Swirl | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4797 | d15f74fb | Blue Swirl | cpu_gpr[rB(ctx->opcode)]); |
4798 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4799 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4800 | 76a66253 | j_mayer | } |
4801 | 76a66253 | j_mayer | |
4802 | 76a66253 | j_mayer | /* divso - divso. */
|
4803 | 99e300ef | Blue Swirl | static void gen_divso(DisasContext *ctx) |
4804 | 76a66253 | j_mayer | { |
4805 | d15f74fb | Blue Swirl | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4806 | d15f74fb | Blue Swirl | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4807 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4808 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4809 | 76a66253 | j_mayer | } |
4810 | 76a66253 | j_mayer | |
4811 | 76a66253 | j_mayer | /* doz - doz. */
|
4812 | 99e300ef | Blue Swirl | static void gen_doz(DisasContext *ctx) |
4813 | 76a66253 | j_mayer | { |
4814 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4815 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4816 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4817 | 22e0e173 | aurel32 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4818 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4819 | 22e0e173 | aurel32 | gen_set_label(l1); |
4820 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4821 | 22e0e173 | aurel32 | gen_set_label(l2); |
4822 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4823 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4824 | 76a66253 | j_mayer | } |
4825 | 76a66253 | j_mayer | |
4826 | 76a66253 | j_mayer | /* dozo - dozo. */
|
4827 | 99e300ef | Blue Swirl | static void gen_dozo(DisasContext *ctx) |
4828 | 76a66253 | j_mayer | { |
4829 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4830 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4831 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4832 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4833 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4834 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4835 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
4836 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4837 | 22e0e173 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4838 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4839 | 22e0e173 | aurel32 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); |
4840 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
4841 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4842 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
4843 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 1);
|
4844 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 1);
|
4845 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4846 | 22e0e173 | aurel32 | gen_set_label(l1); |
4847 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4848 | 22e0e173 | aurel32 | gen_set_label(l2); |
4849 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4850 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4851 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4852 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4853 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4854 | 76a66253 | j_mayer | } |
4855 | 76a66253 | j_mayer | |
4856 | 76a66253 | j_mayer | /* dozi */
|
4857 | 99e300ef | Blue Swirl | static void gen_dozi(DisasContext *ctx) |
4858 | 76a66253 | j_mayer | { |
4859 | 22e0e173 | aurel32 | target_long simm = SIMM(ctx->opcode); |
4860 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4861 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4862 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4863 | 22e0e173 | aurel32 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); |
4864 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4865 | 22e0e173 | aurel32 | gen_set_label(l1); |
4866 | 22e0e173 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
|
4867 | 22e0e173 | aurel32 | gen_set_label(l2); |
4868 | 22e0e173 | aurel32 | if (unlikely(Rc(ctx->opcode) != 0)) |
4869 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4870 | 76a66253 | j_mayer | } |
4871 | 76a66253 | j_mayer | |
4872 | 76a66253 | j_mayer | /* lscbx - lscbx. */
|
4873 | 99e300ef | Blue Swirl | static void gen_lscbx(DisasContext *ctx) |
4874 | 76a66253 | j_mayer | { |
4875 | bdb4b689 | aurel32 | TCGv t0 = tcg_temp_new(); |
4876 | bdb4b689 | aurel32 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); |
4877 | bdb4b689 | aurel32 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); |
4878 | bdb4b689 | aurel32 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); |
4879 | 76a66253 | j_mayer | |
4880 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
4881 | 76a66253 | j_mayer | /* NIP cannot be restored if the memory exception comes from an helper */
|
4882 | d9bce9d9 | j_mayer | gen_update_nip(ctx, ctx->nip - 4);
|
4883 | 2f5a189c | Blue Swirl | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
4884 | bdb4b689 | aurel32 | tcg_temp_free_i32(t1); |
4885 | bdb4b689 | aurel32 | tcg_temp_free_i32(t2); |
4886 | bdb4b689 | aurel32 | tcg_temp_free_i32(t3); |
4887 | 3d7b417e | aurel32 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
|
4888 | bdb4b689 | aurel32 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
4889 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4890 | bdb4b689 | aurel32 | gen_set_Rc0(ctx, t0); |
4891 | bdb4b689 | aurel32 | tcg_temp_free(t0); |
4892 | 76a66253 | j_mayer | } |
4893 | 76a66253 | j_mayer | |
4894 | 76a66253 | j_mayer | /* maskg - maskg. */
|
4895 | 99e300ef | Blue Swirl | static void gen_maskg(DisasContext *ctx) |
4896 | 76a66253 | j_mayer | { |
4897 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4898 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4899 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4900 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4901 | 22e0e173 | aurel32 | TCGv t3 = tcg_temp_new(); |
4902 | 22e0e173 | aurel32 | tcg_gen_movi_tl(t3, 0xFFFFFFFF);
|
4903 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
4904 | 22e0e173 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
|
4905 | 22e0e173 | aurel32 | tcg_gen_addi_tl(t2, t0, 1);
|
4906 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t2, t3, t2); |
4907 | 22e0e173 | aurel32 | tcg_gen_shr_tl(t3, t3, t1); |
4908 | 22e0e173 | aurel32 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); |
4909 | 22e0e173 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
4910 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4911 | 22e0e173 | aurel32 | gen_set_label(l1); |
4912 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4913 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4914 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4915 | 22e0e173 | aurel32 | tcg_temp_free(t3); |
4916 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4917 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4918 | 76a66253 | j_mayer | } |
4919 | 76a66253 | j_mayer | |
4920 | 76a66253 | j_mayer | /* maskir - maskir. */
|
4921 | 99e300ef | Blue Swirl | static void gen_maskir(DisasContext *ctx) |
4922 | 76a66253 | j_mayer | { |
4923 | 22e0e173 | aurel32 | TCGv t0 = tcg_temp_new(); |
4924 | 22e0e173 | aurel32 | TCGv t1 = tcg_temp_new(); |
4925 | 22e0e173 | aurel32 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4926 | 22e0e173 | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
4927 | 22e0e173 | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
4928 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
4929 | 22e0e173 | aurel32 | tcg_temp_free(t1); |
4930 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4931 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
4932 | 76a66253 | j_mayer | } |
4933 | 76a66253 | j_mayer | |
4934 | 76a66253 | j_mayer | /* mul - mul. */
|
4935 | 99e300ef | Blue Swirl | static void gen_mul(DisasContext *ctx) |
4936 | 76a66253 | j_mayer | { |
4937 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4938 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4939 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4940 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4941 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4942 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4943 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4944 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4945 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4946 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4947 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4948 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4949 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4950 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4951 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4952 | 76a66253 | j_mayer | } |
4953 | 76a66253 | j_mayer | |
4954 | 76a66253 | j_mayer | /* mulo - mulo. */
|
4955 | 99e300ef | Blue Swirl | static void gen_mulo(DisasContext *ctx) |
4956 | 76a66253 | j_mayer | { |
4957 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4958 | 22e0e173 | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4959 | 22e0e173 | aurel32 | TCGv_i64 t1 = tcg_temp_new_i64(); |
4960 | 22e0e173 | aurel32 | TCGv t2 = tcg_temp_new(); |
4961 | 22e0e173 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
4962 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
4963 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4964 | 22e0e173 | aurel32 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
4965 | 22e0e173 | aurel32 | tcg_gen_mul_i64(t0, t0, t1); |
4966 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(t2, t0); |
4967 | 22e0e173 | aurel32 | gen_store_spr(SPR_MQ, t2); |
4968 | 22e0e173 | aurel32 | tcg_gen_shri_i64(t1, t0, 32);
|
4969 | 22e0e173 | aurel32 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
4970 | 22e0e173 | aurel32 | tcg_gen_ext32s_i64(t1, t0); |
4971 | 22e0e173 | aurel32 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
4972 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 1);
|
4973 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 1);
|
4974 | 22e0e173 | aurel32 | gen_set_label(l1); |
4975 | 22e0e173 | aurel32 | tcg_temp_free_i64(t0); |
4976 | 22e0e173 | aurel32 | tcg_temp_free_i64(t1); |
4977 | 22e0e173 | aurel32 | tcg_temp_free(t2); |
4978 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4979 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4980 | 76a66253 | j_mayer | } |
4981 | 76a66253 | j_mayer | |
4982 | 76a66253 | j_mayer | /* nabs - nabs. */
|
4983 | 99e300ef | Blue Swirl | static void gen_nabs(DisasContext *ctx) |
4984 | 76a66253 | j_mayer | { |
4985 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
4986 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
4987 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
4988 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4989 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
4990 | 22e0e173 | aurel32 | gen_set_label(l1); |
4991 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
4992 | 22e0e173 | aurel32 | gen_set_label(l2); |
4993 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
4994 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
4995 | 76a66253 | j_mayer | } |
4996 | 76a66253 | j_mayer | |
4997 | 76a66253 | j_mayer | /* nabso - nabso. */
|
4998 | 99e300ef | Blue Swirl | static void gen_nabso(DisasContext *ctx) |
4999 | 76a66253 | j_mayer | { |
5000 | 22e0e173 | aurel32 | int l1 = gen_new_label();
|
5001 | 22e0e173 | aurel32 | int l2 = gen_new_label();
|
5002 | 22e0e173 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
|
5003 | 22e0e173 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5004 | 22e0e173 | aurel32 | tcg_gen_br(l2); |
5005 | 22e0e173 | aurel32 | gen_set_label(l1); |
5006 | 22e0e173 | aurel32 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5007 | 22e0e173 | aurel32 | gen_set_label(l2); |
5008 | 22e0e173 | aurel32 | /* nabs never overflows */
|
5009 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
5010 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5011 | 22e0e173 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5012 | 76a66253 | j_mayer | } |
5013 | 76a66253 | j_mayer | |
5014 | 76a66253 | j_mayer | /* rlmi - rlmi. */
|
5015 | 99e300ef | Blue Swirl | static void gen_rlmi(DisasContext *ctx) |
5016 | 76a66253 | j_mayer | { |
5017 | 7487953d | aurel32 | uint32_t mb = MB(ctx->opcode); |
5018 | 7487953d | aurel32 | uint32_t me = ME(ctx->opcode); |
5019 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5020 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5021 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5022 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); |
5023 | 7487953d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); |
5024 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
5025 | 7487953d | aurel32 | tcg_temp_free(t0); |
5026 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5027 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5028 | 76a66253 | j_mayer | } |
5029 | 76a66253 | j_mayer | |
5030 | 76a66253 | j_mayer | /* rrib - rrib. */
|
5031 | 99e300ef | Blue Swirl | static void gen_rrib(DisasContext *ctx) |
5032 | 76a66253 | j_mayer | { |
5033 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5034 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5035 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5036 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0x80000000);
|
5037 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
5038 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5039 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
5040 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); |
5041 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5042 | 7487953d | aurel32 | tcg_temp_free(t0); |
5043 | 7487953d | aurel32 | tcg_temp_free(t1); |
5044 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5045 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5046 | 76a66253 | j_mayer | } |
5047 | 76a66253 | j_mayer | |
5048 | 76a66253 | j_mayer | /* sle - sle. */
|
5049 | 99e300ef | Blue Swirl | static void gen_sle(DisasContext *ctx) |
5050 | 76a66253 | j_mayer | { |
5051 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5052 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5053 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5054 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5055 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
5056 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5057 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5058 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5059 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5060 | 7487953d | aurel32 | tcg_temp_free(t0); |
5061 | 7487953d | aurel32 | tcg_temp_free(t1); |
5062 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5063 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5064 | 76a66253 | j_mayer | } |
5065 | 76a66253 | j_mayer | |
5066 | 76a66253 | j_mayer | /* sleq - sleq. */
|
5067 | 99e300ef | Blue Swirl | static void gen_sleq(DisasContext *ctx) |
5068 | 76a66253 | j_mayer | { |
5069 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5070 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5071 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
5072 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5073 | 7487953d | aurel32 | tcg_gen_movi_tl(t2, 0xFFFFFFFF);
|
5074 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, t2, t0); |
5075 | 7487953d | aurel32 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5076 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
5077 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5078 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
5079 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
5080 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5081 | 7487953d | aurel32 | tcg_temp_free(t0); |
5082 | 7487953d | aurel32 | tcg_temp_free(t1); |
5083 | 7487953d | aurel32 | tcg_temp_free(t2); |
5084 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5085 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5086 | 76a66253 | j_mayer | } |
5087 | 76a66253 | j_mayer | |
5088 | 76a66253 | j_mayer | /* sliq - sliq. */
|
5089 | 99e300ef | Blue Swirl | static void gen_sliq(DisasContext *ctx) |
5090 | 76a66253 | j_mayer | { |
5091 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
5092 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5093 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5094 | 7487953d | aurel32 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5095 | 7487953d | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
5096 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5097 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5098 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5099 | 7487953d | aurel32 | tcg_temp_free(t0); |
5100 | 7487953d | aurel32 | tcg_temp_free(t1); |
5101 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5102 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5103 | 76a66253 | j_mayer | } |
5104 | 76a66253 | j_mayer | |
5105 | 76a66253 | j_mayer | /* slliq - slliq. */
|
5106 | 99e300ef | Blue Swirl | static void gen_slliq(DisasContext *ctx) |
5107 | 76a66253 | j_mayer | { |
5108 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
5109 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5110 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5111 | 7487953d | aurel32 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5112 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
5113 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5114 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
|
5115 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
|
5116 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5117 | 7487953d | aurel32 | tcg_temp_free(t0); |
5118 | 7487953d | aurel32 | tcg_temp_free(t1); |
5119 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5120 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5121 | 76a66253 | j_mayer | } |
5122 | 76a66253 | j_mayer | |
5123 | 76a66253 | j_mayer | /* sllq - sllq. */
|
5124 | 99e300ef | Blue Swirl | static void gen_sllq(DisasContext *ctx) |
5125 | 76a66253 | j_mayer | { |
5126 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5127 | 7487953d | aurel32 | int l2 = gen_new_label();
|
5128 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
5129 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
5130 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
5131 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5132 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
5133 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, t1, t2); |
5134 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5135 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
5136 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
5137 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5138 | 7487953d | aurel32 | tcg_gen_br(l2); |
5139 | 7487953d | aurel32 | gen_set_label(l1); |
5140 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5141 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
5142 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t2, t1); |
5143 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5144 | 7487953d | aurel32 | gen_set_label(l2); |
5145 | 7487953d | aurel32 | tcg_temp_free(t0); |
5146 | 7487953d | aurel32 | tcg_temp_free(t1); |
5147 | 7487953d | aurel32 | tcg_temp_free(t2); |
5148 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5149 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5150 | 76a66253 | j_mayer | } |
5151 | 76a66253 | j_mayer | |
5152 | 76a66253 | j_mayer | /* slq - slq. */
|
5153 | 99e300ef | Blue Swirl | static void gen_slq(DisasContext *ctx) |
5154 | 76a66253 | j_mayer | { |
5155 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5156 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5157 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5158 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5159 | 7487953d | aurel32 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5160 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
5161 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5162 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5163 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5164 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5165 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5166 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
5167 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
5168 | 7487953d | aurel32 | gen_set_label(l1); |
5169 | 7487953d | aurel32 | tcg_temp_free(t0); |
5170 | 7487953d | aurel32 | tcg_temp_free(t1); |
5171 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5172 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5173 | 76a66253 | j_mayer | } |
5174 | 76a66253 | j_mayer | |
5175 | d9bce9d9 | j_mayer | /* sraiq - sraiq. */
|
5176 | 99e300ef | Blue Swirl | static void gen_sraiq(DisasContext *ctx) |
5177 | 76a66253 | j_mayer | { |
5178 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
5179 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5180 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5181 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5182 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5183 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
5184 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t1); |
5185 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5186 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 0);
|
5187 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
|
5188 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
|
5189 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 1);
|
5190 | 7487953d | aurel32 | gen_set_label(l1); |
5191 | 7487953d | aurel32 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
5192 | 7487953d | aurel32 | tcg_temp_free(t0); |
5193 | 7487953d | aurel32 | tcg_temp_free(t1); |
5194 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5195 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5196 | 76a66253 | j_mayer | } |
5197 | 76a66253 | j_mayer | |
5198 | 76a66253 | j_mayer | /* sraq - sraq. */
|
5199 | 99e300ef | Blue Swirl | static void gen_sraq(DisasContext *ctx) |
5200 | 76a66253 | j_mayer | { |
5201 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5202 | 7487953d | aurel32 | int l2 = gen_new_label();
|
5203 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5204 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
5205 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
5206 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5207 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5208 | 7487953d | aurel32 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); |
5209 | 7487953d | aurel32 | tcg_gen_subfi_tl(t2, 32, t2);
|
5210 | 7487953d | aurel32 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); |
5211 | 7487953d | aurel32 | tcg_gen_or_tl(t0, t0, t2); |
5212 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5213 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5214 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
|
5215 | 7487953d | aurel32 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); |
5216 | 7487953d | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
|
5217 | 7487953d | aurel32 | gen_set_label(l1); |
5218 | 7487953d | aurel32 | tcg_temp_free(t0); |
5219 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
5220 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 0);
|
5221 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
|
5222 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
|
5223 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ca, 1);
|
5224 | 7487953d | aurel32 | gen_set_label(l2); |
5225 | 7487953d | aurel32 | tcg_temp_free(t1); |
5226 | 7487953d | aurel32 | tcg_temp_free(t2); |
5227 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5228 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5229 | 76a66253 | j_mayer | } |
5230 | 76a66253 | j_mayer | |
5231 | 76a66253 | j_mayer | /* sre - sre. */
|
5232 | 99e300ef | Blue Swirl | static void gen_sre(DisasContext *ctx) |
5233 | 76a66253 | j_mayer | { |
5234 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5235 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5236 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5237 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5238 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
5239 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5240 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5241 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5242 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5243 | 7487953d | aurel32 | tcg_temp_free(t0); |
5244 | 7487953d | aurel32 | tcg_temp_free(t1); |
5245 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5246 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5247 | 76a66253 | j_mayer | } |
5248 | 76a66253 | j_mayer | |
5249 | 76a66253 | j_mayer | /* srea - srea. */
|
5250 | 99e300ef | Blue Swirl | static void gen_srea(DisasContext *ctx) |
5251 | 76a66253 | j_mayer | { |
5252 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5253 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5254 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5255 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5256 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5257 | 7487953d | aurel32 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); |
5258 | 7487953d | aurel32 | tcg_temp_free(t0); |
5259 | 7487953d | aurel32 | tcg_temp_free(t1); |
5260 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5261 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5262 | 76a66253 | j_mayer | } |
5263 | 76a66253 | j_mayer | |
5264 | 76a66253 | j_mayer | /* sreq */
|
5265 | 99e300ef | Blue Swirl | static void gen_sreq(DisasContext *ctx) |
5266 | 76a66253 | j_mayer | { |
5267 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5268 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5269 | 7487953d | aurel32 | TCGv t2 = tcg_temp_new(); |
5270 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5271 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
5272 | 7487953d | aurel32 | tcg_gen_shr_tl(t1, t1, t0); |
5273 | 7487953d | aurel32 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5274 | 7487953d | aurel32 | gen_load_spr(t2, SPR_MQ); |
5275 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5276 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t1); |
5277 | 7487953d | aurel32 | tcg_gen_andc_tl(t2, t2, t1); |
5278 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
5279 | 7487953d | aurel32 | tcg_temp_free(t0); |
5280 | 7487953d | aurel32 | tcg_temp_free(t1); |
5281 | 7487953d | aurel32 | tcg_temp_free(t2); |
5282 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5283 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5284 | 76a66253 | j_mayer | } |
5285 | 76a66253 | j_mayer | |
5286 | 76a66253 | j_mayer | /* sriq */
|
5287 | 99e300ef | Blue Swirl | static void gen_sriq(DisasContext *ctx) |
5288 | 76a66253 | j_mayer | { |
5289 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
5290 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5291 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5292 | 7487953d | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5293 | 7487953d | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
|
5294 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5295 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5296 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5297 | 7487953d | aurel32 | tcg_temp_free(t0); |
5298 | 7487953d | aurel32 | tcg_temp_free(t1); |
5299 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5300 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5301 | 76a66253 | j_mayer | } |
5302 | 76a66253 | j_mayer | |
5303 | 76a66253 | j_mayer | /* srliq */
|
5304 | 99e300ef | Blue Swirl | static void gen_srliq(DisasContext *ctx) |
5305 | 76a66253 | j_mayer | { |
5306 | 7487953d | aurel32 | int sh = SH(ctx->opcode);
|
5307 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5308 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5309 | 7487953d | aurel32 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5310 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
5311 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t0); |
5312 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
|
5313 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
|
5314 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5315 | 7487953d | aurel32 | tcg_temp_free(t0); |
5316 | 7487953d | aurel32 | tcg_temp_free(t1); |
5317 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5318 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5319 | 76a66253 | j_mayer | } |
5320 | 76a66253 | j_mayer | |
5321 | 76a66253 | j_mayer | /* srlq */
|
5322 | 99e300ef | Blue Swirl | static void gen_srlq(DisasContext *ctx) |
5323 | 76a66253 | j_mayer | { |
5324 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5325 | 7487953d | aurel32 | int l2 = gen_new_label();
|
5326 | 7487953d | aurel32 | TCGv t0 = tcg_temp_local_new(); |
5327 | 7487953d | aurel32 | TCGv t1 = tcg_temp_local_new(); |
5328 | 7487953d | aurel32 | TCGv t2 = tcg_temp_local_new(); |
5329 | 7487953d | aurel32 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5330 | 7487953d | aurel32 | tcg_gen_movi_tl(t1, 0xFFFFFFFF);
|
5331 | 7487953d | aurel32 | tcg_gen_shr_tl(t2, t1, t2); |
5332 | 7487953d | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5333 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
5334 | 7487953d | aurel32 | gen_load_spr(t0, SPR_MQ); |
5335 | 7487953d | aurel32 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
5336 | 7487953d | aurel32 | tcg_gen_br(l2); |
5337 | 7487953d | aurel32 | gen_set_label(l1); |
5338 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5339 | 7487953d | aurel32 | tcg_gen_and_tl(t0, t0, t2); |
5340 | 7487953d | aurel32 | gen_load_spr(t1, SPR_MQ); |
5341 | 7487953d | aurel32 | tcg_gen_andc_tl(t1, t1, t2); |
5342 | 7487953d | aurel32 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5343 | 7487953d | aurel32 | gen_set_label(l2); |
5344 | 7487953d | aurel32 | tcg_temp_free(t0); |
5345 | 7487953d | aurel32 | tcg_temp_free(t1); |
5346 | 7487953d | aurel32 | tcg_temp_free(t2); |
5347 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5348 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5349 | 76a66253 | j_mayer | } |
5350 | 76a66253 | j_mayer | |
5351 | 76a66253 | j_mayer | /* srq */
|
5352 | 99e300ef | Blue Swirl | static void gen_srq(DisasContext *ctx) |
5353 | 76a66253 | j_mayer | { |
5354 | 7487953d | aurel32 | int l1 = gen_new_label();
|
5355 | 7487953d | aurel32 | TCGv t0 = tcg_temp_new(); |
5356 | 7487953d | aurel32 | TCGv t1 = tcg_temp_new(); |
5357 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
|
5358 | 7487953d | aurel32 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5359 | 7487953d | aurel32 | tcg_gen_subfi_tl(t1, 32, t1);
|
5360 | 7487953d | aurel32 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5361 | 7487953d | aurel32 | tcg_gen_or_tl(t1, t0, t1); |
5362 | 7487953d | aurel32 | gen_store_spr(SPR_MQ, t1); |
5363 | 7487953d | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
|
5364 | 7487953d | aurel32 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5365 | 7487953d | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
|
5366 | 7487953d | aurel32 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
|
5367 | 7487953d | aurel32 | gen_set_label(l1); |
5368 | 7487953d | aurel32 | tcg_temp_free(t0); |
5369 | 7487953d | aurel32 | tcg_temp_free(t1); |
5370 | 76a66253 | j_mayer | if (unlikely(Rc(ctx->opcode) != 0)) |
5371 | 7487953d | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5372 | 76a66253 | j_mayer | } |
5373 | 76a66253 | j_mayer | |
5374 | 76a66253 | j_mayer | /* PowerPC 602 specific instructions */
|
5375 | 99e300ef | Blue Swirl | |
5376 | 54623277 | Blue Swirl | /* dsa */
|
5377 | 99e300ef | Blue Swirl | static void gen_dsa(DisasContext *ctx) |
5378 | 76a66253 | j_mayer | { |
5379 | 76a66253 | j_mayer | /* XXX: TODO */
|
5380 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5381 | 76a66253 | j_mayer | } |
5382 | 76a66253 | j_mayer | |
5383 | 76a66253 | j_mayer | /* esa */
|
5384 | 99e300ef | Blue Swirl | static void gen_esa(DisasContext *ctx) |
5385 | 76a66253 | j_mayer | { |
5386 | 76a66253 | j_mayer | /* XXX: TODO */
|
5387 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5388 | 76a66253 | j_mayer | } |
5389 | 76a66253 | j_mayer | |
5390 | 76a66253 | j_mayer | /* mfrom */
|
5391 | 99e300ef | Blue Swirl | static void gen_mfrom(DisasContext *ctx) |
5392 | 76a66253 | j_mayer | { |
5393 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5394 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5395 | 76a66253 | j_mayer | #else
|
5396 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5397 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5398 | 76a66253 | j_mayer | return;
|
5399 | 76a66253 | j_mayer | } |
5400 | cf02a65c | aurel32 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5401 | 76a66253 | j_mayer | #endif
|
5402 | 76a66253 | j_mayer | } |
5403 | 76a66253 | j_mayer | |
5404 | 76a66253 | j_mayer | /* 602 - 603 - G2 TLB management */
|
5405 | e8eaa2c0 | Blue Swirl | |
5406 | 54623277 | Blue Swirl | /* tlbld */
|
5407 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_6xx(DisasContext *ctx) |
5408 | 76a66253 | j_mayer | { |
5409 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5410 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5411 | 76a66253 | j_mayer | #else
|
5412 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5413 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5414 | 76a66253 | j_mayer | return;
|
5415 | 76a66253 | j_mayer | } |
5416 | c6c7cf05 | Blue Swirl | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5417 | 76a66253 | j_mayer | #endif
|
5418 | 76a66253 | j_mayer | } |
5419 | 76a66253 | j_mayer | |
5420 | 76a66253 | j_mayer | /* tlbli */
|
5421 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_6xx(DisasContext *ctx) |
5422 | 76a66253 | j_mayer | { |
5423 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5424 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5425 | 76a66253 | j_mayer | #else
|
5426 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5427 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5428 | 76a66253 | j_mayer | return;
|
5429 | 76a66253 | j_mayer | } |
5430 | c6c7cf05 | Blue Swirl | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5431 | 76a66253 | j_mayer | #endif
|
5432 | 76a66253 | j_mayer | } |
5433 | 76a66253 | j_mayer | |
5434 | 7dbe11ac | j_mayer | /* 74xx TLB management */
|
5435 | e8eaa2c0 | Blue Swirl | |
5436 | 54623277 | Blue Swirl | /* tlbld */
|
5437 | e8eaa2c0 | Blue Swirl | static void gen_tlbld_74xx(DisasContext *ctx) |
5438 | 7dbe11ac | j_mayer | { |
5439 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5440 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5441 | 7dbe11ac | j_mayer | #else
|
5442 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5443 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5444 | 7dbe11ac | j_mayer | return;
|
5445 | 7dbe11ac | j_mayer | } |
5446 | c6c7cf05 | Blue Swirl | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5447 | 7dbe11ac | j_mayer | #endif
|
5448 | 7dbe11ac | j_mayer | } |
5449 | 7dbe11ac | j_mayer | |
5450 | 7dbe11ac | j_mayer | /* tlbli */
|
5451 | e8eaa2c0 | Blue Swirl | static void gen_tlbli_74xx(DisasContext *ctx) |
5452 | 7dbe11ac | j_mayer | { |
5453 | 7dbe11ac | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5454 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5455 | 7dbe11ac | j_mayer | #else
|
5456 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5457 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5458 | 7dbe11ac | j_mayer | return;
|
5459 | 7dbe11ac | j_mayer | } |
5460 | c6c7cf05 | Blue Swirl | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5461 | 7dbe11ac | j_mayer | #endif
|
5462 | 7dbe11ac | j_mayer | } |
5463 | 7dbe11ac | j_mayer | |
5464 | 76a66253 | j_mayer | /* POWER instructions not in PowerPC 601 */
|
5465 | 99e300ef | Blue Swirl | |
5466 | 54623277 | Blue Swirl | /* clf */
|
5467 | 99e300ef | Blue Swirl | static void gen_clf(DisasContext *ctx) |
5468 | 76a66253 | j_mayer | { |
5469 | 76a66253 | j_mayer | /* Cache line flush: implemented as no-op */
|
5470 | 76a66253 | j_mayer | } |
5471 | 76a66253 | j_mayer | |
5472 | 76a66253 | j_mayer | /* cli */
|
5473 | 99e300ef | Blue Swirl | static void gen_cli(DisasContext *ctx) |
5474 | 76a66253 | j_mayer | { |
5475 | 7f75ffd3 | blueswir1 | /* Cache line invalidate: privileged and treated as no-op */
|
5476 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5477 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5478 | 76a66253 | j_mayer | #else
|
5479 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5480 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5481 | 76a66253 | j_mayer | return;
|
5482 | 76a66253 | j_mayer | } |
5483 | 76a66253 | j_mayer | #endif
|
5484 | 76a66253 | j_mayer | } |
5485 | 76a66253 | j_mayer | |
5486 | 76a66253 | j_mayer | /* dclst */
|
5487 | 99e300ef | Blue Swirl | static void gen_dclst(DisasContext *ctx) |
5488 | 76a66253 | j_mayer | { |
5489 | 76a66253 | j_mayer | /* Data cache line store: treated as no-op */
|
5490 | 76a66253 | j_mayer | } |
5491 | 76a66253 | j_mayer | |
5492 | 99e300ef | Blue Swirl | static void gen_mfsri(DisasContext *ctx) |
5493 | 76a66253 | j_mayer | { |
5494 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5495 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5496 | 76a66253 | j_mayer | #else
|
5497 | 74d37793 | aurel32 | int ra = rA(ctx->opcode);
|
5498 | 74d37793 | aurel32 | int rd = rD(ctx->opcode);
|
5499 | 74d37793 | aurel32 | TCGv t0; |
5500 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5501 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5502 | 76a66253 | j_mayer | return;
|
5503 | 76a66253 | j_mayer | } |
5504 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
5505 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5506 | 74d37793 | aurel32 | tcg_gen_shri_tl(t0, t0, 28);
|
5507 | 74d37793 | aurel32 | tcg_gen_andi_tl(t0, t0, 0xF);
|
5508 | c6c7cf05 | Blue Swirl | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
5509 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5510 | 76a66253 | j_mayer | if (ra != 0 && ra != rd) |
5511 | 74d37793 | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
5512 | 76a66253 | j_mayer | #endif
|
5513 | 76a66253 | j_mayer | } |
5514 | 76a66253 | j_mayer | |
5515 | 99e300ef | Blue Swirl | static void gen_rac(DisasContext *ctx) |
5516 | 76a66253 | j_mayer | { |
5517 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5518 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5519 | 76a66253 | j_mayer | #else
|
5520 | 22e0e173 | aurel32 | TCGv t0; |
5521 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5522 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5523 | 76a66253 | j_mayer | return;
|
5524 | 76a66253 | j_mayer | } |
5525 | 22e0e173 | aurel32 | t0 = tcg_temp_new(); |
5526 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5527 | c6c7cf05 | Blue Swirl | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
5528 | 22e0e173 | aurel32 | tcg_temp_free(t0); |
5529 | 76a66253 | j_mayer | #endif
|
5530 | 76a66253 | j_mayer | } |
5531 | 76a66253 | j_mayer | |
5532 | 99e300ef | Blue Swirl | static void gen_rfsvc(DisasContext *ctx) |
5533 | 76a66253 | j_mayer | { |
5534 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5535 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5536 | 76a66253 | j_mayer | #else
|
5537 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5538 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5539 | 76a66253 | j_mayer | return;
|
5540 | 76a66253 | j_mayer | } |
5541 | e5f17ac6 | Blue Swirl | gen_helper_rfsvc(cpu_env); |
5542 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
5543 | 76a66253 | j_mayer | #endif
|
5544 | 76a66253 | j_mayer | } |
5545 | 76a66253 | j_mayer | |
5546 | 76a66253 | j_mayer | /* svc is not implemented for now */
|
5547 | 76a66253 | j_mayer | |
5548 | 76a66253 | j_mayer | /* POWER2 specific instructions */
|
5549 | 76a66253 | j_mayer | /* Quad manipulation (load/store two floats at a time) */
|
5550 | 76a66253 | j_mayer | |
5551 | 76a66253 | j_mayer | /* lfq */
|
5552 | 99e300ef | Blue Swirl | static void gen_lfq(DisasContext *ctx) |
5553 | 76a66253 | j_mayer | { |
5554 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5555 | 76db3ba4 | aurel32 | TCGv t0; |
5556 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5557 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5558 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5559 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5560 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5561 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5562 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5563 | 76a66253 | j_mayer | } |
5564 | 76a66253 | j_mayer | |
5565 | 76a66253 | j_mayer | /* lfqu */
|
5566 | 99e300ef | Blue Swirl | static void gen_lfqu(DisasContext *ctx) |
5567 | 76a66253 | j_mayer | { |
5568 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5569 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5570 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5571 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5572 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5573 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5574 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5575 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5576 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5577 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5578 | 76a66253 | j_mayer | if (ra != 0) |
5579 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5580 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5581 | 01a4afeb | aurel32 | tcg_temp_free(t1); |
5582 | 76a66253 | j_mayer | } |
5583 | 76a66253 | j_mayer | |
5584 | 76a66253 | j_mayer | /* lfqux */
|
5585 | 99e300ef | Blue Swirl | static void gen_lfqux(DisasContext *ctx) |
5586 | 76a66253 | j_mayer | { |
5587 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5588 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5589 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5590 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5591 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5592 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5593 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5594 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5595 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5596 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5597 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5598 | 76a66253 | j_mayer | if (ra != 0) |
5599 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5600 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5601 | 76a66253 | j_mayer | } |
5602 | 76a66253 | j_mayer | |
5603 | 76a66253 | j_mayer | /* lfqx */
|
5604 | 99e300ef | Blue Swirl | static void gen_lfqx(DisasContext *ctx) |
5605 | 76a66253 | j_mayer | { |
5606 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5607 | 76db3ba4 | aurel32 | TCGv t0; |
5608 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5609 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5610 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5611 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); |
5612 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5613 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5614 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5615 | 76a66253 | j_mayer | } |
5616 | 76a66253 | j_mayer | |
5617 | 76a66253 | j_mayer | /* stfq */
|
5618 | 99e300ef | Blue Swirl | static void gen_stfq(DisasContext *ctx) |
5619 | 76a66253 | j_mayer | { |
5620 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5621 | 76db3ba4 | aurel32 | TCGv t0; |
5622 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5623 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5624 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5625 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5626 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5627 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5628 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5629 | 76a66253 | j_mayer | } |
5630 | 76a66253 | j_mayer | |
5631 | 76a66253 | j_mayer | /* stfqu */
|
5632 | 99e300ef | Blue Swirl | static void gen_stfqu(DisasContext *ctx) |
5633 | 76a66253 | j_mayer | { |
5634 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5635 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5636 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5637 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5638 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5639 | 76db3ba4 | aurel32 | gen_addr_imm_index(ctx, t0, 0);
|
5640 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5641 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5642 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5643 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5644 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5645 | 76a66253 | j_mayer | if (ra != 0) |
5646 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5647 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5648 | 76a66253 | j_mayer | } |
5649 | 76a66253 | j_mayer | |
5650 | 76a66253 | j_mayer | /* stfqux */
|
5651 | 99e300ef | Blue Swirl | static void gen_stfqux(DisasContext *ctx) |
5652 | 76a66253 | j_mayer | { |
5653 | 76a66253 | j_mayer | int ra = rA(ctx->opcode);
|
5654 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5655 | 76db3ba4 | aurel32 | TCGv t0, t1; |
5656 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5657 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5658 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5659 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5660 | 76db3ba4 | aurel32 | t1 = tcg_temp_new(); |
5661 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t1, t0, 8);
|
5662 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); |
5663 | 76db3ba4 | aurel32 | tcg_temp_free(t1); |
5664 | 76a66253 | j_mayer | if (ra != 0) |
5665 | 01a4afeb | aurel32 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5666 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5667 | 76a66253 | j_mayer | } |
5668 | 76a66253 | j_mayer | |
5669 | 76a66253 | j_mayer | /* stfqx */
|
5670 | 99e300ef | Blue Swirl | static void gen_stfqx(DisasContext *ctx) |
5671 | 76a66253 | j_mayer | { |
5672 | 01a4afeb | aurel32 | int rd = rD(ctx->opcode);
|
5673 | 76db3ba4 | aurel32 | TCGv t0; |
5674 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5675 | 76db3ba4 | aurel32 | t0 = tcg_temp_new(); |
5676 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5677 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); |
5678 | 76db3ba4 | aurel32 | gen_addr_add(ctx, t0, t0, 8);
|
5679 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); |
5680 | 01a4afeb | aurel32 | tcg_temp_free(t0); |
5681 | 76a66253 | j_mayer | } |
5682 | 76a66253 | j_mayer | |
5683 | 76a66253 | j_mayer | /* BookE specific instructions */
|
5684 | 99e300ef | Blue Swirl | |
5685 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
5686 | 99e300ef | Blue Swirl | static void gen_mfapidi(DisasContext *ctx) |
5687 | 76a66253 | j_mayer | { |
5688 | 76a66253 | j_mayer | /* XXX: TODO */
|
5689 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5690 | 76a66253 | j_mayer | } |
5691 | 76a66253 | j_mayer | |
5692 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5693 | 99e300ef | Blue Swirl | static void gen_tlbiva(DisasContext *ctx) |
5694 | 76a66253 | j_mayer | { |
5695 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5696 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5697 | 76a66253 | j_mayer | #else
|
5698 | 74d37793 | aurel32 | TCGv t0; |
5699 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5700 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5701 | 76a66253 | j_mayer | return;
|
5702 | 76a66253 | j_mayer | } |
5703 | ec72e276 | aurel32 | t0 = tcg_temp_new(); |
5704 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
5705 | c6c7cf05 | Blue Swirl | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5706 | 74d37793 | aurel32 | tcg_temp_free(t0); |
5707 | 76a66253 | j_mayer | #endif
|
5708 | 76a66253 | j_mayer | } |
5709 | 76a66253 | j_mayer | |
5710 | 76a66253 | j_mayer | /* All 405 MAC instructions are translated here */
|
5711 | 636aa200 | Blue Swirl | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5712 | 636aa200 | Blue Swirl | int ra, int rb, int rt, int Rc) |
5713 | 76a66253 | j_mayer | { |
5714 | 182608d4 | aurel32 | TCGv t0, t1; |
5715 | 182608d4 | aurel32 | |
5716 | a7812ae4 | pbrook | t0 = tcg_temp_local_new(); |
5717 | a7812ae4 | pbrook | t1 = tcg_temp_local_new(); |
5718 | 182608d4 | aurel32 | |
5719 | 76a66253 | j_mayer | switch (opc3 & 0x0D) { |
5720 | 76a66253 | j_mayer | case 0x05: |
5721 | 76a66253 | j_mayer | /* macchw - macchw. - macchwo - macchwo. */
|
5722 | 76a66253 | j_mayer | /* macchws - macchws. - macchwso - macchwso. */
|
5723 | 76a66253 | j_mayer | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
|
5724 | 76a66253 | j_mayer | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
|
5725 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5726 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5727 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5728 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5729 | 76a66253 | j_mayer | break;
|
5730 | 76a66253 | j_mayer | case 0x04: |
5731 | 76a66253 | j_mayer | /* macchwu - macchwu. - macchwuo - macchwuo. */
|
5732 | 76a66253 | j_mayer | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
|
5733 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5734 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5735 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5736 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5737 | 76a66253 | j_mayer | break;
|
5738 | 76a66253 | j_mayer | case 0x01: |
5739 | 76a66253 | j_mayer | /* machhw - machhw. - machhwo - machhwo. */
|
5740 | 76a66253 | j_mayer | /* machhws - machhws. - machhwso - machhwso. */
|
5741 | 76a66253 | j_mayer | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
|
5742 | 76a66253 | j_mayer | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
|
5743 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5744 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
|
5745 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, t0); |
5746 | 182608d4 | aurel32 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
|
5747 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, t1); |
5748 | 76a66253 | j_mayer | break;
|
5749 | 76a66253 | j_mayer | case 0x00: |
5750 | 76a66253 | j_mayer | /* machhwu - machhwu. - machhwuo - machhwuo. */
|
5751 | 76a66253 | j_mayer | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
|
5752 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5753 | 182608d4 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
|
5754 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, t0); |
5755 | 182608d4 | aurel32 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
|
5756 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, t1); |
5757 | 76a66253 | j_mayer | break;
|
5758 | 76a66253 | j_mayer | case 0x0D: |
5759 | 76a66253 | j_mayer | /* maclhw - maclhw. - maclhwo - maclhwo. */
|
5760 | 76a66253 | j_mayer | /* maclhws - maclhws. - maclhwso - maclhwso. */
|
5761 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
|
5762 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
|
5763 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5764 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5765 | 182608d4 | aurel32 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); |
5766 | 76a66253 | j_mayer | break;
|
5767 | 76a66253 | j_mayer | case 0x0C: |
5768 | 76a66253 | j_mayer | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
|
5769 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
|
5770 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5771 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5772 | 182608d4 | aurel32 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); |
5773 | 76a66253 | j_mayer | break;
|
5774 | 76a66253 | j_mayer | } |
5775 | 76a66253 | j_mayer | if (opc2 & 0x04) { |
5776 | 182608d4 | aurel32 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */
|
5777 | 182608d4 | aurel32 | tcg_gen_mul_tl(t1, t0, t1); |
5778 | 182608d4 | aurel32 | if (opc2 & 0x02) { |
5779 | 182608d4 | aurel32 | /* nmultiply-and-accumulate (0x0E) */
|
5780 | 182608d4 | aurel32 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); |
5781 | 182608d4 | aurel32 | } else {
|
5782 | 182608d4 | aurel32 | /* multiply-and-accumulate (0x0C) */
|
5783 | 182608d4 | aurel32 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); |
5784 | 182608d4 | aurel32 | } |
5785 | 182608d4 | aurel32 | |
5786 | 182608d4 | aurel32 | if (opc3 & 0x12) { |
5787 | 182608d4 | aurel32 | /* Check overflow and/or saturate */
|
5788 | 182608d4 | aurel32 | int l1 = gen_new_label();
|
5789 | 182608d4 | aurel32 | |
5790 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5791 | 182608d4 | aurel32 | /* Start with XER OV disabled, the most likely case */
|
5792 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 0);
|
5793 | 182608d4 | aurel32 | } |
5794 | 182608d4 | aurel32 | if (opc3 & 0x01) { |
5795 | 182608d4 | aurel32 | /* Signed */
|
5796 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); |
5797 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
|
5798 | 182608d4 | aurel32 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); |
5799 | 182608d4 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
|
5800 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5801 | 182608d4 | aurel32 | /* Saturate */
|
5802 | 182608d4 | aurel32 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
|
5803 | 182608d4 | aurel32 | tcg_gen_xori_tl(t0, t0, 0x7fffffff);
|
5804 | 182608d4 | aurel32 | } |
5805 | 182608d4 | aurel32 | } else {
|
5806 | 182608d4 | aurel32 | /* Unsigned */
|
5807 | 182608d4 | aurel32 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
5808 | bdc4e053 | aurel32 | if (opc3 & 0x02) { |
5809 | 182608d4 | aurel32 | /* Saturate */
|
5810 | 182608d4 | aurel32 | tcg_gen_movi_tl(t0, UINT32_MAX); |
5811 | 182608d4 | aurel32 | } |
5812 | 182608d4 | aurel32 | } |
5813 | 182608d4 | aurel32 | if (opc3 & 0x10) { |
5814 | 182608d4 | aurel32 | /* Check overflow */
|
5815 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_ov, 1);
|
5816 | da91a00f | Richard Henderson | tcg_gen_movi_tl(cpu_so, 1);
|
5817 | 182608d4 | aurel32 | } |
5818 | 182608d4 | aurel32 | gen_set_label(l1); |
5819 | 182608d4 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rt], t0); |
5820 | 182608d4 | aurel32 | } |
5821 | 182608d4 | aurel32 | } else {
|
5822 | 182608d4 | aurel32 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); |
5823 | 76a66253 | j_mayer | } |
5824 | 182608d4 | aurel32 | tcg_temp_free(t0); |
5825 | 182608d4 | aurel32 | tcg_temp_free(t1); |
5826 | 76a66253 | j_mayer | if (unlikely(Rc) != 0) { |
5827 | 76a66253 | j_mayer | /* Update Rc0 */
|
5828 | 182608d4 | aurel32 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
5829 | 76a66253 | j_mayer | } |
5830 | 76a66253 | j_mayer | } |
5831 | 76a66253 | j_mayer | |
5832 | a750fc0b | j_mayer | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
5833 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
5834 | 76a66253 | j_mayer | { \ |
5835 | 76a66253 | j_mayer | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
5836 | 76a66253 | j_mayer | rD(ctx->opcode), Rc(ctx->opcode)); \ |
5837 | 76a66253 | j_mayer | } |
5838 | 76a66253 | j_mayer | |
5839 | 76a66253 | j_mayer | /* macchw - macchw. */
|
5840 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
5841 | 76a66253 | j_mayer | /* macchwo - macchwo. */
|
5842 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
5843 | 76a66253 | j_mayer | /* macchws - macchws. */
|
5844 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
5845 | 76a66253 | j_mayer | /* macchwso - macchwso. */
|
5846 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
5847 | 76a66253 | j_mayer | /* macchwsu - macchwsu. */
|
5848 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
5849 | 76a66253 | j_mayer | /* macchwsuo - macchwsuo. */
|
5850 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
5851 | 76a66253 | j_mayer | /* macchwu - macchwu. */
|
5852 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
5853 | 76a66253 | j_mayer | /* macchwuo - macchwuo. */
|
5854 | a750fc0b | j_mayer | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
5855 | 76a66253 | j_mayer | /* machhw - machhw. */
|
5856 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
5857 | 76a66253 | j_mayer | /* machhwo - machhwo. */
|
5858 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
5859 | 76a66253 | j_mayer | /* machhws - machhws. */
|
5860 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
5861 | 76a66253 | j_mayer | /* machhwso - machhwso. */
|
5862 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
5863 | 76a66253 | j_mayer | /* machhwsu - machhwsu. */
|
5864 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
5865 | 76a66253 | j_mayer | /* machhwsuo - machhwsuo. */
|
5866 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
5867 | 76a66253 | j_mayer | /* machhwu - machhwu. */
|
5868 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
5869 | 76a66253 | j_mayer | /* machhwuo - machhwuo. */
|
5870 | a750fc0b | j_mayer | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
5871 | 76a66253 | j_mayer | /* maclhw - maclhw. */
|
5872 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
5873 | 76a66253 | j_mayer | /* maclhwo - maclhwo. */
|
5874 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
5875 | 76a66253 | j_mayer | /* maclhws - maclhws. */
|
5876 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
5877 | 76a66253 | j_mayer | /* maclhwso - maclhwso. */
|
5878 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
5879 | 76a66253 | j_mayer | /* maclhwu - maclhwu. */
|
5880 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
5881 | 76a66253 | j_mayer | /* maclhwuo - maclhwuo. */
|
5882 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
5883 | 76a66253 | j_mayer | /* maclhwsu - maclhwsu. */
|
5884 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
5885 | 76a66253 | j_mayer | /* maclhwsuo - maclhwsuo. */
|
5886 | a750fc0b | j_mayer | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
5887 | 76a66253 | j_mayer | /* nmacchw - nmacchw. */
|
5888 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
5889 | 76a66253 | j_mayer | /* nmacchwo - nmacchwo. */
|
5890 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
5891 | 76a66253 | j_mayer | /* nmacchws - nmacchws. */
|
5892 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
5893 | 76a66253 | j_mayer | /* nmacchwso - nmacchwso. */
|
5894 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
5895 | 76a66253 | j_mayer | /* nmachhw - nmachhw. */
|
5896 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
5897 | 76a66253 | j_mayer | /* nmachhwo - nmachhwo. */
|
5898 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
5899 | 76a66253 | j_mayer | /* nmachhws - nmachhws. */
|
5900 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
5901 | 76a66253 | j_mayer | /* nmachhwso - nmachhwso. */
|
5902 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
5903 | 76a66253 | j_mayer | /* nmaclhw - nmaclhw. */
|
5904 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
5905 | 76a66253 | j_mayer | /* nmaclhwo - nmaclhwo. */
|
5906 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
5907 | 76a66253 | j_mayer | /* nmaclhws - nmaclhws. */
|
5908 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
5909 | 76a66253 | j_mayer | /* nmaclhwso - nmaclhwso. */
|
5910 | a750fc0b | j_mayer | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
5911 | 76a66253 | j_mayer | |
5912 | 76a66253 | j_mayer | /* mulchw - mulchw. */
|
5913 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
5914 | 76a66253 | j_mayer | /* mulchwu - mulchwu. */
|
5915 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
5916 | 76a66253 | j_mayer | /* mulhhw - mulhhw. */
|
5917 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
5918 | 76a66253 | j_mayer | /* mulhhwu - mulhhwu. */
|
5919 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
5920 | 76a66253 | j_mayer | /* mullhw - mullhw. */
|
5921 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
5922 | 76a66253 | j_mayer | /* mullhwu - mullhwu. */
|
5923 | a750fc0b | j_mayer | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
5924 | 76a66253 | j_mayer | |
5925 | 76a66253 | j_mayer | /* mfdcr */
|
5926 | 99e300ef | Blue Swirl | static void gen_mfdcr(DisasContext *ctx) |
5927 | 76a66253 | j_mayer | { |
5928 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5929 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5930 | 76a66253 | j_mayer | #else
|
5931 | 06dca6a7 | aurel32 | TCGv dcrn; |
5932 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5933 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5934 | 76a66253 | j_mayer | return;
|
5935 | 76a66253 | j_mayer | } |
5936 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5937 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5938 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5939 | d0f1562d | Blue Swirl | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
5940 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5941 | 76a66253 | j_mayer | #endif
|
5942 | 76a66253 | j_mayer | } |
5943 | 76a66253 | j_mayer | |
5944 | 76a66253 | j_mayer | /* mtdcr */
|
5945 | 99e300ef | Blue Swirl | static void gen_mtdcr(DisasContext *ctx) |
5946 | 76a66253 | j_mayer | { |
5947 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5948 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5949 | 76a66253 | j_mayer | #else
|
5950 | 06dca6a7 | aurel32 | TCGv dcrn; |
5951 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5952 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5953 | 76a66253 | j_mayer | return;
|
5954 | 76a66253 | j_mayer | } |
5955 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5956 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5957 | 06dca6a7 | aurel32 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
5958 | d0f1562d | Blue Swirl | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
5959 | 06dca6a7 | aurel32 | tcg_temp_free(dcrn); |
5960 | a42bd6cc | j_mayer | #endif
|
5961 | a42bd6cc | j_mayer | } |
5962 | a42bd6cc | j_mayer | |
5963 | a42bd6cc | j_mayer | /* mfdcrx */
|
5964 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5965 | 99e300ef | Blue Swirl | static void gen_mfdcrx(DisasContext *ctx) |
5966 | a42bd6cc | j_mayer | { |
5967 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5968 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5969 | a42bd6cc | j_mayer | #else
|
5970 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5971 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5972 | a42bd6cc | j_mayer | return;
|
5973 | a42bd6cc | j_mayer | } |
5974 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5975 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5976 | d0f1562d | Blue Swirl | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5977 | d0f1562d | Blue Swirl | cpu_gpr[rA(ctx->opcode)]); |
5978 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5979 | a42bd6cc | j_mayer | #endif
|
5980 | a42bd6cc | j_mayer | } |
5981 | a42bd6cc | j_mayer | |
5982 | a42bd6cc | j_mayer | /* mtdcrx */
|
5983 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
5984 | 99e300ef | Blue Swirl | static void gen_mtdcrx(DisasContext *ctx) |
5985 | a42bd6cc | j_mayer | { |
5986 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
5987 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5988 | a42bd6cc | j_mayer | #else
|
5989 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
5990 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
5991 | a42bd6cc | j_mayer | return;
|
5992 | a42bd6cc | j_mayer | } |
5993 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
5994 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
5995 | d0f1562d | Blue Swirl | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5996 | d0f1562d | Blue Swirl | cpu_gpr[rS(ctx->opcode)]); |
5997 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
5998 | 76a66253 | j_mayer | #endif
|
5999 | 76a66253 | j_mayer | } |
6000 | 76a66253 | j_mayer | |
6001 | a750fc0b | j_mayer | /* mfdcrux (PPC 460) : user-mode access to DCR */
|
6002 | 99e300ef | Blue Swirl | static void gen_mfdcrux(DisasContext *ctx) |
6003 | a750fc0b | j_mayer | { |
6004 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
6005 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
6006 | d0f1562d | Blue Swirl | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6007 | d0f1562d | Blue Swirl | cpu_gpr[rA(ctx->opcode)]); |
6008 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
6009 | a750fc0b | j_mayer | } |
6010 | a750fc0b | j_mayer | |
6011 | a750fc0b | j_mayer | /* mtdcrux (PPC 460) : user-mode access to DCR */
|
6012 | 99e300ef | Blue Swirl | static void gen_mtdcrux(DisasContext *ctx) |
6013 | a750fc0b | j_mayer | { |
6014 | 06dca6a7 | aurel32 | /* NIP cannot be restored if the memory exception comes from an helper */
|
6015 | 06dca6a7 | aurel32 | gen_update_nip(ctx, ctx->nip - 4);
|
6016 | 975e5463 | Stefan Weil | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6017 | d0f1562d | Blue Swirl | cpu_gpr[rS(ctx->opcode)]); |
6018 | a750fc0b | j_mayer | /* Note: Rc update flag set leads to undefined state of Rc0 */
|
6019 | a750fc0b | j_mayer | } |
6020 | a750fc0b | j_mayer | |
6021 | 76a66253 | j_mayer | /* dccci */
|
6022 | 99e300ef | Blue Swirl | static void gen_dccci(DisasContext *ctx) |
6023 | 76a66253 | j_mayer | { |
6024 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6025 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6026 | 76a66253 | j_mayer | #else
|
6027 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6028 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6029 | 76a66253 | j_mayer | return;
|
6030 | 76a66253 | j_mayer | } |
6031 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6032 | 76a66253 | j_mayer | #endif
|
6033 | 76a66253 | j_mayer | } |
6034 | 76a66253 | j_mayer | |
6035 | 76a66253 | j_mayer | /* dcread */
|
6036 | 99e300ef | Blue Swirl | static void gen_dcread(DisasContext *ctx) |
6037 | 76a66253 | j_mayer | { |
6038 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6039 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6040 | 76a66253 | j_mayer | #else
|
6041 | b61f2753 | aurel32 | TCGv EA, val; |
6042 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6043 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6044 | 76a66253 | j_mayer | return;
|
6045 | 76a66253 | j_mayer | } |
6046 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_CACHE); |
6047 | a7812ae4 | pbrook | EA = tcg_temp_new(); |
6048 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); |
6049 | a7812ae4 | pbrook | val = tcg_temp_new(); |
6050 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, val, EA); |
6051 | b61f2753 | aurel32 | tcg_temp_free(val); |
6052 | b61f2753 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
6053 | b61f2753 | aurel32 | tcg_temp_free(EA); |
6054 | 76a66253 | j_mayer | #endif
|
6055 | 76a66253 | j_mayer | } |
6056 | 76a66253 | j_mayer | |
6057 | 76a66253 | j_mayer | /* icbt */
|
6058 | e8eaa2c0 | Blue Swirl | static void gen_icbt_40x(DisasContext *ctx) |
6059 | 76a66253 | j_mayer | { |
6060 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6061 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
6062 | 76a66253 | j_mayer | * but does not generate any exception
|
6063 | 76a66253 | j_mayer | */
|
6064 | 76a66253 | j_mayer | } |
6065 | 76a66253 | j_mayer | |
6066 | 76a66253 | j_mayer | /* iccci */
|
6067 | 99e300ef | Blue Swirl | static void gen_iccci(DisasContext *ctx) |
6068 | 76a66253 | j_mayer | { |
6069 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6070 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6071 | 76a66253 | j_mayer | #else
|
6072 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6073 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6074 | 76a66253 | j_mayer | return;
|
6075 | 76a66253 | j_mayer | } |
6076 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6077 | 76a66253 | j_mayer | #endif
|
6078 | 76a66253 | j_mayer | } |
6079 | 76a66253 | j_mayer | |
6080 | 76a66253 | j_mayer | /* icread */
|
6081 | 99e300ef | Blue Swirl | static void gen_icread(DisasContext *ctx) |
6082 | 76a66253 | j_mayer | { |
6083 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6084 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6085 | 76a66253 | j_mayer | #else
|
6086 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6087 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6088 | 76a66253 | j_mayer | return;
|
6089 | 76a66253 | j_mayer | } |
6090 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6091 | 76a66253 | j_mayer | #endif
|
6092 | 76a66253 | j_mayer | } |
6093 | 76a66253 | j_mayer | |
6094 | 76db3ba4 | aurel32 | /* rfci (mem_idx only) */
|
6095 | e8eaa2c0 | Blue Swirl | static void gen_rfci_40x(DisasContext *ctx) |
6096 | a42bd6cc | j_mayer | { |
6097 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6098 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6099 | a42bd6cc | j_mayer | #else
|
6100 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6101 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6102 | a42bd6cc | j_mayer | return;
|
6103 | a42bd6cc | j_mayer | } |
6104 | a42bd6cc | j_mayer | /* Restore CPU state */
|
6105 | e5f17ac6 | Blue Swirl | gen_helper_40x_rfci(cpu_env); |
6106 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
6107 | a42bd6cc | j_mayer | #endif
|
6108 | a42bd6cc | j_mayer | } |
6109 | a42bd6cc | j_mayer | |
6110 | 99e300ef | Blue Swirl | static void gen_rfci(DisasContext *ctx) |
6111 | a42bd6cc | j_mayer | { |
6112 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6113 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6114 | a42bd6cc | j_mayer | #else
|
6115 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6116 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6117 | a42bd6cc | j_mayer | return;
|
6118 | a42bd6cc | j_mayer | } |
6119 | a42bd6cc | j_mayer | /* Restore CPU state */
|
6120 | e5f17ac6 | Blue Swirl | gen_helper_rfci(cpu_env); |
6121 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
6122 | a42bd6cc | j_mayer | #endif
|
6123 | a42bd6cc | j_mayer | } |
6124 | a42bd6cc | j_mayer | |
6125 | a42bd6cc | j_mayer | /* BookE specific */
|
6126 | 99e300ef | Blue Swirl | |
6127 | 54623277 | Blue Swirl | /* XXX: not implemented on 440 ? */
|
6128 | 99e300ef | Blue Swirl | static void gen_rfdi(DisasContext *ctx) |
6129 | 76a66253 | j_mayer | { |
6130 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6131 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6132 | 76a66253 | j_mayer | #else
|
6133 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6134 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6135 | 76a66253 | j_mayer | return;
|
6136 | 76a66253 | j_mayer | } |
6137 | 76a66253 | j_mayer | /* Restore CPU state */
|
6138 | e5f17ac6 | Blue Swirl | gen_helper_rfdi(cpu_env); |
6139 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
6140 | 76a66253 | j_mayer | #endif
|
6141 | 76a66253 | j_mayer | } |
6142 | 76a66253 | j_mayer | |
6143 | 2662a059 | j_mayer | /* XXX: not implemented on 440 ? */
|
6144 | 99e300ef | Blue Swirl | static void gen_rfmci(DisasContext *ctx) |
6145 | a42bd6cc | j_mayer | { |
6146 | a42bd6cc | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6147 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6148 | a42bd6cc | j_mayer | #else
|
6149 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6150 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6151 | a42bd6cc | j_mayer | return;
|
6152 | a42bd6cc | j_mayer | } |
6153 | a42bd6cc | j_mayer | /* Restore CPU state */
|
6154 | e5f17ac6 | Blue Swirl | gen_helper_rfmci(cpu_env); |
6155 | e06fcd75 | aurel32 | gen_sync_exception(ctx); |
6156 | a42bd6cc | j_mayer | #endif
|
6157 | a42bd6cc | j_mayer | } |
6158 | 5eb7995e | j_mayer | |
6159 | d9bce9d9 | j_mayer | /* TLB management - PowerPC 405 implementation */
|
6160 | e8eaa2c0 | Blue Swirl | |
6161 | 54623277 | Blue Swirl | /* tlbre */
|
6162 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_40x(DisasContext *ctx) |
6163 | 76a66253 | j_mayer | { |
6164 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6165 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6166 | 76a66253 | j_mayer | #else
|
6167 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6168 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6169 | 76a66253 | j_mayer | return;
|
6170 | 76a66253 | j_mayer | } |
6171 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
6172 | 76a66253 | j_mayer | case 0: |
6173 | c6c7cf05 | Blue Swirl | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6174 | c6c7cf05 | Blue Swirl | cpu_gpr[rA(ctx->opcode)]); |
6175 | 76a66253 | j_mayer | break;
|
6176 | 76a66253 | j_mayer | case 1: |
6177 | c6c7cf05 | Blue Swirl | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6178 | c6c7cf05 | Blue Swirl | cpu_gpr[rA(ctx->opcode)]); |
6179 | 76a66253 | j_mayer | break;
|
6180 | 76a66253 | j_mayer | default:
|
6181 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6182 | 76a66253 | j_mayer | break;
|
6183 | 9a64fbe4 | bellard | } |
6184 | 76a66253 | j_mayer | #endif
|
6185 | 76a66253 | j_mayer | } |
6186 | 76a66253 | j_mayer | |
6187 | d9bce9d9 | j_mayer | /* tlbsx - tlbsx. */
|
6188 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_40x(DisasContext *ctx) |
6189 | 76a66253 | j_mayer | { |
6190 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6191 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6192 | 76a66253 | j_mayer | #else
|
6193 | 74d37793 | aurel32 | TCGv t0; |
6194 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6195 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6196 | 76a66253 | j_mayer | return;
|
6197 | 76a66253 | j_mayer | } |
6198 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
6199 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
6200 | c6c7cf05 | Blue Swirl | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
6201 | 74d37793 | aurel32 | tcg_temp_free(t0); |
6202 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
6203 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
6204 | da91a00f | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
|
6205 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
6206 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
6207 | 74d37793 | aurel32 | gen_set_label(l1); |
6208 | 74d37793 | aurel32 | } |
6209 | 76a66253 | j_mayer | #endif
|
6210 | 79aceca5 | bellard | } |
6211 | 79aceca5 | bellard | |
6212 | 76a66253 | j_mayer | /* tlbwe */
|
6213 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_40x(DisasContext *ctx) |
6214 | 79aceca5 | bellard | { |
6215 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6216 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6217 | 76a66253 | j_mayer | #else
|
6218 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6219 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6220 | 76a66253 | j_mayer | return;
|
6221 | 76a66253 | j_mayer | } |
6222 | 76a66253 | j_mayer | switch (rB(ctx->opcode)) {
|
6223 | 76a66253 | j_mayer | case 0: |
6224 | c6c7cf05 | Blue Swirl | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6225 | c6c7cf05 | Blue Swirl | cpu_gpr[rS(ctx->opcode)]); |
6226 | 76a66253 | j_mayer | break;
|
6227 | 76a66253 | j_mayer | case 1: |
6228 | c6c7cf05 | Blue Swirl | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6229 | c6c7cf05 | Blue Swirl | cpu_gpr[rS(ctx->opcode)]); |
6230 | 76a66253 | j_mayer | break;
|
6231 | 76a66253 | j_mayer | default:
|
6232 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6233 | 76a66253 | j_mayer | break;
|
6234 | 9a64fbe4 | bellard | } |
6235 | 76a66253 | j_mayer | #endif
|
6236 | 76a66253 | j_mayer | } |
6237 | 76a66253 | j_mayer | |
6238 | a4bb6c3e | j_mayer | /* TLB management - PowerPC 440 implementation */
|
6239 | e8eaa2c0 | Blue Swirl | |
6240 | 54623277 | Blue Swirl | /* tlbre */
|
6241 | e8eaa2c0 | Blue Swirl | static void gen_tlbre_440(DisasContext *ctx) |
6242 | 5eb7995e | j_mayer | { |
6243 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6244 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6245 | 5eb7995e | j_mayer | #else
|
6246 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6247 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6248 | 5eb7995e | j_mayer | return;
|
6249 | 5eb7995e | j_mayer | } |
6250 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
6251 | 5eb7995e | j_mayer | case 0: |
6252 | 5eb7995e | j_mayer | case 1: |
6253 | 5eb7995e | j_mayer | case 2: |
6254 | 74d37793 | aurel32 | { |
6255 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
6256 | c6c7cf05 | Blue Swirl | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6257 | c6c7cf05 | Blue Swirl | t0, cpu_gpr[rA(ctx->opcode)]); |
6258 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
6259 | 74d37793 | aurel32 | } |
6260 | 5eb7995e | j_mayer | break;
|
6261 | 5eb7995e | j_mayer | default:
|
6262 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6263 | 5eb7995e | j_mayer | break;
|
6264 | 5eb7995e | j_mayer | } |
6265 | 5eb7995e | j_mayer | #endif
|
6266 | 5eb7995e | j_mayer | } |
6267 | 5eb7995e | j_mayer | |
6268 | 5eb7995e | j_mayer | /* tlbsx - tlbsx. */
|
6269 | e8eaa2c0 | Blue Swirl | static void gen_tlbsx_440(DisasContext *ctx) |
6270 | 5eb7995e | j_mayer | { |
6271 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6272 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6273 | 5eb7995e | j_mayer | #else
|
6274 | 74d37793 | aurel32 | TCGv t0; |
6275 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6276 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6277 | 5eb7995e | j_mayer | return;
|
6278 | 5eb7995e | j_mayer | } |
6279 | 74d37793 | aurel32 | t0 = tcg_temp_new(); |
6280 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); |
6281 | c6c7cf05 | Blue Swirl | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
6282 | 74d37793 | aurel32 | tcg_temp_free(t0); |
6283 | 74d37793 | aurel32 | if (Rc(ctx->opcode)) {
|
6284 | 74d37793 | aurel32 | int l1 = gen_new_label();
|
6285 | da91a00f | Richard Henderson | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
|
6286 | 74d37793 | aurel32 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
|
6287 | 74d37793 | aurel32 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
6288 | 74d37793 | aurel32 | gen_set_label(l1); |
6289 | 74d37793 | aurel32 | } |
6290 | 5eb7995e | j_mayer | #endif
|
6291 | 5eb7995e | j_mayer | } |
6292 | 5eb7995e | j_mayer | |
6293 | 5eb7995e | j_mayer | /* tlbwe */
|
6294 | e8eaa2c0 | Blue Swirl | static void gen_tlbwe_440(DisasContext *ctx) |
6295 | 5eb7995e | j_mayer | { |
6296 | 5eb7995e | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6297 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6298 | 5eb7995e | j_mayer | #else
|
6299 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6300 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6301 | 5eb7995e | j_mayer | return;
|
6302 | 5eb7995e | j_mayer | } |
6303 | 5eb7995e | j_mayer | switch (rB(ctx->opcode)) {
|
6304 | 5eb7995e | j_mayer | case 0: |
6305 | 5eb7995e | j_mayer | case 1: |
6306 | 5eb7995e | j_mayer | case 2: |
6307 | 74d37793 | aurel32 | { |
6308 | 74d37793 | aurel32 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
6309 | c6c7cf05 | Blue Swirl | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6310 | c6c7cf05 | Blue Swirl | cpu_gpr[rS(ctx->opcode)]); |
6311 | 74d37793 | aurel32 | tcg_temp_free_i32(t0); |
6312 | 74d37793 | aurel32 | } |
6313 | 5eb7995e | j_mayer | break;
|
6314 | 5eb7995e | j_mayer | default:
|
6315 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6316 | 5eb7995e | j_mayer | break;
|
6317 | 5eb7995e | j_mayer | } |
6318 | 5eb7995e | j_mayer | #endif
|
6319 | 5eb7995e | j_mayer | } |
6320 | 5eb7995e | j_mayer | |
6321 | 01662f3e | Alexander Graf | /* TLB management - PowerPC BookE 2.06 implementation */
|
6322 | 01662f3e | Alexander Graf | |
6323 | 01662f3e | Alexander Graf | /* tlbre */
|
6324 | 01662f3e | Alexander Graf | static void gen_tlbre_booke206(DisasContext *ctx) |
6325 | 01662f3e | Alexander Graf | { |
6326 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6327 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6328 | 01662f3e | Alexander Graf | #else
|
6329 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6330 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6331 | 01662f3e | Alexander Graf | return;
|
6332 | 01662f3e | Alexander Graf | } |
6333 | 01662f3e | Alexander Graf | |
6334 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbre(cpu_env); |
6335 | 01662f3e | Alexander Graf | #endif
|
6336 | 01662f3e | Alexander Graf | } |
6337 | 01662f3e | Alexander Graf | |
6338 | 01662f3e | Alexander Graf | /* tlbsx - tlbsx. */
|
6339 | 01662f3e | Alexander Graf | static void gen_tlbsx_booke206(DisasContext *ctx) |
6340 | 01662f3e | Alexander Graf | { |
6341 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6342 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6343 | 01662f3e | Alexander Graf | #else
|
6344 | 01662f3e | Alexander Graf | TCGv t0; |
6345 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6346 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6347 | 01662f3e | Alexander Graf | return;
|
6348 | 01662f3e | Alexander Graf | } |
6349 | 01662f3e | Alexander Graf | |
6350 | 01662f3e | Alexander Graf | if (rA(ctx->opcode)) {
|
6351 | 01662f3e | Alexander Graf | t0 = tcg_temp_new(); |
6352 | 01662f3e | Alexander Graf | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); |
6353 | 01662f3e | Alexander Graf | } else {
|
6354 | 01662f3e | Alexander Graf | t0 = tcg_const_tl(0);
|
6355 | 01662f3e | Alexander Graf | } |
6356 | 01662f3e | Alexander Graf | |
6357 | 01662f3e | Alexander Graf | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); |
6358 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbsx(cpu_env, t0); |
6359 | 01662f3e | Alexander Graf | #endif
|
6360 | 01662f3e | Alexander Graf | } |
6361 | 01662f3e | Alexander Graf | |
6362 | 01662f3e | Alexander Graf | /* tlbwe */
|
6363 | 01662f3e | Alexander Graf | static void gen_tlbwe_booke206(DisasContext *ctx) |
6364 | 01662f3e | Alexander Graf | { |
6365 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6366 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6367 | 01662f3e | Alexander Graf | #else
|
6368 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6369 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6370 | 01662f3e | Alexander Graf | return;
|
6371 | 01662f3e | Alexander Graf | } |
6372 | 3f162d11 | Alexander Graf | gen_update_nip(ctx, ctx->nip - 4);
|
6373 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbwe(cpu_env); |
6374 | 01662f3e | Alexander Graf | #endif
|
6375 | 01662f3e | Alexander Graf | } |
6376 | 01662f3e | Alexander Graf | |
6377 | 01662f3e | Alexander Graf | static void gen_tlbivax_booke206(DisasContext *ctx) |
6378 | 01662f3e | Alexander Graf | { |
6379 | 01662f3e | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6380 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6381 | 01662f3e | Alexander Graf | #else
|
6382 | 01662f3e | Alexander Graf | TCGv t0; |
6383 | 01662f3e | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6384 | 01662f3e | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6385 | 01662f3e | Alexander Graf | return;
|
6386 | 01662f3e | Alexander Graf | } |
6387 | 01662f3e | Alexander Graf | |
6388 | 01662f3e | Alexander Graf | t0 = tcg_temp_new(); |
6389 | 01662f3e | Alexander Graf | gen_addr_reg_index(ctx, t0); |
6390 | 01662f3e | Alexander Graf | |
6391 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbivax(cpu_env, t0); |
6392 | 01662f3e | Alexander Graf | #endif
|
6393 | 01662f3e | Alexander Graf | } |
6394 | 01662f3e | Alexander Graf | |
6395 | 6d3db821 | Alexander Graf | static void gen_tlbilx_booke206(DisasContext *ctx) |
6396 | 6d3db821 | Alexander Graf | { |
6397 | 6d3db821 | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6398 | 6d3db821 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6399 | 6d3db821 | Alexander Graf | #else
|
6400 | 6d3db821 | Alexander Graf | TCGv t0; |
6401 | 6d3db821 | Alexander Graf | if (unlikely(!ctx->mem_idx)) {
|
6402 | 6d3db821 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6403 | 6d3db821 | Alexander Graf | return;
|
6404 | 6d3db821 | Alexander Graf | } |
6405 | 6d3db821 | Alexander Graf | |
6406 | 6d3db821 | Alexander Graf | t0 = tcg_temp_new(); |
6407 | 6d3db821 | Alexander Graf | gen_addr_reg_index(ctx, t0); |
6408 | 6d3db821 | Alexander Graf | |
6409 | 6d3db821 | Alexander Graf | switch((ctx->opcode >> 21) & 0x3) { |
6410 | 6d3db821 | Alexander Graf | case 0: |
6411 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6412 | 6d3db821 | Alexander Graf | break;
|
6413 | 6d3db821 | Alexander Graf | case 1: |
6414 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6415 | 6d3db821 | Alexander Graf | break;
|
6416 | 6d3db821 | Alexander Graf | case 3: |
6417 | c6c7cf05 | Blue Swirl | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6418 | 6d3db821 | Alexander Graf | break;
|
6419 | 6d3db821 | Alexander Graf | default:
|
6420 | 6d3db821 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6421 | 6d3db821 | Alexander Graf | break;
|
6422 | 6d3db821 | Alexander Graf | } |
6423 | 6d3db821 | Alexander Graf | |
6424 | 6d3db821 | Alexander Graf | tcg_temp_free(t0); |
6425 | 6d3db821 | Alexander Graf | #endif
|
6426 | 6d3db821 | Alexander Graf | } |
6427 | 6d3db821 | Alexander Graf | |
6428 | 01662f3e | Alexander Graf | |
6429 | 76a66253 | j_mayer | /* wrtee */
|
6430 | 99e300ef | Blue Swirl | static void gen_wrtee(DisasContext *ctx) |
6431 | 76a66253 | j_mayer | { |
6432 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6433 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6434 | 76a66253 | j_mayer | #else
|
6435 | 6527f6ea | aurel32 | TCGv t0; |
6436 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6437 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6438 | 76a66253 | j_mayer | return;
|
6439 | 76a66253 | j_mayer | } |
6440 | 6527f6ea | aurel32 | t0 = tcg_temp_new(); |
6441 | 6527f6ea | aurel32 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
|
6442 | 6527f6ea | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
6443 | 6527f6ea | aurel32 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
6444 | 6527f6ea | aurel32 | tcg_temp_free(t0); |
6445 | dee96f6c | j_mayer | /* Stop translation to have a chance to raise an exception
|
6446 | dee96f6c | j_mayer | * if we just set msr_ee to 1
|
6447 | dee96f6c | j_mayer | */
|
6448 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
6449 | 76a66253 | j_mayer | #endif
|
6450 | 76a66253 | j_mayer | } |
6451 | 76a66253 | j_mayer | |
6452 | 76a66253 | j_mayer | /* wrteei */
|
6453 | 99e300ef | Blue Swirl | static void gen_wrteei(DisasContext *ctx) |
6454 | 76a66253 | j_mayer | { |
6455 | 76a66253 | j_mayer | #if defined(CONFIG_USER_ONLY)
|
6456 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6457 | 76a66253 | j_mayer | #else
|
6458 | 76db3ba4 | aurel32 | if (unlikely(!ctx->mem_idx)) {
|
6459 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6460 | 76a66253 | j_mayer | return;
|
6461 | 76a66253 | j_mayer | } |
6462 | fbe73008 | Baojun Wang | if (ctx->opcode & 0x00008000) { |
6463 | 6527f6ea | aurel32 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
|
6464 | 6527f6ea | aurel32 | /* Stop translation to have a chance to raise an exception */
|
6465 | e06fcd75 | aurel32 | gen_stop_exception(ctx); |
6466 | 6527f6ea | aurel32 | } else {
|
6467 | 1b6e5f99 | aurel32 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
|
6468 | 6527f6ea | aurel32 | } |
6469 | 76a66253 | j_mayer | #endif
|
6470 | 76a66253 | j_mayer | } |
6471 | 76a66253 | j_mayer | |
6472 | 08e46e54 | j_mayer | /* PowerPC 440 specific instructions */
|
6473 | 99e300ef | Blue Swirl | |
6474 | 54623277 | Blue Swirl | /* dlmzb */
|
6475 | 99e300ef | Blue Swirl | static void gen_dlmzb(DisasContext *ctx) |
6476 | 76a66253 | j_mayer | { |
6477 | ef0d51af | aurel32 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
6478 | d15f74fb | Blue Swirl | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6479 | d15f74fb | Blue Swirl | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
6480 | ef0d51af | aurel32 | tcg_temp_free_i32(t0); |
6481 | 76a66253 | j_mayer | } |
6482 | 76a66253 | j_mayer | |
6483 | 76a66253 | j_mayer | /* mbar replaces eieio on 440 */
|
6484 | 99e300ef | Blue Swirl | static void gen_mbar(DisasContext *ctx) |
6485 | 76a66253 | j_mayer | { |
6486 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6487 | 76a66253 | j_mayer | } |
6488 | 76a66253 | j_mayer | |
6489 | 76a66253 | j_mayer | /* msync replaces sync on 440 */
|
6490 | dcb2b9e1 | Alexander Graf | static void gen_msync_4xx(DisasContext *ctx) |
6491 | 76a66253 | j_mayer | { |
6492 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6493 | 76a66253 | j_mayer | } |
6494 | 76a66253 | j_mayer | |
6495 | 76a66253 | j_mayer | /* icbt */
|
6496 | e8eaa2c0 | Blue Swirl | static void gen_icbt_440(DisasContext *ctx) |
6497 | 76a66253 | j_mayer | { |
6498 | 76a66253 | j_mayer | /* interpreted as no-op */
|
6499 | 76a66253 | j_mayer | /* XXX: specification say this is treated as a load by the MMU
|
6500 | 76a66253 | j_mayer | * but does not generate any exception
|
6501 | 76a66253 | j_mayer | */
|
6502 | 79aceca5 | bellard | } |
6503 | 79aceca5 | bellard | |
6504 | 9e0b5cb1 | Alexander Graf | /* Embedded.Processor Control */
|
6505 | 9e0b5cb1 | Alexander Graf | |
6506 | 9e0b5cb1 | Alexander Graf | static void gen_msgclr(DisasContext *ctx) |
6507 | 9e0b5cb1 | Alexander Graf | { |
6508 | 9e0b5cb1 | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6509 | 9e0b5cb1 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6510 | 9e0b5cb1 | Alexander Graf | #else
|
6511 | 9e0b5cb1 | Alexander Graf | if (unlikely(ctx->mem_idx == 0)) { |
6512 | 9e0b5cb1 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6513 | 9e0b5cb1 | Alexander Graf | return;
|
6514 | 9e0b5cb1 | Alexander Graf | } |
6515 | 9e0b5cb1 | Alexander Graf | |
6516 | e5f17ac6 | Blue Swirl | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
6517 | 9e0b5cb1 | Alexander Graf | #endif
|
6518 | 9e0b5cb1 | Alexander Graf | } |
6519 | 9e0b5cb1 | Alexander Graf | |
6520 | d5d11a39 | Alexander Graf | static void gen_msgsnd(DisasContext *ctx) |
6521 | d5d11a39 | Alexander Graf | { |
6522 | d5d11a39 | Alexander Graf | #if defined(CONFIG_USER_ONLY)
|
6523 | d5d11a39 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6524 | d5d11a39 | Alexander Graf | #else
|
6525 | d5d11a39 | Alexander Graf | if (unlikely(ctx->mem_idx == 0)) { |
6526 | d5d11a39 | Alexander Graf | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
6527 | d5d11a39 | Alexander Graf | return;
|
6528 | d5d11a39 | Alexander Graf | } |
6529 | d5d11a39 | Alexander Graf | |
6530 | d5d11a39 | Alexander Graf | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
6531 | d5d11a39 | Alexander Graf | #endif
|
6532 | d5d11a39 | Alexander Graf | } |
6533 | d5d11a39 | Alexander Graf | |
6534 | a9d9eb8f | j_mayer | /*** Altivec vector extension ***/
|
6535 | a9d9eb8f | j_mayer | /* Altivec registers moves */
|
6536 | a9d9eb8f | j_mayer | |
6537 | 636aa200 | Blue Swirl | static inline TCGv_ptr gen_avr_ptr(int reg) |
6538 | 564e571a | aurel32 | { |
6539 | e4704b3b | aurel32 | TCGv_ptr r = tcg_temp_new_ptr(); |
6540 | 564e571a | aurel32 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6541 | 564e571a | aurel32 | return r;
|
6542 | 564e571a | aurel32 | } |
6543 | 564e571a | aurel32 | |
6544 | a9d9eb8f | j_mayer | #define GEN_VR_LDX(name, opc2, opc3) \
|
6545 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6546 | a9d9eb8f | j_mayer | { \ |
6547 | fe1e5c53 | aurel32 | TCGv EA; \ |
6548 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6549 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6550 | a9d9eb8f | j_mayer | return; \
|
6551 | a9d9eb8f | j_mayer | } \ |
6552 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6553 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6554 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6555 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6556 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6557 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6558 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6559 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6560 | fe1e5c53 | aurel32 | } else { \
|
6561 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6562 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6563 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6564 | fe1e5c53 | aurel32 | } \ |
6565 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6566 | a9d9eb8f | j_mayer | } |
6567 | a9d9eb8f | j_mayer | |
6568 | a9d9eb8f | j_mayer | #define GEN_VR_STX(name, opc2, opc3) \
|
6569 | 99e300ef | Blue Swirl | static void gen_st##name(DisasContext *ctx) \ |
6570 | a9d9eb8f | j_mayer | { \ |
6571 | fe1e5c53 | aurel32 | TCGv EA; \ |
6572 | a9d9eb8f | j_mayer | if (unlikely(!ctx->altivec_enabled)) { \
|
6573 | e06fcd75 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6574 | a9d9eb8f | j_mayer | return; \
|
6575 | a9d9eb8f | j_mayer | } \ |
6576 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6577 | fe1e5c53 | aurel32 | EA = tcg_temp_new(); \ |
6578 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6579 | fe1e5c53 | aurel32 | tcg_gen_andi_tl(EA, EA, ~0xf); \
|
6580 | 76db3ba4 | aurel32 | if (ctx->le_mode) { \
|
6581 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6582 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6583 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6584 | fe1e5c53 | aurel32 | } else { \
|
6585 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
6586 | fe1e5c53 | aurel32 | tcg_gen_addi_tl(EA, EA, 8); \
|
6587 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
6588 | fe1e5c53 | aurel32 | } \ |
6589 | fe1e5c53 | aurel32 | tcg_temp_free(EA); \ |
6590 | a9d9eb8f | j_mayer | } |
6591 | a9d9eb8f | j_mayer | |
6592 | cbfb6ae9 | aurel32 | #define GEN_VR_LVE(name, opc2, opc3) \
|
6593 | 99e300ef | Blue Swirl | static void gen_lve##name(DisasContext *ctx) \ |
6594 | cbfb6ae9 | aurel32 | { \ |
6595 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6596 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6597 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6598 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6599 | cbfb6ae9 | aurel32 | return; \
|
6600 | cbfb6ae9 | aurel32 | } \ |
6601 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6602 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6603 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6604 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6605 | 2f5a189c | Blue Swirl | gen_helper_lve##name(cpu_env, rs, EA); \ |
6606 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6607 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6608 | cbfb6ae9 | aurel32 | } |
6609 | cbfb6ae9 | aurel32 | |
6610 | cbfb6ae9 | aurel32 | #define GEN_VR_STVE(name, opc2, opc3) \
|
6611 | 99e300ef | Blue Swirl | static void gen_stve##name(DisasContext *ctx) \ |
6612 | cbfb6ae9 | aurel32 | { \ |
6613 | cbfb6ae9 | aurel32 | TCGv EA; \ |
6614 | cbfb6ae9 | aurel32 | TCGv_ptr rs; \ |
6615 | cbfb6ae9 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6616 | cbfb6ae9 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6617 | cbfb6ae9 | aurel32 | return; \
|
6618 | cbfb6ae9 | aurel32 | } \ |
6619 | cbfb6ae9 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
6620 | cbfb6ae9 | aurel32 | EA = tcg_temp_new(); \ |
6621 | cbfb6ae9 | aurel32 | gen_addr_reg_index(ctx, EA); \ |
6622 | cbfb6ae9 | aurel32 | rs = gen_avr_ptr(rS(ctx->opcode)); \ |
6623 | 2f5a189c | Blue Swirl | gen_helper_stve##name(cpu_env, rs, EA); \ |
6624 | cbfb6ae9 | aurel32 | tcg_temp_free(EA); \ |
6625 | cbfb6ae9 | aurel32 | tcg_temp_free_ptr(rs); \ |
6626 | cbfb6ae9 | aurel32 | } |
6627 | cbfb6ae9 | aurel32 | |
6628 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvx, 0x07, 0x03); |
6629 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
|
6630 | fe1e5c53 | aurel32 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
6631 | a9d9eb8f | j_mayer | |
6632 | cbfb6ae9 | aurel32 | GEN_VR_LVE(bx, 0x07, 0x00); |
6633 | cbfb6ae9 | aurel32 | GEN_VR_LVE(hx, 0x07, 0x01); |
6634 | cbfb6ae9 | aurel32 | GEN_VR_LVE(wx, 0x07, 0x02); |
6635 | cbfb6ae9 | aurel32 | |
6636 | fe1e5c53 | aurel32 | GEN_VR_STX(svx, 0x07, 0x07); |
6637 | a9d9eb8f | j_mayer | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
|
6638 | fe1e5c53 | aurel32 | GEN_VR_STX(svxl, 0x07, 0x0F); |
6639 | a9d9eb8f | j_mayer | |
6640 | cbfb6ae9 | aurel32 | GEN_VR_STVE(bx, 0x07, 0x04); |
6641 | cbfb6ae9 | aurel32 | GEN_VR_STVE(hx, 0x07, 0x05); |
6642 | cbfb6ae9 | aurel32 | GEN_VR_STVE(wx, 0x07, 0x06); |
6643 | cbfb6ae9 | aurel32 | |
6644 | 99e300ef | Blue Swirl | static void gen_lvsl(DisasContext *ctx) |
6645 | bf8d8ded | aurel32 | { |
6646 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6647 | bf8d8ded | aurel32 | TCGv EA; |
6648 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6649 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6650 | bf8d8ded | aurel32 | return;
|
6651 | bf8d8ded | aurel32 | } |
6652 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6653 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6654 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6655 | bf8d8ded | aurel32 | gen_helper_lvsl(rd, EA); |
6656 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6657 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6658 | bf8d8ded | aurel32 | } |
6659 | bf8d8ded | aurel32 | |
6660 | 99e300ef | Blue Swirl | static void gen_lvsr(DisasContext *ctx) |
6661 | bf8d8ded | aurel32 | { |
6662 | bf8d8ded | aurel32 | TCGv_ptr rd; |
6663 | bf8d8ded | aurel32 | TCGv EA; |
6664 | bf8d8ded | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6665 | bf8d8ded | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6666 | bf8d8ded | aurel32 | return;
|
6667 | bf8d8ded | aurel32 | } |
6668 | bf8d8ded | aurel32 | EA = tcg_temp_new(); |
6669 | bf8d8ded | aurel32 | gen_addr_reg_index(ctx, EA); |
6670 | bf8d8ded | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
6671 | bf8d8ded | aurel32 | gen_helper_lvsr(rd, EA); |
6672 | bf8d8ded | aurel32 | tcg_temp_free(EA); |
6673 | bf8d8ded | aurel32 | tcg_temp_free_ptr(rd); |
6674 | bf8d8ded | aurel32 | } |
6675 | bf8d8ded | aurel32 | |
6676 | 99e300ef | Blue Swirl | static void gen_mfvscr(DisasContext *ctx) |
6677 | 785f451b | aurel32 | { |
6678 | 785f451b | aurel32 | TCGv_i32 t; |
6679 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6680 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6681 | 785f451b | aurel32 | return;
|
6682 | 785f451b | aurel32 | } |
6683 | 785f451b | aurel32 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
|
6684 | 785f451b | aurel32 | t = tcg_temp_new_i32(); |
6685 | 1328c2bf | Andreas Färber | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
6686 | 785f451b | aurel32 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
6687 | fce5ecb7 | aurel32 | tcg_temp_free_i32(t); |
6688 | 785f451b | aurel32 | } |
6689 | 785f451b | aurel32 | |
6690 | 99e300ef | Blue Swirl | static void gen_mtvscr(DisasContext *ctx) |
6691 | 785f451b | aurel32 | { |
6692 | 6e87b7c7 | aurel32 | TCGv_ptr p; |
6693 | 785f451b | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
6694 | 785f451b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
6695 | 785f451b | aurel32 | return;
|
6696 | 785f451b | aurel32 | } |
6697 | 6e87b7c7 | aurel32 | p = gen_avr_ptr(rD(ctx->opcode)); |
6698 | d15f74fb | Blue Swirl | gen_helper_mtvscr(cpu_env, p); |
6699 | 6e87b7c7 | aurel32 | tcg_temp_free_ptr(p); |
6700 | 785f451b | aurel32 | } |
6701 | 785f451b | aurel32 | |
6702 | 7a9b96cf | aurel32 | /* Logical operations */
|
6703 | 7a9b96cf | aurel32 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
6704 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6705 | 7a9b96cf | aurel32 | { \ |
6706 | 7a9b96cf | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6707 | 7a9b96cf | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6708 | 7a9b96cf | aurel32 | return; \
|
6709 | 7a9b96cf | aurel32 | } \ |
6710 | 7a9b96cf | aurel32 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ |
6711 | 7a9b96cf | aurel32 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ |
6712 | 7a9b96cf | aurel32 | } |
6713 | 7a9b96cf | aurel32 | |
6714 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); |
6715 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); |
6716 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); |
6717 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); |
6718 | 7a9b96cf | aurel32 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); |
6719 | 7a9b96cf | aurel32 | |
6720 | 8e27dd6f | aurel32 | #define GEN_VXFORM(name, opc2, opc3) \
|
6721 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6722 | 8e27dd6f | aurel32 | { \ |
6723 | 8e27dd6f | aurel32 | TCGv_ptr ra, rb, rd; \ |
6724 | 8e27dd6f | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6725 | 8e27dd6f | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6726 | 8e27dd6f | aurel32 | return; \
|
6727 | 8e27dd6f | aurel32 | } \ |
6728 | 8e27dd6f | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6729 | 8e27dd6f | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6730 | 8e27dd6f | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6731 | 8e27dd6f | aurel32 | gen_helper_##name (rd, ra, rb); \ |
6732 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(ra); \ |
6733 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rb); \ |
6734 | 8e27dd6f | aurel32 | tcg_temp_free_ptr(rd); \ |
6735 | 8e27dd6f | aurel32 | } |
6736 | 8e27dd6f | aurel32 | |
6737 | d15f74fb | Blue Swirl | #define GEN_VXFORM_ENV(name, opc2, opc3) \
|
6738 | d15f74fb | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6739 | d15f74fb | Blue Swirl | { \ |
6740 | d15f74fb | Blue Swirl | TCGv_ptr ra, rb, rd; \ |
6741 | d15f74fb | Blue Swirl | if (unlikely(!ctx->altivec_enabled)) { \
|
6742 | d15f74fb | Blue Swirl | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6743 | d15f74fb | Blue Swirl | return; \
|
6744 | d15f74fb | Blue Swirl | } \ |
6745 | d15f74fb | Blue Swirl | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6746 | d15f74fb | Blue Swirl | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6747 | d15f74fb | Blue Swirl | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6748 | 54cddd21 | Aurelien Jarno | gen_helper_##name(cpu_env, rd, ra, rb); \ |
6749 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(ra); \ |
6750 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(rb); \ |
6751 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(rd); \ |
6752 | d15f74fb | Blue Swirl | } |
6753 | d15f74fb | Blue Swirl | |
6754 | 7872c51c | aurel32 | GEN_VXFORM(vaddubm, 0, 0); |
6755 | 7872c51c | aurel32 | GEN_VXFORM(vadduhm, 0, 1); |
6756 | 7872c51c | aurel32 | GEN_VXFORM(vadduwm, 0, 2); |
6757 | 7872c51c | aurel32 | GEN_VXFORM(vsububm, 0, 16); |
6758 | 7872c51c | aurel32 | GEN_VXFORM(vsubuhm, 0, 17); |
6759 | 7872c51c | aurel32 | GEN_VXFORM(vsubuwm, 0, 18); |
6760 | e4039339 | aurel32 | GEN_VXFORM(vmaxub, 1, 0); |
6761 | e4039339 | aurel32 | GEN_VXFORM(vmaxuh, 1, 1); |
6762 | e4039339 | aurel32 | GEN_VXFORM(vmaxuw, 1, 2); |
6763 | e4039339 | aurel32 | GEN_VXFORM(vmaxsb, 1, 4); |
6764 | e4039339 | aurel32 | GEN_VXFORM(vmaxsh, 1, 5); |
6765 | e4039339 | aurel32 | GEN_VXFORM(vmaxsw, 1, 6); |
6766 | e4039339 | aurel32 | GEN_VXFORM(vminub, 1, 8); |
6767 | e4039339 | aurel32 | GEN_VXFORM(vminuh, 1, 9); |
6768 | e4039339 | aurel32 | GEN_VXFORM(vminuw, 1, 10); |
6769 | e4039339 | aurel32 | GEN_VXFORM(vminsb, 1, 12); |
6770 | e4039339 | aurel32 | GEN_VXFORM(vminsh, 1, 13); |
6771 | e4039339 | aurel32 | GEN_VXFORM(vminsw, 1, 14); |
6772 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgub, 1, 16); |
6773 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguh, 1, 17); |
6774 | fab3cbe9 | aurel32 | GEN_VXFORM(vavguw, 1, 18); |
6775 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsb, 1, 20); |
6776 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsh, 1, 21); |
6777 | fab3cbe9 | aurel32 | GEN_VXFORM(vavgsw, 1, 22); |
6778 | 3b430048 | aurel32 | GEN_VXFORM(vmrghb, 6, 0); |
6779 | 3b430048 | aurel32 | GEN_VXFORM(vmrghh, 6, 1); |
6780 | 3b430048 | aurel32 | GEN_VXFORM(vmrghw, 6, 2); |
6781 | 3b430048 | aurel32 | GEN_VXFORM(vmrglb, 6, 4); |
6782 | 3b430048 | aurel32 | GEN_VXFORM(vmrglh, 6, 5); |
6783 | 3b430048 | aurel32 | GEN_VXFORM(vmrglw, 6, 6); |
6784 | 2c277908 | aurel32 | GEN_VXFORM(vmuloub, 4, 0); |
6785 | 2c277908 | aurel32 | GEN_VXFORM(vmulouh, 4, 1); |
6786 | 2c277908 | aurel32 | GEN_VXFORM(vmulosb, 4, 4); |
6787 | 2c277908 | aurel32 | GEN_VXFORM(vmulosh, 4, 5); |
6788 | 2c277908 | aurel32 | GEN_VXFORM(vmuleub, 4, 8); |
6789 | 2c277908 | aurel32 | GEN_VXFORM(vmuleuh, 4, 9); |
6790 | 2c277908 | aurel32 | GEN_VXFORM(vmulesb, 4, 12); |
6791 | 2c277908 | aurel32 | GEN_VXFORM(vmulesh, 4, 13); |
6792 | d79f0809 | aurel32 | GEN_VXFORM(vslb, 2, 4); |
6793 | d79f0809 | aurel32 | GEN_VXFORM(vslh, 2, 5); |
6794 | d79f0809 | aurel32 | GEN_VXFORM(vslw, 2, 6); |
6795 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrb, 2, 8); |
6796 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrh, 2, 9); |
6797 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrw, 2, 10); |
6798 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrab, 2, 12); |
6799 | 07ef34c3 | aurel32 | GEN_VXFORM(vsrah, 2, 13); |
6800 | 07ef34c3 | aurel32 | GEN_VXFORM(vsraw, 2, 14); |
6801 | 7b239bec | aurel32 | GEN_VXFORM(vslo, 6, 16); |
6802 | 7b239bec | aurel32 | GEN_VXFORM(vsro, 6, 17); |
6803 | e343da72 | aurel32 | GEN_VXFORM(vaddcuw, 0, 6); |
6804 | e343da72 | aurel32 | GEN_VXFORM(vsubcuw, 0, 22); |
6805 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vaddubs, 0, 8); |
6806 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vadduhs, 0, 9); |
6807 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vadduws, 0, 10); |
6808 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vaddsbs, 0, 12); |
6809 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vaddshs, 0, 13); |
6810 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vaddsws, 0, 14); |
6811 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsububs, 0, 24); |
6812 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsubuhs, 0, 25); |
6813 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsubuws, 0, 26); |
6814 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsubsbs, 0, 28); |
6815 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsubshs, 0, 29); |
6816 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsubsws, 0, 30); |
6817 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlb, 2, 0); |
6818 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlh, 2, 1); |
6819 | 5e1d0985 | aurel32 | GEN_VXFORM(vrlw, 2, 2); |
6820 | d9430add | aurel32 | GEN_VXFORM(vsl, 2, 7); |
6821 | d9430add | aurel32 | GEN_VXFORM(vsr, 2, 11); |
6822 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
6823 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkuwum, 7, 1); |
6824 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkuhus, 7, 2); |
6825 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkuwus, 7, 3); |
6826 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkshus, 7, 4); |
6827 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkswus, 7, 5); |
6828 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkshss, 7, 6); |
6829 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vpkswss, 7, 7); |
6830 | 1dd9ffb9 | aurel32 | GEN_VXFORM(vpkpx, 7, 12); |
6831 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
6832 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsum4sbs, 4, 28); |
6833 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsum4shs, 4, 25); |
6834 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsum2sws, 4, 26); |
6835 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsumsws, 4, 30); |
6836 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vaddfp, 5, 0); |
6837 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vsubfp, 5, 1); |
6838 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vmaxfp, 5, 16); |
6839 | d15f74fb | Blue Swirl | GEN_VXFORM_ENV(vminfp, 5, 17); |
6840 | fab3cbe9 | aurel32 | |
6841 | 0cbcd906 | aurel32 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
6842 | e8eaa2c0 | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6843 | 0cbcd906 | aurel32 | { \ |
6844 | 0cbcd906 | aurel32 | TCGv_ptr ra, rb, rd; \ |
6845 | 0cbcd906 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6846 | 0cbcd906 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6847 | 0cbcd906 | aurel32 | return; \
|
6848 | 0cbcd906 | aurel32 | } \ |
6849 | 0cbcd906 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
6850 | 0cbcd906 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6851 | 0cbcd906 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6852 | d15f74fb | Blue Swirl | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
6853 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(ra); \ |
6854 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rb); \ |
6855 | 0cbcd906 | aurel32 | tcg_temp_free_ptr(rd); \ |
6856 | 0cbcd906 | aurel32 | } |
6857 | 0cbcd906 | aurel32 | |
6858 | 0cbcd906 | aurel32 | #define GEN_VXRFORM(name, opc2, opc3) \
|
6859 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
6860 | 0cbcd906 | aurel32 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
6861 | 0cbcd906 | aurel32 | |
6862 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequb, 3, 0) |
6863 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequh, 3, 1) |
6864 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpequw, 3, 2) |
6865 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
6866 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsh, 3, 13) |
6867 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtsw, 3, 14) |
6868 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtub, 3, 8) |
6869 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuh, 3, 9) |
6870 | 1add6e23 | aurel32 | GEN_VXRFORM(vcmpgtuw, 3, 10) |
6871 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6872 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6873 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpgtfp, 3, 11) |
6874 | 819ca121 | aurel32 | GEN_VXRFORM(vcmpbfp, 3, 15) |
6875 | 1add6e23 | aurel32 | |
6876 | c026766b | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6877 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6878 | c026766b | aurel32 | { \ |
6879 | c026766b | aurel32 | TCGv_ptr rd; \ |
6880 | c026766b | aurel32 | TCGv_i32 simm; \ |
6881 | c026766b | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6882 | c026766b | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6883 | c026766b | aurel32 | return; \
|
6884 | c026766b | aurel32 | } \ |
6885 | c026766b | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6886 | c026766b | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6887 | c026766b | aurel32 | gen_helper_##name (rd, simm); \ |
6888 | c026766b | aurel32 | tcg_temp_free_i32(simm); \ |
6889 | c026766b | aurel32 | tcg_temp_free_ptr(rd); \ |
6890 | c026766b | aurel32 | } |
6891 | c026766b | aurel32 | |
6892 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisb, 6, 12); |
6893 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltish, 6, 13); |
6894 | c026766b | aurel32 | GEN_VXFORM_SIMM(vspltisw, 6, 14); |
6895 | c026766b | aurel32 | |
6896 | de5f2484 | aurel32 | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
6897 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6898 | de5f2484 | aurel32 | { \ |
6899 | de5f2484 | aurel32 | TCGv_ptr rb, rd; \ |
6900 | de5f2484 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6901 | de5f2484 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6902 | de5f2484 | aurel32 | return; \
|
6903 | de5f2484 | aurel32 | } \ |
6904 | de5f2484 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6905 | de5f2484 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6906 | de5f2484 | aurel32 | gen_helper_##name (rd, rb); \ |
6907 | de5f2484 | aurel32 | tcg_temp_free_ptr(rb); \ |
6908 | de5f2484 | aurel32 | tcg_temp_free_ptr(rd); \ |
6909 | de5f2484 | aurel32 | } |
6910 | de5f2484 | aurel32 | |
6911 | d15f74fb | Blue Swirl | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
|
6912 | d15f74fb | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6913 | d15f74fb | Blue Swirl | { \ |
6914 | d15f74fb | Blue Swirl | TCGv_ptr rb, rd; \ |
6915 | d15f74fb | Blue Swirl | \ |
6916 | d15f74fb | Blue Swirl | if (unlikely(!ctx->altivec_enabled)) { \
|
6917 | d15f74fb | Blue Swirl | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6918 | d15f74fb | Blue Swirl | return; \
|
6919 | d15f74fb | Blue Swirl | } \ |
6920 | d15f74fb | Blue Swirl | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6921 | d15f74fb | Blue Swirl | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6922 | d15f74fb | Blue Swirl | gen_helper_##name(cpu_env, rd, rb); \ |
6923 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(rb); \ |
6924 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(rd); \ |
6925 | d15f74fb | Blue Swirl | } |
6926 | d15f74fb | Blue Swirl | |
6927 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6928 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupkhsh, 7, 9); |
6929 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
6930 | 6cf1c6e5 | aurel32 | GEN_VXFORM_NOA(vupklsh, 7, 11); |
6931 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6932 | 79f85c3a | aurel32 | GEN_VXFORM_NOA(vupklpx, 7, 15); |
6933 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
6934 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); |
6935 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); |
6936 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); |
6937 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); |
6938 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); |
6939 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); |
6940 | d15f74fb | Blue Swirl | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); |
6941 | 79f85c3a | aurel32 | |
6942 | 21d21583 | aurel32 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
6943 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6944 | 21d21583 | aurel32 | { \ |
6945 | 21d21583 | aurel32 | TCGv_ptr rd; \ |
6946 | 21d21583 | aurel32 | TCGv_i32 simm; \ |
6947 | 21d21583 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6948 | 21d21583 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6949 | 21d21583 | aurel32 | return; \
|
6950 | 21d21583 | aurel32 | } \ |
6951 | 21d21583 | aurel32 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ |
6952 | 21d21583 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6953 | 21d21583 | aurel32 | gen_helper_##name (rd, simm); \ |
6954 | 21d21583 | aurel32 | tcg_temp_free_i32(simm); \ |
6955 | 21d21583 | aurel32 | tcg_temp_free_ptr(rd); \ |
6956 | 21d21583 | aurel32 | } |
6957 | 21d21583 | aurel32 | |
6958 | 27a4edb3 | aurel32 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
6959 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6960 | 27a4edb3 | aurel32 | { \ |
6961 | 27a4edb3 | aurel32 | TCGv_ptr rb, rd; \ |
6962 | 27a4edb3 | aurel32 | TCGv_i32 uimm; \ |
6963 | 27a4edb3 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
6964 | 27a4edb3 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6965 | 27a4edb3 | aurel32 | return; \
|
6966 | 27a4edb3 | aurel32 | } \ |
6967 | 27a4edb3 | aurel32 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ |
6968 | 27a4edb3 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6969 | 27a4edb3 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6970 | 27a4edb3 | aurel32 | gen_helper_##name (rd, rb, uimm); \ |
6971 | 27a4edb3 | aurel32 | tcg_temp_free_i32(uimm); \ |
6972 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rb); \ |
6973 | 27a4edb3 | aurel32 | tcg_temp_free_ptr(rd); \ |
6974 | 27a4edb3 | aurel32 | } |
6975 | 27a4edb3 | aurel32 | |
6976 | d15f74fb | Blue Swirl | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
|
6977 | d15f74fb | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
6978 | d15f74fb | Blue Swirl | { \ |
6979 | d15f74fb | Blue Swirl | TCGv_ptr rb, rd; \ |
6980 | d15f74fb | Blue Swirl | TCGv_i32 uimm; \ |
6981 | d15f74fb | Blue Swirl | \ |
6982 | d15f74fb | Blue Swirl | if (unlikely(!ctx->altivec_enabled)) { \
|
6983 | d15f74fb | Blue Swirl | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
6984 | d15f74fb | Blue Swirl | return; \
|
6985 | d15f74fb | Blue Swirl | } \ |
6986 | d15f74fb | Blue Swirl | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ |
6987 | d15f74fb | Blue Swirl | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
6988 | d15f74fb | Blue Swirl | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
6989 | d15f74fb | Blue Swirl | gen_helper_##name(cpu_env, rd, rb, uimm); \ |
6990 | d15f74fb | Blue Swirl | tcg_temp_free_i32(uimm); \ |
6991 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(rb); \ |
6992 | d15f74fb | Blue Swirl | tcg_temp_free_ptr(rd); \ |
6993 | d15f74fb | Blue Swirl | } |
6994 | d15f74fb | Blue Swirl | |
6995 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6996 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vsplth, 6, 9); |
6997 | e4e6bee7 | aurel32 | GEN_VXFORM_UIMM(vspltw, 6, 10); |
6998 | d15f74fb | Blue Swirl | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
6999 | d15f74fb | Blue Swirl | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); |
7000 | d15f74fb | Blue Swirl | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); |
7001 | d15f74fb | Blue Swirl | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); |
7002 | e4e6bee7 | aurel32 | |
7003 | 99e300ef | Blue Swirl | static void gen_vsldoi(DisasContext *ctx) |
7004 | cd633b10 | aurel32 | { |
7005 | cd633b10 | aurel32 | TCGv_ptr ra, rb, rd; |
7006 | fce5ecb7 | aurel32 | TCGv_i32 sh; |
7007 | cd633b10 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
7008 | cd633b10 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
7009 | cd633b10 | aurel32 | return;
|
7010 | cd633b10 | aurel32 | } |
7011 | cd633b10 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
7012 | cd633b10 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
7013 | cd633b10 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
7014 | cd633b10 | aurel32 | sh = tcg_const_i32(VSH(ctx->opcode)); |
7015 | cd633b10 | aurel32 | gen_helper_vsldoi (rd, ra, rb, sh); |
7016 | cd633b10 | aurel32 | tcg_temp_free_ptr(ra); |
7017 | cd633b10 | aurel32 | tcg_temp_free_ptr(rb); |
7018 | cd633b10 | aurel32 | tcg_temp_free_ptr(rd); |
7019 | fce5ecb7 | aurel32 | tcg_temp_free_i32(sh); |
7020 | cd633b10 | aurel32 | } |
7021 | cd633b10 | aurel32 | |
7022 | 707cec33 | aurel32 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
7023 | d15f74fb | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
7024 | 707cec33 | aurel32 | { \ |
7025 | 707cec33 | aurel32 | TCGv_ptr ra, rb, rc, rd; \ |
7026 | 707cec33 | aurel32 | if (unlikely(!ctx->altivec_enabled)) { \
|
7027 | 707cec33 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
7028 | 707cec33 | aurel32 | return; \
|
7029 | 707cec33 | aurel32 | } \ |
7030 | 707cec33 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); \ |
7031 | 707cec33 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); \ |
7032 | 707cec33 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); \ |
7033 | 707cec33 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); \ |
7034 | 707cec33 | aurel32 | if (Rc(ctx->opcode)) { \
|
7035 | d15f74fb | Blue Swirl | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
7036 | 707cec33 | aurel32 | } else { \
|
7037 | d15f74fb | Blue Swirl | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
7038 | 707cec33 | aurel32 | } \ |
7039 | 707cec33 | aurel32 | tcg_temp_free_ptr(ra); \ |
7040 | 707cec33 | aurel32 | tcg_temp_free_ptr(rb); \ |
7041 | 707cec33 | aurel32 | tcg_temp_free_ptr(rc); \ |
7042 | 707cec33 | aurel32 | tcg_temp_free_ptr(rd); \ |
7043 | 707cec33 | aurel32 | } |
7044 | 707cec33 | aurel32 | |
7045 | b161ae27 | aurel32 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
|
7046 | b161ae27 | aurel32 | |
7047 | 99e300ef | Blue Swirl | static void gen_vmladduhm(DisasContext *ctx) |
7048 | bcd2ee23 | aurel32 | { |
7049 | bcd2ee23 | aurel32 | TCGv_ptr ra, rb, rc, rd; |
7050 | bcd2ee23 | aurel32 | if (unlikely(!ctx->altivec_enabled)) {
|
7051 | bcd2ee23 | aurel32 | gen_exception(ctx, POWERPC_EXCP_VPU); |
7052 | bcd2ee23 | aurel32 | return;
|
7053 | bcd2ee23 | aurel32 | } |
7054 | bcd2ee23 | aurel32 | ra = gen_avr_ptr(rA(ctx->opcode)); |
7055 | bcd2ee23 | aurel32 | rb = gen_avr_ptr(rB(ctx->opcode)); |
7056 | bcd2ee23 | aurel32 | rc = gen_avr_ptr(rC(ctx->opcode)); |
7057 | bcd2ee23 | aurel32 | rd = gen_avr_ptr(rD(ctx->opcode)); |
7058 | bcd2ee23 | aurel32 | gen_helper_vmladduhm(rd, ra, rb, rc); |
7059 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(ra); |
7060 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rb); |
7061 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rc); |
7062 | bcd2ee23 | aurel32 | tcg_temp_free_ptr(rd); |
7063 | bcd2ee23 | aurel32 | } |
7064 | bcd2ee23 | aurel32 | |
7065 | b04ae981 | aurel32 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
|
7066 | 4d9903b6 | aurel32 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
|
7067 | eae07261 | aurel32 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
|
7068 | d1258698 | aurel32 | GEN_VAFORM_PAIRED(vsel, vperm, 21)
|
7069 | 35cf7c7e | aurel32 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
|
7070 | b04ae981 | aurel32 | |
7071 | 472b24ce | Tom Musta | /*** VSX extension ***/
|
7072 | 472b24ce | Tom Musta | |
7073 | 472b24ce | Tom Musta | static inline TCGv_i64 cpu_vsrh(int n) |
7074 | 472b24ce | Tom Musta | { |
7075 | 472b24ce | Tom Musta | if (n < 32) { |
7076 | 472b24ce | Tom Musta | return cpu_fpr[n];
|
7077 | 472b24ce | Tom Musta | } else {
|
7078 | 472b24ce | Tom Musta | return cpu_avrh[n-32]; |
7079 | 472b24ce | Tom Musta | } |
7080 | 472b24ce | Tom Musta | } |
7081 | 472b24ce | Tom Musta | |
7082 | 472b24ce | Tom Musta | static inline TCGv_i64 cpu_vsrl(int n) |
7083 | 472b24ce | Tom Musta | { |
7084 | 472b24ce | Tom Musta | if (n < 32) { |
7085 | 472b24ce | Tom Musta | return cpu_vsr[n];
|
7086 | 472b24ce | Tom Musta | } else {
|
7087 | 472b24ce | Tom Musta | return cpu_avrl[n-32]; |
7088 | 472b24ce | Tom Musta | } |
7089 | 472b24ce | Tom Musta | } |
7090 | 472b24ce | Tom Musta | |
7091 | e072fe79 | Tom Musta | #define VSX_LOAD_SCALAR(name, operation) \
|
7092 | e072fe79 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
7093 | e072fe79 | Tom Musta | { \ |
7094 | e072fe79 | Tom Musta | TCGv EA; \ |
7095 | e072fe79 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7096 | e072fe79 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7097 | e072fe79 | Tom Musta | return; \
|
7098 | e072fe79 | Tom Musta | } \ |
7099 | e072fe79 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); \ |
7100 | e072fe79 | Tom Musta | EA = tcg_temp_new(); \ |
7101 | e072fe79 | Tom Musta | gen_addr_reg_index(ctx, EA); \ |
7102 | e072fe79 | Tom Musta | gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \ |
7103 | e072fe79 | Tom Musta | /* NOTE: cpu_vsrl is undefined */ \
|
7104 | e072fe79 | Tom Musta | tcg_temp_free(EA); \ |
7105 | e072fe79 | Tom Musta | } |
7106 | e072fe79 | Tom Musta | |
7107 | e072fe79 | Tom Musta | VSX_LOAD_SCALAR(lxsdx, ld64) |
7108 | cac7f0ba | Tom Musta | VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) |
7109 | cac7f0ba | Tom Musta | VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) |
7110 | cac7f0ba | Tom Musta | VSX_LOAD_SCALAR(lxsspx, ld32fs) |
7111 | fa1832d7 | Tom Musta | |
7112 | 304af367 | Tom Musta | static void gen_lxvd2x(DisasContext *ctx) |
7113 | 304af367 | Tom Musta | { |
7114 | 304af367 | Tom Musta | TCGv EA; |
7115 | 304af367 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7116 | 304af367 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7117 | 304af367 | Tom Musta | return;
|
7118 | 304af367 | Tom Musta | } |
7119 | 304af367 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); |
7120 | 304af367 | Tom Musta | EA = tcg_temp_new(); |
7121 | 304af367 | Tom Musta | gen_addr_reg_index(ctx, EA); |
7122 | 304af367 | Tom Musta | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); |
7123 | 304af367 | Tom Musta | tcg_gen_addi_tl(EA, EA, 8);
|
7124 | 304af367 | Tom Musta | gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); |
7125 | 304af367 | Tom Musta | tcg_temp_free(EA); |
7126 | 304af367 | Tom Musta | } |
7127 | 304af367 | Tom Musta | |
7128 | ca03b467 | Tom Musta | static void gen_lxvdsx(DisasContext *ctx) |
7129 | ca03b467 | Tom Musta | { |
7130 | ca03b467 | Tom Musta | TCGv EA; |
7131 | ca03b467 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7132 | ca03b467 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7133 | ca03b467 | Tom Musta | return;
|
7134 | ca03b467 | Tom Musta | } |
7135 | ca03b467 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); |
7136 | ca03b467 | Tom Musta | EA = tcg_temp_new(); |
7137 | ca03b467 | Tom Musta | gen_addr_reg_index(ctx, EA); |
7138 | ca03b467 | Tom Musta | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); |
7139 | f976b09e | Alexander Graf | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); |
7140 | ca03b467 | Tom Musta | tcg_temp_free(EA); |
7141 | ca03b467 | Tom Musta | } |
7142 | ca03b467 | Tom Musta | |
7143 | 897e61d1 | Tom Musta | static void gen_lxvw4x(DisasContext *ctx) |
7144 | 897e61d1 | Tom Musta | { |
7145 | f976b09e | Alexander Graf | TCGv EA; |
7146 | f976b09e | Alexander Graf | TCGv_i64 tmp; |
7147 | 897e61d1 | Tom Musta | TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); |
7148 | 897e61d1 | Tom Musta | TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); |
7149 | 897e61d1 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7150 | 897e61d1 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7151 | 897e61d1 | Tom Musta | return;
|
7152 | 897e61d1 | Tom Musta | } |
7153 | 897e61d1 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); |
7154 | 897e61d1 | Tom Musta | EA = tcg_temp_new(); |
7155 | f976b09e | Alexander Graf | tmp = tcg_temp_new_i64(); |
7156 | f976b09e | Alexander Graf | |
7157 | 897e61d1 | Tom Musta | gen_addr_reg_index(ctx, EA); |
7158 | f976b09e | Alexander Graf | gen_qemu_ld32u_i64(ctx, tmp, EA); |
7159 | 897e61d1 | Tom Musta | tcg_gen_addi_tl(EA, EA, 4);
|
7160 | f976b09e | Alexander Graf | gen_qemu_ld32u_i64(ctx, xth, EA); |
7161 | 897e61d1 | Tom Musta | tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); |
7162 | 897e61d1 | Tom Musta | |
7163 | 897e61d1 | Tom Musta | tcg_gen_addi_tl(EA, EA, 4);
|
7164 | f976b09e | Alexander Graf | gen_qemu_ld32u_i64(ctx, tmp, EA); |
7165 | 897e61d1 | Tom Musta | tcg_gen_addi_tl(EA, EA, 4);
|
7166 | f976b09e | Alexander Graf | gen_qemu_ld32u_i64(ctx, xtl, EA); |
7167 | 897e61d1 | Tom Musta | tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); |
7168 | 897e61d1 | Tom Musta | |
7169 | 897e61d1 | Tom Musta | tcg_temp_free(EA); |
7170 | f976b09e | Alexander Graf | tcg_temp_free_i64(tmp); |
7171 | 897e61d1 | Tom Musta | } |
7172 | 897e61d1 | Tom Musta | |
7173 | f026da78 | Tom Musta | #define VSX_STORE_SCALAR(name, operation) \
|
7174 | f026da78 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
7175 | f026da78 | Tom Musta | { \ |
7176 | f026da78 | Tom Musta | TCGv EA; \ |
7177 | f026da78 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7178 | f026da78 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7179 | f026da78 | Tom Musta | return; \
|
7180 | f026da78 | Tom Musta | } \ |
7181 | f026da78 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); \ |
7182 | f026da78 | Tom Musta | EA = tcg_temp_new(); \ |
7183 | f026da78 | Tom Musta | gen_addr_reg_index(ctx, EA); \ |
7184 | f026da78 | Tom Musta | gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \ |
7185 | f026da78 | Tom Musta | tcg_temp_free(EA); \ |
7186 | 9231ba9e | Tom Musta | } |
7187 | 9231ba9e | Tom Musta | |
7188 | f026da78 | Tom Musta | VSX_STORE_SCALAR(stxsdx, st64) |
7189 | e16a626b | Tom Musta | VSX_STORE_SCALAR(stxsiwx, st32_i64) |
7190 | e16a626b | Tom Musta | VSX_STORE_SCALAR(stxsspx, st32fs) |
7191 | f026da78 | Tom Musta | |
7192 | fbed2478 | Tom Musta | static void gen_stxvd2x(DisasContext *ctx) |
7193 | fbed2478 | Tom Musta | { |
7194 | fbed2478 | Tom Musta | TCGv EA; |
7195 | fbed2478 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7196 | fbed2478 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7197 | fbed2478 | Tom Musta | return;
|
7198 | fbed2478 | Tom Musta | } |
7199 | fbed2478 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); |
7200 | fbed2478 | Tom Musta | EA = tcg_temp_new(); |
7201 | fbed2478 | Tom Musta | gen_addr_reg_index(ctx, EA); |
7202 | fbed2478 | Tom Musta | gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); |
7203 | fbed2478 | Tom Musta | tcg_gen_addi_tl(EA, EA, 8);
|
7204 | fbed2478 | Tom Musta | gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); |
7205 | fbed2478 | Tom Musta | tcg_temp_free(EA); |
7206 | fbed2478 | Tom Musta | } |
7207 | fbed2478 | Tom Musta | |
7208 | 86e61ce3 | Tom Musta | static void gen_stxvw4x(DisasContext *ctx) |
7209 | 86e61ce3 | Tom Musta | { |
7210 | f976b09e | Alexander Graf | TCGv_i64 tmp; |
7211 | f976b09e | Alexander Graf | TCGv EA; |
7212 | 86e61ce3 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7213 | 86e61ce3 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7214 | 86e61ce3 | Tom Musta | return;
|
7215 | 86e61ce3 | Tom Musta | } |
7216 | 86e61ce3 | Tom Musta | gen_set_access_type(ctx, ACCESS_INT); |
7217 | 86e61ce3 | Tom Musta | EA = tcg_temp_new(); |
7218 | 86e61ce3 | Tom Musta | gen_addr_reg_index(ctx, EA); |
7219 | f976b09e | Alexander Graf | tmp = tcg_temp_new_i64(); |
7220 | 86e61ce3 | Tom Musta | |
7221 | 86e61ce3 | Tom Musta | tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
|
7222 | f976b09e | Alexander Graf | gen_qemu_st32_i64(ctx, tmp, EA); |
7223 | 86e61ce3 | Tom Musta | tcg_gen_addi_tl(EA, EA, 4);
|
7224 | f976b09e | Alexander Graf | gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); |
7225 | 86e61ce3 | Tom Musta | |
7226 | 86e61ce3 | Tom Musta | tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
|
7227 | 86e61ce3 | Tom Musta | tcg_gen_addi_tl(EA, EA, 4);
|
7228 | f976b09e | Alexander Graf | gen_qemu_st32_i64(ctx, tmp, EA); |
7229 | 86e61ce3 | Tom Musta | tcg_gen_addi_tl(EA, EA, 4);
|
7230 | f976b09e | Alexander Graf | gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); |
7231 | 86e61ce3 | Tom Musta | |
7232 | 86e61ce3 | Tom Musta | tcg_temp_free(EA); |
7233 | f976b09e | Alexander Graf | tcg_temp_free_i64(tmp); |
7234 | 86e61ce3 | Tom Musta | } |
7235 | 86e61ce3 | Tom Musta | |
7236 | f5c0f7f9 | Tom Musta | #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
|
7237 | f5c0f7f9 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
7238 | f5c0f7f9 | Tom Musta | { \ |
7239 | f5c0f7f9 | Tom Musta | if (xS(ctx->opcode) < 32) { \ |
7240 | f5c0f7f9 | Tom Musta | if (unlikely(!ctx->fpu_enabled)) { \
|
7241 | f5c0f7f9 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
7242 | f5c0f7f9 | Tom Musta | return; \
|
7243 | f5c0f7f9 | Tom Musta | } \ |
7244 | f5c0f7f9 | Tom Musta | } else { \
|
7245 | f5c0f7f9 | Tom Musta | if (unlikely(!ctx->altivec_enabled)) { \
|
7246 | f5c0f7f9 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
7247 | f5c0f7f9 | Tom Musta | return; \
|
7248 | f5c0f7f9 | Tom Musta | } \ |
7249 | f5c0f7f9 | Tom Musta | } \ |
7250 | f5c0f7f9 | Tom Musta | TCGv_i64 tmp = tcg_temp_new_i64(); \ |
7251 | f5c0f7f9 | Tom Musta | tcg_gen_##tcgop1(tmp, source); \ |
7252 | f5c0f7f9 | Tom Musta | tcg_gen_##tcgop2(target, tmp); \ |
7253 | f5c0f7f9 | Tom Musta | tcg_temp_free_i64(tmp); \ |
7254 | f5c0f7f9 | Tom Musta | } |
7255 | f5c0f7f9 | Tom Musta | |
7256 | f5c0f7f9 | Tom Musta | |
7257 | f5c0f7f9 | Tom Musta | MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \ |
7258 | f5c0f7f9 | Tom Musta | cpu_vsrh(xS(ctx->opcode))) |
7259 | f5c0f7f9 | Tom Musta | MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \ |
7260 | f5c0f7f9 | Tom Musta | cpu_gpr[rA(ctx->opcode)]) |
7261 | f5c0f7f9 | Tom Musta | MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \ |
7262 | f5c0f7f9 | Tom Musta | cpu_gpr[rA(ctx->opcode)]) |
7263 | f5c0f7f9 | Tom Musta | |
7264 | f5c0f7f9 | Tom Musta | #if defined(TARGET_PPC64)
|
7265 | f5c0f7f9 | Tom Musta | #define MV_VSRD(name, target, source) \
|
7266 | f5c0f7f9 | Tom Musta | static void gen_##name(DisasContext *ctx) \ |
7267 | f5c0f7f9 | Tom Musta | { \ |
7268 | f5c0f7f9 | Tom Musta | if (xS(ctx->opcode) < 32) { \ |
7269 | f5c0f7f9 | Tom Musta | if (unlikely(!ctx->fpu_enabled)) { \
|
7270 | f5c0f7f9 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
7271 | f5c0f7f9 | Tom Musta | return; \
|
7272 | f5c0f7f9 | Tom Musta | } \ |
7273 | f5c0f7f9 | Tom Musta | } else { \
|
7274 | f5c0f7f9 | Tom Musta | if (unlikely(!ctx->altivec_enabled)) { \
|
7275 | f5c0f7f9 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
7276 | f5c0f7f9 | Tom Musta | return; \
|
7277 | f5c0f7f9 | Tom Musta | } \ |
7278 | f5c0f7f9 | Tom Musta | } \ |
7279 | f5c0f7f9 | Tom Musta | tcg_gen_mov_i64(target, source); \ |
7280 | f5c0f7f9 | Tom Musta | } |
7281 | f5c0f7f9 | Tom Musta | |
7282 | f5c0f7f9 | Tom Musta | MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) |
7283 | f5c0f7f9 | Tom Musta | MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) |
7284 | f5c0f7f9 | Tom Musta | |
7285 | f5c0f7f9 | Tom Musta | #endif
|
7286 | f5c0f7f9 | Tom Musta | |
7287 | cd73f2c9 | Tom Musta | static void gen_xxpermdi(DisasContext *ctx) |
7288 | cd73f2c9 | Tom Musta | { |
7289 | cd73f2c9 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7290 | cd73f2c9 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7291 | cd73f2c9 | Tom Musta | return;
|
7292 | cd73f2c9 | Tom Musta | } |
7293 | cd73f2c9 | Tom Musta | |
7294 | cd73f2c9 | Tom Musta | if ((DM(ctx->opcode) & 2) == 0) { |
7295 | cd73f2c9 | Tom Musta | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode))); |
7296 | cd73f2c9 | Tom Musta | } else {
|
7297 | cd73f2c9 | Tom Musta | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode))); |
7298 | cd73f2c9 | Tom Musta | } |
7299 | cd73f2c9 | Tom Musta | if ((DM(ctx->opcode) & 1) == 0) { |
7300 | cd73f2c9 | Tom Musta | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode))); |
7301 | cd73f2c9 | Tom Musta | } else {
|
7302 | cd73f2c9 | Tom Musta | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode))); |
7303 | cd73f2c9 | Tom Musta | } |
7304 | cd73f2c9 | Tom Musta | } |
7305 | cd73f2c9 | Tom Musta | |
7306 | df020ce0 | Tom Musta | #define OP_ABS 1 |
7307 | df020ce0 | Tom Musta | #define OP_NABS 2 |
7308 | df020ce0 | Tom Musta | #define OP_NEG 3 |
7309 | df020ce0 | Tom Musta | #define OP_CPSGN 4 |
7310 | df020ce0 | Tom Musta | #define SGN_MASK_DP 0x8000000000000000ul |
7311 | df020ce0 | Tom Musta | #define SGN_MASK_SP 0x8000000080000000ul |
7312 | df020ce0 | Tom Musta | |
7313 | df020ce0 | Tom Musta | #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
|
7314 | df020ce0 | Tom Musta | static void glue(gen_, name)(DisasContext * ctx) \ |
7315 | df020ce0 | Tom Musta | { \ |
7316 | df020ce0 | Tom Musta | TCGv_i64 xb, sgm; \ |
7317 | df020ce0 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7318 | df020ce0 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7319 | df020ce0 | Tom Musta | return; \
|
7320 | df020ce0 | Tom Musta | } \ |
7321 | f976b09e | Alexander Graf | xb = tcg_temp_new_i64(); \ |
7322 | f976b09e | Alexander Graf | sgm = tcg_temp_new_i64(); \ |
7323 | df020ce0 | Tom Musta | tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ |
7324 | df020ce0 | Tom Musta | tcg_gen_movi_i64(sgm, sgn_mask); \ |
7325 | df020ce0 | Tom Musta | switch (op) { \
|
7326 | df020ce0 | Tom Musta | case OP_ABS: { \
|
7327 | df020ce0 | Tom Musta | tcg_gen_andc_i64(xb, xb, sgm); \ |
7328 | df020ce0 | Tom Musta | break; \
|
7329 | df020ce0 | Tom Musta | } \ |
7330 | df020ce0 | Tom Musta | case OP_NABS: { \
|
7331 | df020ce0 | Tom Musta | tcg_gen_or_i64(xb, xb, sgm); \ |
7332 | df020ce0 | Tom Musta | break; \
|
7333 | df020ce0 | Tom Musta | } \ |
7334 | df020ce0 | Tom Musta | case OP_NEG: { \
|
7335 | df020ce0 | Tom Musta | tcg_gen_xor_i64(xb, xb, sgm); \ |
7336 | df020ce0 | Tom Musta | break; \
|
7337 | df020ce0 | Tom Musta | } \ |
7338 | df020ce0 | Tom Musta | case OP_CPSGN: { \
|
7339 | f976b09e | Alexander Graf | TCGv_i64 xa = tcg_temp_new_i64(); \ |
7340 | df020ce0 | Tom Musta | tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ |
7341 | df020ce0 | Tom Musta | tcg_gen_and_i64(xa, xa, sgm); \ |
7342 | df020ce0 | Tom Musta | tcg_gen_andc_i64(xb, xb, sgm); \ |
7343 | df020ce0 | Tom Musta | tcg_gen_or_i64(xb, xb, xa); \ |
7344 | f976b09e | Alexander Graf | tcg_temp_free_i64(xa); \ |
7345 | df020ce0 | Tom Musta | break; \
|
7346 | df020ce0 | Tom Musta | } \ |
7347 | df020ce0 | Tom Musta | } \ |
7348 | df020ce0 | Tom Musta | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ |
7349 | f976b09e | Alexander Graf | tcg_temp_free_i64(xb); \ |
7350 | f976b09e | Alexander Graf | tcg_temp_free_i64(sgm); \ |
7351 | df020ce0 | Tom Musta | } |
7352 | df020ce0 | Tom Musta | |
7353 | df020ce0 | Tom Musta | VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) |
7354 | df020ce0 | Tom Musta | VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) |
7355 | df020ce0 | Tom Musta | VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) |
7356 | df020ce0 | Tom Musta | VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) |
7357 | df020ce0 | Tom Musta | |
7358 | be574920 | Tom Musta | #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
|
7359 | be574920 | Tom Musta | static void glue(gen_, name)(DisasContext * ctx) \ |
7360 | be574920 | Tom Musta | { \ |
7361 | be574920 | Tom Musta | TCGv_i64 xbh, xbl, sgm; \ |
7362 | be574920 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7363 | be574920 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7364 | be574920 | Tom Musta | return; \
|
7365 | be574920 | Tom Musta | } \ |
7366 | f976b09e | Alexander Graf | xbh = tcg_temp_new_i64(); \ |
7367 | f976b09e | Alexander Graf | xbl = tcg_temp_new_i64(); \ |
7368 | f976b09e | Alexander Graf | sgm = tcg_temp_new_i64(); \ |
7369 | be574920 | Tom Musta | tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ |
7370 | be574920 | Tom Musta | tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ |
7371 | be574920 | Tom Musta | tcg_gen_movi_i64(sgm, sgn_mask); \ |
7372 | be574920 | Tom Musta | switch (op) { \
|
7373 | be574920 | Tom Musta | case OP_ABS: { \
|
7374 | be574920 | Tom Musta | tcg_gen_andc_i64(xbh, xbh, sgm); \ |
7375 | be574920 | Tom Musta | tcg_gen_andc_i64(xbl, xbl, sgm); \ |
7376 | be574920 | Tom Musta | break; \
|
7377 | be574920 | Tom Musta | } \ |
7378 | be574920 | Tom Musta | case OP_NABS: { \
|
7379 | be574920 | Tom Musta | tcg_gen_or_i64(xbh, xbh, sgm); \ |
7380 | be574920 | Tom Musta | tcg_gen_or_i64(xbl, xbl, sgm); \ |
7381 | be574920 | Tom Musta | break; \
|
7382 | be574920 | Tom Musta | } \ |
7383 | be574920 | Tom Musta | case OP_NEG: { \
|
7384 | be574920 | Tom Musta | tcg_gen_xor_i64(xbh, xbh, sgm); \ |
7385 | be574920 | Tom Musta | tcg_gen_xor_i64(xbl, xbl, sgm); \ |
7386 | be574920 | Tom Musta | break; \
|
7387 | be574920 | Tom Musta | } \ |
7388 | be574920 | Tom Musta | case OP_CPSGN: { \
|
7389 | f976b09e | Alexander Graf | TCGv_i64 xah = tcg_temp_new_i64(); \ |
7390 | f976b09e | Alexander Graf | TCGv_i64 xal = tcg_temp_new_i64(); \ |
7391 | be574920 | Tom Musta | tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ |
7392 | be574920 | Tom Musta | tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ |
7393 | be574920 | Tom Musta | tcg_gen_and_i64(xah, xah, sgm); \ |
7394 | be574920 | Tom Musta | tcg_gen_and_i64(xal, xal, sgm); \ |
7395 | be574920 | Tom Musta | tcg_gen_andc_i64(xbh, xbh, sgm); \ |
7396 | be574920 | Tom Musta | tcg_gen_andc_i64(xbl, xbl, sgm); \ |
7397 | be574920 | Tom Musta | tcg_gen_or_i64(xbh, xbh, xah); \ |
7398 | be574920 | Tom Musta | tcg_gen_or_i64(xbl, xbl, xal); \ |
7399 | f976b09e | Alexander Graf | tcg_temp_free_i64(xah); \ |
7400 | f976b09e | Alexander Graf | tcg_temp_free_i64(xal); \ |
7401 | be574920 | Tom Musta | break; \
|
7402 | be574920 | Tom Musta | } \ |
7403 | be574920 | Tom Musta | } \ |
7404 | be574920 | Tom Musta | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ |
7405 | be574920 | Tom Musta | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ |
7406 | f976b09e | Alexander Graf | tcg_temp_free_i64(xbh); \ |
7407 | f976b09e | Alexander Graf | tcg_temp_free_i64(xbl); \ |
7408 | f976b09e | Alexander Graf | tcg_temp_free_i64(sgm); \ |
7409 | be574920 | Tom Musta | } |
7410 | be574920 | Tom Musta | |
7411 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) |
7412 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) |
7413 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) |
7414 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) |
7415 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) |
7416 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) |
7417 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) |
7418 | be574920 | Tom Musta | VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) |
7419 | be574920 | Tom Musta | |
7420 | 3c3cbbdc | Tom Musta | #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
|
7421 | 3c3cbbdc | Tom Musta | static void gen_##name(DisasContext * ctx) \ |
7422 | 3c3cbbdc | Tom Musta | { \ |
7423 | 3c3cbbdc | Tom Musta | TCGv_i32 opc; \ |
7424 | 3c3cbbdc | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7425 | 3c3cbbdc | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7426 | 3c3cbbdc | Tom Musta | return; \
|
7427 | 3c3cbbdc | Tom Musta | } \ |
7428 | 3c3cbbdc | Tom Musta | /* NIP cannot be restored if the memory exception comes from an helper */ \
|
7429 | 3c3cbbdc | Tom Musta | gen_update_nip(ctx, ctx->nip - 4); \
|
7430 | 3c3cbbdc | Tom Musta | opc = tcg_const_i32(ctx->opcode); \ |
7431 | 3c3cbbdc | Tom Musta | gen_helper_##name(cpu_env, opc); \ |
7432 | 3c3cbbdc | Tom Musta | tcg_temp_free_i32(opc); \ |
7433 | 3c3cbbdc | Tom Musta | } |
7434 | be574920 | Tom Musta | |
7435 | 3d1140bf | Tom Musta | #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
|
7436 | 3d1140bf | Tom Musta | static void gen_##name(DisasContext * ctx) \ |
7437 | 3d1140bf | Tom Musta | { \ |
7438 | 3d1140bf | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7439 | 3d1140bf | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7440 | 3d1140bf | Tom Musta | return; \
|
7441 | 3d1140bf | Tom Musta | } \ |
7442 | 3d1140bf | Tom Musta | /* NIP cannot be restored if the exception comes */ \
|
7443 | 3d1140bf | Tom Musta | /* from a helper. */ \
|
7444 | 3d1140bf | Tom Musta | gen_update_nip(ctx, ctx->nip - 4); \
|
7445 | 3d1140bf | Tom Musta | \ |
7446 | 3d1140bf | Tom Musta | gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ |
7447 | 3d1140bf | Tom Musta | cpu_vsrh(xB(ctx->opcode))); \ |
7448 | 3d1140bf | Tom Musta | } |
7449 | 3d1140bf | Tom Musta | |
7450 | ee6e02c0 | Tom Musta | GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) |
7451 | ee6e02c0 | Tom Musta | GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX) |
7452 | 5e591d88 | Tom Musta | GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) |
7453 | 4b98eeef | Tom Musta | GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) |
7454 | 2009227f | Tom Musta | GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) |
7455 | d32404fe | Tom Musta | GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) |
7456 | d3f9df8f | Tom Musta | GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) |
7457 | bc80838f | Tom Musta | GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) |
7458 | 5cb151ac | Tom Musta | GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) |
7459 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) |
7460 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) |
7461 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) |
7462 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) |
7463 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) |
7464 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) |
7465 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) |
7466 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) |
7467 | 4f17e9c7 | Tom Musta | GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) |
7468 | 4f17e9c7 | Tom Musta | GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) |
7469 | 959e9c9d | Tom Musta | GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) |
7470 | 959e9c9d | Tom Musta | GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX) |
7471 | ed8ac568 | Tom Musta | GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) |
7472 | 7ee19fb9 | Tom Musta | GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) |
7473 | ed8ac568 | Tom Musta | GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) |
7474 | 7ee19fb9 | Tom Musta | GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) |
7475 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) |
7476 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) |
7477 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) |
7478 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) |
7479 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) |
7480 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) |
7481 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) |
7482 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) |
7483 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) |
7484 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) |
7485 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) |
7486 | 3d1140bf | Tom Musta | GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) |
7487 | ee6e02c0 | Tom Musta | |
7488 | 3fd0aadf | Tom Musta | GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) |
7489 | 3fd0aadf | Tom Musta | GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) |
7490 | ab9408a2 | Tom Musta | GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) |
7491 | b24d0b47 | Tom Musta | GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) |
7492 | 2c0c52ae | Tom Musta | GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) |
7493 | cea4e574 | Tom Musta | GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) |
7494 | 968e76bc | Tom Musta | GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) |
7495 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) |
7496 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) |
7497 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) |
7498 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) |
7499 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) |
7500 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) |
7501 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) |
7502 | f53f81e0 | Tom Musta | GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) |
7503 | 74698350 | Tom Musta | GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) |
7504 | 74698350 | Tom Musta | GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) |
7505 | 3fd0aadf | Tom Musta | |
7506 | ee6e02c0 | Tom Musta | GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) |
7507 | ee6e02c0 | Tom Musta | GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) |
7508 | 5e591d88 | Tom Musta | GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) |
7509 | 4b98eeef | Tom Musta | GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) |
7510 | 2009227f | Tom Musta | GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) |
7511 | d32404fe | Tom Musta | GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) |
7512 | d3f9df8f | Tom Musta | GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) |
7513 | bc80838f | Tom Musta | GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) |
7514 | 5cb151ac | Tom Musta | GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) |
7515 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) |
7516 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) |
7517 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) |
7518 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) |
7519 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) |
7520 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) |
7521 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) |
7522 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) |
7523 | 959e9c9d | Tom Musta | GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) |
7524 | 959e9c9d | Tom Musta | GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) |
7525 | 354a6dec | Tom Musta | GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) |
7526 | 354a6dec | Tom Musta | GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) |
7527 | 354a6dec | Tom Musta | GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) |
7528 | ed8ac568 | Tom Musta | GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) |
7529 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) |
7530 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) |
7531 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) |
7532 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) |
7533 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) |
7534 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) |
7535 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) |
7536 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) |
7537 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) |
7538 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) |
7539 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) |
7540 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) |
7541 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) |
7542 | ee6e02c0 | Tom Musta | |
7543 | ee6e02c0 | Tom Musta | GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) |
7544 | ee6e02c0 | Tom Musta | GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) |
7545 | 5e591d88 | Tom Musta | GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) |
7546 | 4b98eeef | Tom Musta | GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) |
7547 | 2009227f | Tom Musta | GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) |
7548 | d32404fe | Tom Musta | GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) |
7549 | d3f9df8f | Tom Musta | GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) |
7550 | bc80838f | Tom Musta | GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) |
7551 | 5cb151ac | Tom Musta | GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) |
7552 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) |
7553 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) |
7554 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) |
7555 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) |
7556 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) |
7557 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) |
7558 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) |
7559 | 595c6eef | Tom Musta | GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) |
7560 | 959e9c9d | Tom Musta | GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) |
7561 | 959e9c9d | Tom Musta | GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX) |
7562 | 354a6dec | Tom Musta | GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) |
7563 | 354a6dec | Tom Musta | GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) |
7564 | 354a6dec | Tom Musta | GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) |
7565 | ed8ac568 | Tom Musta | GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) |
7566 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) |
7567 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) |
7568 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) |
7569 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) |
7570 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) |
7571 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) |
7572 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) |
7573 | 5177d2ca | Tom Musta | GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) |
7574 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) |
7575 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) |
7576 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) |
7577 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) |
7578 | 88e33d08 | Tom Musta | GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) |
7579 | ee6e02c0 | Tom Musta | |
7580 | 79ca8a6a | Tom Musta | #define VSX_LOGICAL(name, tcg_op) \
|
7581 | 79ca8a6a | Tom Musta | static void glue(gen_, name)(DisasContext * ctx) \ |
7582 | 79ca8a6a | Tom Musta | { \ |
7583 | 79ca8a6a | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7584 | 79ca8a6a | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7585 | 79ca8a6a | Tom Musta | return; \
|
7586 | 79ca8a6a | Tom Musta | } \ |
7587 | 79ca8a6a | Tom Musta | tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ |
7588 | 79ca8a6a | Tom Musta | cpu_vsrh(xB(ctx->opcode))); \ |
7589 | 79ca8a6a | Tom Musta | tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ |
7590 | 79ca8a6a | Tom Musta | cpu_vsrl(xB(ctx->opcode))); \ |
7591 | 79ca8a6a | Tom Musta | } |
7592 | 79ca8a6a | Tom Musta | |
7593 | f976b09e | Alexander Graf | VSX_LOGICAL(xxland, tcg_gen_and_i64) |
7594 | f976b09e | Alexander Graf | VSX_LOGICAL(xxlandc, tcg_gen_andc_i64) |
7595 | f976b09e | Alexander Graf | VSX_LOGICAL(xxlor, tcg_gen_or_i64) |
7596 | f976b09e | Alexander Graf | VSX_LOGICAL(xxlxor, tcg_gen_xor_i64) |
7597 | f976b09e | Alexander Graf | VSX_LOGICAL(xxlnor, tcg_gen_nor_i64) |
7598 | 67a33f37 | Tom Musta | VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64) |
7599 | 67a33f37 | Tom Musta | VSX_LOGICAL(xxlnand, tcg_gen_nand_i64) |
7600 | 67a33f37 | Tom Musta | VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) |
7601 | df020ce0 | Tom Musta | |
7602 | ce577d2e | Tom Musta | #define VSX_XXMRG(name, high) \
|
7603 | ce577d2e | Tom Musta | static void glue(gen_, name)(DisasContext * ctx) \ |
7604 | ce577d2e | Tom Musta | { \ |
7605 | ce577d2e | Tom Musta | TCGv_i64 a0, a1, b0, b1; \ |
7606 | ce577d2e | Tom Musta | if (unlikely(!ctx->vsx_enabled)) { \
|
7607 | ce577d2e | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); \ |
7608 | ce577d2e | Tom Musta | return; \
|
7609 | ce577d2e | Tom Musta | } \ |
7610 | f976b09e | Alexander Graf | a0 = tcg_temp_new_i64(); \ |
7611 | f976b09e | Alexander Graf | a1 = tcg_temp_new_i64(); \ |
7612 | f976b09e | Alexander Graf | b0 = tcg_temp_new_i64(); \ |
7613 | f976b09e | Alexander Graf | b1 = tcg_temp_new_i64(); \ |
7614 | ce577d2e | Tom Musta | if (high) { \
|
7615 | ce577d2e | Tom Musta | tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ |
7616 | ce577d2e | Tom Musta | tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ |
7617 | ce577d2e | Tom Musta | tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ |
7618 | ce577d2e | Tom Musta | tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ |
7619 | ce577d2e | Tom Musta | } else { \
|
7620 | ce577d2e | Tom Musta | tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ |
7621 | ce577d2e | Tom Musta | tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ |
7622 | ce577d2e | Tom Musta | tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ |
7623 | ce577d2e | Tom Musta | tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ |
7624 | ce577d2e | Tom Musta | } \ |
7625 | ce577d2e | Tom Musta | tcg_gen_shri_i64(a0, a0, 32); \
|
7626 | ce577d2e | Tom Musta | tcg_gen_shri_i64(b0, b0, 32); \
|
7627 | ce577d2e | Tom Musta | tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ |
7628 | ce577d2e | Tom Musta | b0, a0, 32, 32); \ |
7629 | ce577d2e | Tom Musta | tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ |
7630 | ce577d2e | Tom Musta | b1, a1, 32, 32); \ |
7631 | f976b09e | Alexander Graf | tcg_temp_free_i64(a0); \ |
7632 | f976b09e | Alexander Graf | tcg_temp_free_i64(a1); \ |
7633 | f976b09e | Alexander Graf | tcg_temp_free_i64(b0); \ |
7634 | f976b09e | Alexander Graf | tcg_temp_free_i64(b1); \ |
7635 | ce577d2e | Tom Musta | } |
7636 | ce577d2e | Tom Musta | |
7637 | ce577d2e | Tom Musta | VSX_XXMRG(xxmrghw, 1)
|
7638 | ce577d2e | Tom Musta | VSX_XXMRG(xxmrglw, 0)
|
7639 | ce577d2e | Tom Musta | |
7640 | 551e3ef7 | Tom Musta | static void gen_xxsel(DisasContext * ctx) |
7641 | 551e3ef7 | Tom Musta | { |
7642 | 551e3ef7 | Tom Musta | TCGv_i64 a, b, c; |
7643 | 551e3ef7 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7644 | 551e3ef7 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7645 | 551e3ef7 | Tom Musta | return;
|
7646 | 551e3ef7 | Tom Musta | } |
7647 | f976b09e | Alexander Graf | a = tcg_temp_new_i64(); |
7648 | f976b09e | Alexander Graf | b = tcg_temp_new_i64(); |
7649 | f976b09e | Alexander Graf | c = tcg_temp_new_i64(); |
7650 | 551e3ef7 | Tom Musta | |
7651 | 551e3ef7 | Tom Musta | tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); |
7652 | 551e3ef7 | Tom Musta | tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); |
7653 | 551e3ef7 | Tom Musta | tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); |
7654 | 551e3ef7 | Tom Musta | |
7655 | 551e3ef7 | Tom Musta | tcg_gen_and_i64(b, b, c); |
7656 | 551e3ef7 | Tom Musta | tcg_gen_andc_i64(a, a, c); |
7657 | 551e3ef7 | Tom Musta | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); |
7658 | 551e3ef7 | Tom Musta | |
7659 | 551e3ef7 | Tom Musta | tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); |
7660 | 551e3ef7 | Tom Musta | tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); |
7661 | 551e3ef7 | Tom Musta | tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); |
7662 | 551e3ef7 | Tom Musta | |
7663 | 551e3ef7 | Tom Musta | tcg_gen_and_i64(b, b, c); |
7664 | 551e3ef7 | Tom Musta | tcg_gen_andc_i64(a, a, c); |
7665 | 551e3ef7 | Tom Musta | tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); |
7666 | 551e3ef7 | Tom Musta | |
7667 | f976b09e | Alexander Graf | tcg_temp_free_i64(a); |
7668 | f976b09e | Alexander Graf | tcg_temp_free_i64(b); |
7669 | f976b09e | Alexander Graf | tcg_temp_free_i64(c); |
7670 | 551e3ef7 | Tom Musta | } |
7671 | 551e3ef7 | Tom Musta | |
7672 | 76c15fe0 | Tom Musta | static void gen_xxspltw(DisasContext *ctx) |
7673 | 76c15fe0 | Tom Musta | { |
7674 | 76c15fe0 | Tom Musta | TCGv_i64 b, b2; |
7675 | 76c15fe0 | Tom Musta | TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
|
7676 | 76c15fe0 | Tom Musta | cpu_vsrl(xB(ctx->opcode)) : |
7677 | 76c15fe0 | Tom Musta | cpu_vsrh(xB(ctx->opcode)); |
7678 | 76c15fe0 | Tom Musta | |
7679 | 76c15fe0 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7680 | 76c15fe0 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7681 | 76c15fe0 | Tom Musta | return;
|
7682 | 76c15fe0 | Tom Musta | } |
7683 | 76c15fe0 | Tom Musta | |
7684 | f976b09e | Alexander Graf | b = tcg_temp_new_i64(); |
7685 | f976b09e | Alexander Graf | b2 = tcg_temp_new_i64(); |
7686 | 76c15fe0 | Tom Musta | |
7687 | 76c15fe0 | Tom Musta | if (UIM(ctx->opcode) & 1) { |
7688 | 76c15fe0 | Tom Musta | tcg_gen_ext32u_i64(b, vsr); |
7689 | 76c15fe0 | Tom Musta | } else {
|
7690 | 76c15fe0 | Tom Musta | tcg_gen_shri_i64(b, vsr, 32);
|
7691 | 76c15fe0 | Tom Musta | } |
7692 | 76c15fe0 | Tom Musta | |
7693 | 76c15fe0 | Tom Musta | tcg_gen_shli_i64(b2, b, 32);
|
7694 | 76c15fe0 | Tom Musta | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); |
7695 | 76c15fe0 | Tom Musta | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); |
7696 | 76c15fe0 | Tom Musta | |
7697 | f976b09e | Alexander Graf | tcg_temp_free_i64(b); |
7698 | f976b09e | Alexander Graf | tcg_temp_free_i64(b2); |
7699 | 76c15fe0 | Tom Musta | } |
7700 | 76c15fe0 | Tom Musta | |
7701 | acc42968 | Tom Musta | static void gen_xxsldwi(DisasContext *ctx) |
7702 | acc42968 | Tom Musta | { |
7703 | acc42968 | Tom Musta | TCGv_i64 xth, xtl; |
7704 | acc42968 | Tom Musta | if (unlikely(!ctx->vsx_enabled)) {
|
7705 | acc42968 | Tom Musta | gen_exception(ctx, POWERPC_EXCP_VSXU); |
7706 | acc42968 | Tom Musta | return;
|
7707 | acc42968 | Tom Musta | } |
7708 | f976b09e | Alexander Graf | xth = tcg_temp_new_i64(); |
7709 | f976b09e | Alexander Graf | xtl = tcg_temp_new_i64(); |
7710 | acc42968 | Tom Musta | |
7711 | acc42968 | Tom Musta | switch (SHW(ctx->opcode)) {
|
7712 | acc42968 | Tom Musta | case 0: { |
7713 | acc42968 | Tom Musta | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); |
7714 | acc42968 | Tom Musta | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); |
7715 | acc42968 | Tom Musta | break;
|
7716 | acc42968 | Tom Musta | } |
7717 | acc42968 | Tom Musta | case 1: { |
7718 | f976b09e | Alexander Graf | TCGv_i64 t0 = tcg_temp_new_i64(); |
7719 | acc42968 | Tom Musta | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); |
7720 | acc42968 | Tom Musta | tcg_gen_shli_i64(xth, xth, 32);
|
7721 | acc42968 | Tom Musta | tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); |
7722 | acc42968 | Tom Musta | tcg_gen_shri_i64(t0, t0, 32);
|
7723 | acc42968 | Tom Musta | tcg_gen_or_i64(xth, xth, t0); |
7724 | acc42968 | Tom Musta | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); |
7725 | acc42968 | Tom Musta | tcg_gen_shli_i64(xtl, xtl, 32);
|
7726 | acc42968 | Tom Musta | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); |
7727 | acc42968 | Tom Musta | tcg_gen_shri_i64(t0, t0, 32);
|
7728 | acc42968 | Tom Musta | tcg_gen_or_i64(xtl, xtl, t0); |
7729 | f976b09e | Alexander Graf | tcg_temp_free_i64(t0); |
7730 | acc42968 | Tom Musta | break;
|
7731 | acc42968 | Tom Musta | } |
7732 | acc42968 | Tom Musta | case 2: { |
7733 | acc42968 | Tom Musta | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); |
7734 | acc42968 | Tom Musta | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); |
7735 | acc42968 | Tom Musta | break;
|
7736 | acc42968 | Tom Musta | } |
7737 | acc42968 | Tom Musta | case 3: { |
7738 | f976b09e | Alexander Graf | TCGv_i64 t0 = tcg_temp_new_i64(); |
7739 | acc42968 | Tom Musta | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); |
7740 | acc42968 | Tom Musta | tcg_gen_shli_i64(xth, xth, 32);
|
7741 | acc42968 | Tom Musta | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); |
7742 | acc42968 | Tom Musta | tcg_gen_shri_i64(t0, t0, 32);
|
7743 | acc42968 | Tom Musta | tcg_gen_or_i64(xth, xth, t0); |
7744 | acc42968 | Tom Musta | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); |
7745 | acc42968 | Tom Musta | tcg_gen_shli_i64(xtl, xtl, 32);
|
7746 | acc42968 | Tom Musta | tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); |
7747 | acc42968 | Tom Musta | tcg_gen_shri_i64(t0, t0, 32);
|
7748 | acc42968 | Tom Musta | tcg_gen_or_i64(xtl, xtl, t0); |
7749 | f976b09e | Alexander Graf | tcg_temp_free_i64(t0); |
7750 | acc42968 | Tom Musta | break;
|
7751 | acc42968 | Tom Musta | } |
7752 | acc42968 | Tom Musta | } |
7753 | acc42968 | Tom Musta | |
7754 | acc42968 | Tom Musta | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); |
7755 | acc42968 | Tom Musta | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); |
7756 | acc42968 | Tom Musta | |
7757 | f976b09e | Alexander Graf | tcg_temp_free_i64(xth); |
7758 | f976b09e | Alexander Graf | tcg_temp_free_i64(xtl); |
7759 | acc42968 | Tom Musta | } |
7760 | acc42968 | Tom Musta | |
7761 | ce577d2e | Tom Musta | |
7762 | 0487d6a8 | j_mayer | /*** SPE extension ***/
|
7763 | 0487d6a8 | j_mayer | /* Register moves */
|
7764 | 3cd7d1dd | j_mayer | |
7765 | a0e13900 | Fabien Chouteau | static inline void gen_evmra(DisasContext *ctx) |
7766 | a0e13900 | Fabien Chouteau | { |
7767 | a0e13900 | Fabien Chouteau | |
7768 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
7769 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
7770 | a0e13900 | Fabien Chouteau | return;
|
7771 | a0e13900 | Fabien Chouteau | } |
7772 | a0e13900 | Fabien Chouteau | |
7773 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
7774 | a0e13900 | Fabien Chouteau | /* rD := rA */
|
7775 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7776 | a0e13900 | Fabien Chouteau | |
7777 | a0e13900 | Fabien Chouteau | /* spe_acc := rA */
|
7778 | a0e13900 | Fabien Chouteau | tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)], |
7779 | a0e13900 | Fabien Chouteau | cpu_env, |
7780 | 1328c2bf | Andreas Färber | offsetof(CPUPPCState, spe_acc)); |
7781 | a0e13900 | Fabien Chouteau | #else
|
7782 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp = tcg_temp_new_i64(); |
7783 | a0e13900 | Fabien Chouteau | |
7784 | a0e13900 | Fabien Chouteau | /* tmp := rA_lo + rA_hi << 32 */
|
7785 | a0e13900 | Fabien Chouteau | tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
7786 | a0e13900 | Fabien Chouteau | |
7787 | a0e13900 | Fabien Chouteau | /* spe_acc := tmp */
|
7788 | 1328c2bf | Andreas Färber | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
7789 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
7790 | a0e13900 | Fabien Chouteau | |
7791 | a0e13900 | Fabien Chouteau | /* rD := rA */
|
7792 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
7793 | a0e13900 | Fabien Chouteau | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
7794 | a0e13900 | Fabien Chouteau | #endif
|
7795 | a0e13900 | Fabien Chouteau | } |
7796 | a0e13900 | Fabien Chouteau | |
7797 | 636aa200 | Blue Swirl | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
7798 | 636aa200 | Blue Swirl | { |
7799 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
7800 | f78fb44e | aurel32 | tcg_gen_mov_i64(t, cpu_gpr[reg]); |
7801 | f78fb44e | aurel32 | #else
|
7802 | 36aa55dc | pbrook | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
7803 | 3cd7d1dd | j_mayer | #endif
|
7804 | f78fb44e | aurel32 | } |
7805 | 3cd7d1dd | j_mayer | |
7806 | 636aa200 | Blue Swirl | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
7807 | 636aa200 | Blue Swirl | { |
7808 | f78fb44e | aurel32 | #if defined(TARGET_PPC64)
|
7809 | f78fb44e | aurel32 | tcg_gen_mov_i64(cpu_gpr[reg], t); |
7810 | f78fb44e | aurel32 | #else
|
7811 | a7812ae4 | pbrook | TCGv_i64 tmp = tcg_temp_new_i64(); |
7812 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
7813 | f78fb44e | aurel32 | tcg_gen_shri_i64(tmp, t, 32);
|
7814 | f78fb44e | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); |
7815 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp); |
7816 | 3cd7d1dd | j_mayer | #endif
|
7817 | f78fb44e | aurel32 | } |
7818 | 3cd7d1dd | j_mayer | |
7819 | 70560da7 | Fabien Chouteau | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
|
7820 | 99e300ef | Blue Swirl | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
7821 | 0487d6a8 | j_mayer | { \ |
7822 | 0487d6a8 | j_mayer | if (Rc(ctx->opcode)) \
|
7823 | 0487d6a8 | j_mayer | gen_##name1(ctx); \ |
7824 | 0487d6a8 | j_mayer | else \
|
7825 | 0487d6a8 | j_mayer | gen_##name0(ctx); \ |
7826 | 0487d6a8 | j_mayer | } |
7827 | 0487d6a8 | j_mayer | |
7828 | 0487d6a8 | j_mayer | /* Handler for undefined SPE opcodes */
|
7829 | 636aa200 | Blue Swirl | static inline void gen_speundef(DisasContext *ctx) |
7830 | 0487d6a8 | j_mayer | { |
7831 | e06fcd75 | aurel32 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
7832 | 0487d6a8 | j_mayer | } |
7833 | 0487d6a8 | j_mayer | |
7834 | 57951c27 | aurel32 | /* SPE logic */
|
7835 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7836 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
7837 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7838 | 0487d6a8 | j_mayer | { \ |
7839 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
7840 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7841 | 0487d6a8 | j_mayer | return; \
|
7842 | 0487d6a8 | j_mayer | } \ |
7843 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7844 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
7845 | 57951c27 | aurel32 | } |
7846 | 57951c27 | aurel32 | #else
|
7847 | 57951c27 | aurel32 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \
|
7848 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7849 | 57951c27 | aurel32 | { \ |
7850 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7851 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7852 | 57951c27 | aurel32 | return; \
|
7853 | 57951c27 | aurel32 | } \ |
7854 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7855 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
7856 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
7857 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
7858 | 0487d6a8 | j_mayer | } |
7859 | 57951c27 | aurel32 | #endif
|
7860 | 57951c27 | aurel32 | |
7861 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); |
7862 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); |
7863 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); |
7864 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); |
7865 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); |
7866 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); |
7867 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); |
7868 | 57951c27 | aurel32 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); |
7869 | 0487d6a8 | j_mayer | |
7870 | 57951c27 | aurel32 | /* SPE logic immediate */
|
7871 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7872 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
7873 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7874 | 3d3a6a0a | aurel32 | { \ |
7875 | 3d3a6a0a | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7876 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7877 | 3d3a6a0a | aurel32 | return; \
|
7878 | 3d3a6a0a | aurel32 | } \ |
7879 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7880 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
7881 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
7882 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7883 | 57951c27 | aurel32 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
7884 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
7885 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
7886 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
7887 | 57951c27 | aurel32 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
7888 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
7889 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
7890 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
7891 | 3d3a6a0a | aurel32 | } |
7892 | 57951c27 | aurel32 | #else
|
7893 | 57951c27 | aurel32 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
|
7894 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7895 | 0487d6a8 | j_mayer | { \ |
7896 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
7897 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7898 | 0487d6a8 | j_mayer | return; \
|
7899 | 0487d6a8 | j_mayer | } \ |
7900 | 57951c27 | aurel32 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7901 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
7902 | 57951c27 | aurel32 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
7903 | 57951c27 | aurel32 | rB(ctx->opcode)); \ |
7904 | 0487d6a8 | j_mayer | } |
7905 | 57951c27 | aurel32 | #endif
|
7906 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
7907 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); |
7908 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); |
7909 | 57951c27 | aurel32 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); |
7910 | 0487d6a8 | j_mayer | |
7911 | 57951c27 | aurel32 | /* SPE arithmetic */
|
7912 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7913 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
7914 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7915 | 0487d6a8 | j_mayer | { \ |
7916 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
7917 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7918 | 0487d6a8 | j_mayer | return; \
|
7919 | 0487d6a8 | j_mayer | } \ |
7920 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7921 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
7922 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
7923 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7924 | 57951c27 | aurel32 | tcg_op(t0, t0); \ |
7925 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
7926 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
7927 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
7928 | 57951c27 | aurel32 | tcg_op(t1, t1); \ |
7929 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
7930 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
7931 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
7932 | 0487d6a8 | j_mayer | } |
7933 | 57951c27 | aurel32 | #else
|
7934 | a7812ae4 | pbrook | #define GEN_SPEOP_ARITH1(name, tcg_op) \
|
7935 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7936 | 57951c27 | aurel32 | { \ |
7937 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
7938 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7939 | 57951c27 | aurel32 | return; \
|
7940 | 57951c27 | aurel32 | } \ |
7941 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
7942 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ |
7943 | 57951c27 | aurel32 | } |
7944 | 57951c27 | aurel32 | #endif
|
7945 | 0487d6a8 | j_mayer | |
7946 | 636aa200 | Blue Swirl | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
7947 | 57951c27 | aurel32 | { |
7948 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
7949 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
7950 | 0487d6a8 | j_mayer | |
7951 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
|
7952 | 57951c27 | aurel32 | tcg_gen_neg_i32(ret, arg1); |
7953 | 57951c27 | aurel32 | tcg_gen_br(l2); |
7954 | 57951c27 | aurel32 | gen_set_label(l1); |
7955 | a7812ae4 | pbrook | tcg_gen_mov_i32(ret, arg1); |
7956 | 57951c27 | aurel32 | gen_set_label(l2); |
7957 | 57951c27 | aurel32 | } |
7958 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); |
7959 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); |
7960 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); |
7961 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); |
7962 | 636aa200 | Blue Swirl | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
7963 | 0487d6a8 | j_mayer | { |
7964 | 57951c27 | aurel32 | tcg_gen_addi_i32(ret, arg1, 0x8000);
|
7965 | 57951c27 | aurel32 | tcg_gen_ext16u_i32(ret, ret); |
7966 | 57951c27 | aurel32 | } |
7967 | 57951c27 | aurel32 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); |
7968 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7969 | a7812ae4 | pbrook | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); |
7970 | 0487d6a8 | j_mayer | |
7971 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
7972 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
7973 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
7974 | 0487d6a8 | j_mayer | { \ |
7975 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
7976 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
7977 | 0487d6a8 | j_mayer | return; \
|
7978 | 0487d6a8 | j_mayer | } \ |
7979 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7980 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
7981 | a7812ae4 | pbrook | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ |
7982 | 501e23c4 | aurel32 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
7983 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7984 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ |
7985 | 57951c27 | aurel32 | tcg_op(t0, t0, t2); \ |
7986 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
|
7987 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t3); \ |
7988 | 57951c27 | aurel32 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
|
7989 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t2, t3); \ |
7990 | a7812ae4 | pbrook | tcg_temp_free_i64(t3); \ |
7991 | 57951c27 | aurel32 | tcg_op(t1, t1, t2); \ |
7992 | a7812ae4 | pbrook | tcg_temp_free_i32(t2); \ |
7993 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
7994 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
7995 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
7996 | 0487d6a8 | j_mayer | } |
7997 | 57951c27 | aurel32 | #else
|
7998 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH2(name, tcg_op) \
|
7999 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8000 | 0487d6a8 | j_mayer | { \ |
8001 | 0487d6a8 | j_mayer | if (unlikely(!ctx->spe_enabled)) { \
|
8002 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
8003 | 0487d6a8 | j_mayer | return; \
|
8004 | 0487d6a8 | j_mayer | } \ |
8005 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
8006 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)]); \ |
8007 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ |
8008 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)]); \ |
8009 | 0487d6a8 | j_mayer | } |
8010 | 57951c27 | aurel32 | #endif
|
8011 | 0487d6a8 | j_mayer | |
8012 | 636aa200 | Blue Swirl | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
8013 | 57951c27 | aurel32 | { |
8014 | a7812ae4 | pbrook | TCGv_i32 t0; |
8015 | 57951c27 | aurel32 | int l1, l2;
|
8016 | 0487d6a8 | j_mayer | |
8017 | 57951c27 | aurel32 | l1 = gen_new_label(); |
8018 | 57951c27 | aurel32 | l2 = gen_new_label(); |
8019 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
8020 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
8021 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
8022 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
8023 | 57951c27 | aurel32 | tcg_gen_shr_i32(ret, arg1, t0); |
8024 | 57951c27 | aurel32 | tcg_gen_br(l2); |
8025 | 57951c27 | aurel32 | gen_set_label(l1); |
8026 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
8027 | 0aef4261 | Aurelien Jarno | gen_set_label(l2); |
8028 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
8029 | 57951c27 | aurel32 | } |
8030 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); |
8031 | 636aa200 | Blue Swirl | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
8032 | 57951c27 | aurel32 | { |
8033 | a7812ae4 | pbrook | TCGv_i32 t0; |
8034 | 57951c27 | aurel32 | int l1, l2;
|
8035 | 57951c27 | aurel32 | |
8036 | 57951c27 | aurel32 | l1 = gen_new_label(); |
8037 | 57951c27 | aurel32 | l2 = gen_new_label(); |
8038 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
8039 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
8040 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
8041 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
8042 | 57951c27 | aurel32 | tcg_gen_sar_i32(ret, arg1, t0); |
8043 | 57951c27 | aurel32 | tcg_gen_br(l2); |
8044 | 57951c27 | aurel32 | gen_set_label(l1); |
8045 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
8046 | 0aef4261 | Aurelien Jarno | gen_set_label(l2); |
8047 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
8048 | 57951c27 | aurel32 | } |
8049 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); |
8050 | 636aa200 | Blue Swirl | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
8051 | 57951c27 | aurel32 | { |
8052 | a7812ae4 | pbrook | TCGv_i32 t0; |
8053 | 57951c27 | aurel32 | int l1, l2;
|
8054 | 57951c27 | aurel32 | |
8055 | 57951c27 | aurel32 | l1 = gen_new_label(); |
8056 | 57951c27 | aurel32 | l2 = gen_new_label(); |
8057 | a7812ae4 | pbrook | t0 = tcg_temp_local_new_i32(); |
8058 | 57951c27 | aurel32 | /* No error here: 6 bits are used */
|
8059 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x3F);
|
8060 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
|
8061 | 57951c27 | aurel32 | tcg_gen_shl_i32(ret, arg1, t0); |
8062 | 57951c27 | aurel32 | tcg_gen_br(l2); |
8063 | 57951c27 | aurel32 | gen_set_label(l1); |
8064 | 57951c27 | aurel32 | tcg_gen_movi_i32(ret, 0);
|
8065 | e29ef9fa | Aurelien Jarno | gen_set_label(l2); |
8066 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
8067 | 57951c27 | aurel32 | } |
8068 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); |
8069 | 636aa200 | Blue Swirl | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
8070 | 57951c27 | aurel32 | { |
8071 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_new_i32(); |
8072 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, arg2, 0x1F);
|
8073 | 57951c27 | aurel32 | tcg_gen_rotl_i32(ret, arg1, t0); |
8074 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
8075 | 57951c27 | aurel32 | } |
8076 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); |
8077 | 636aa200 | Blue Swirl | static inline void gen_evmergehi(DisasContext *ctx) |
8078 | 57951c27 | aurel32 | { |
8079 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8080 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8081 | 57951c27 | aurel32 | return;
|
8082 | 57951c27 | aurel32 | } |
8083 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8084 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
8085 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
8086 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
8087 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
8088 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
8089 | 57951c27 | aurel32 | tcg_temp_free(t0); |
8090 | 57951c27 | aurel32 | tcg_temp_free(t1); |
8091 | 57951c27 | aurel32 | #else
|
8092 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8093 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
8094 | 57951c27 | aurel32 | #endif
|
8095 | 57951c27 | aurel32 | } |
8096 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); |
8097 | 636aa200 | Blue Swirl | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
8098 | 0487d6a8 | j_mayer | { |
8099 | 57951c27 | aurel32 | tcg_gen_sub_i32(ret, arg2, arg1); |
8100 | 57951c27 | aurel32 | } |
8101 | 57951c27 | aurel32 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); |
8102 | 0487d6a8 | j_mayer | |
8103 | 57951c27 | aurel32 | /* SPE arithmetic immediate */
|
8104 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8105 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
8106 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8107 | 57951c27 | aurel32 | { \ |
8108 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8109 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
8110 | 57951c27 | aurel32 | return; \
|
8111 | 57951c27 | aurel32 | } \ |
8112 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
8113 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
8114 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
8115 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
8116 | 57951c27 | aurel32 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
8117 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
8118 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
8119 | e06fcd75 | aurel32 | tcg_temp_free_i64(t2); \ |
8120 | 57951c27 | aurel32 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
8121 | 57951c27 | aurel32 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
8122 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
8123 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
8124 | 57951c27 | aurel32 | } |
8125 | 57951c27 | aurel32 | #else
|
8126 | 57951c27 | aurel32 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
|
8127 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8128 | 57951c27 | aurel32 | { \ |
8129 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8130 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
8131 | 57951c27 | aurel32 | return; \
|
8132 | 57951c27 | aurel32 | } \ |
8133 | 57951c27 | aurel32 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
8134 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
8135 | 57951c27 | aurel32 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ |
8136 | 57951c27 | aurel32 | rA(ctx->opcode)); \ |
8137 | 57951c27 | aurel32 | } |
8138 | 57951c27 | aurel32 | #endif
|
8139 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
8140 | 57951c27 | aurel32 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); |
8141 | 57951c27 | aurel32 | |
8142 | 57951c27 | aurel32 | /* SPE comparison */
|
8143 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8144 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
8145 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8146 | 57951c27 | aurel32 | { \ |
8147 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8148 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
8149 | 57951c27 | aurel32 | return; \
|
8150 | 57951c27 | aurel32 | } \ |
8151 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
8152 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
8153 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
8154 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
8155 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
8156 | a7812ae4 | pbrook | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ |
8157 | a7812ae4 | pbrook | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ |
8158 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
8159 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
8160 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ |
8161 | a7812ae4 | pbrook | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
|
8162 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
8163 | 57951c27 | aurel32 | gen_set_label(l1); \ |
8164 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
8165 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
8166 | 57951c27 | aurel32 | gen_set_label(l2); \ |
8167 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
|
8168 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t0, t2); \ |
8169 | 57951c27 | aurel32 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
|
8170 | 57951c27 | aurel32 | tcg_gen_trunc_i64_i32(t1, t2); \ |
8171 | a7812ae4 | pbrook | tcg_temp_free_i64(t2); \ |
8172 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
8173 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
8174 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
8175 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
8176 | 57951c27 | aurel32 | gen_set_label(l3); \ |
8177 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
8178 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
8179 | 57951c27 | aurel32 | gen_set_label(l4); \ |
8180 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); \ |
8181 | a7812ae4 | pbrook | tcg_temp_free_i32(t1); \ |
8182 | 57951c27 | aurel32 | } |
8183 | 57951c27 | aurel32 | #else
|
8184 | 57951c27 | aurel32 | #define GEN_SPEOP_COMP(name, tcg_cond) \
|
8185 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
8186 | 57951c27 | aurel32 | { \ |
8187 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8188 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
8189 | 57951c27 | aurel32 | return; \
|
8190 | 57951c27 | aurel32 | } \ |
8191 | 57951c27 | aurel32 | int l1 = gen_new_label(); \
|
8192 | 57951c27 | aurel32 | int l2 = gen_new_label(); \
|
8193 | 57951c27 | aurel32 | int l3 = gen_new_label(); \
|
8194 | 57951c27 | aurel32 | int l4 = gen_new_label(); \
|
8195 | 57951c27 | aurel32 | \ |
8196 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ |
8197 | 57951c27 | aurel32 | cpu_gpr[rB(ctx->opcode)], l1); \ |
8198 | 57951c27 | aurel32 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
|
8199 | 57951c27 | aurel32 | tcg_gen_br(l2); \ |
8200 | 57951c27 | aurel32 | gen_set_label(l1); \ |
8201 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ |
8202 | 57951c27 | aurel32 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ |
8203 | 57951c27 | aurel32 | gen_set_label(l2); \ |
8204 | 57951c27 | aurel32 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
8205 | 57951c27 | aurel32 | cpu_gprh[rB(ctx->opcode)], l3); \ |
8206 | 57951c27 | aurel32 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
8207 | 57951c27 | aurel32 | ~(CRF_CH | CRF_CH_AND_CL)); \ |
8208 | 57951c27 | aurel32 | tcg_gen_br(l4); \ |
8209 | 57951c27 | aurel32 | gen_set_label(l3); \ |
8210 | 57951c27 | aurel32 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ |
8211 | 57951c27 | aurel32 | CRF_CH | CRF_CH_OR_CL); \ |
8212 | 57951c27 | aurel32 | gen_set_label(l4); \ |
8213 | 57951c27 | aurel32 | } |
8214 | 57951c27 | aurel32 | #endif
|
8215 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
8216 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); |
8217 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); |
8218 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); |
8219 | 57951c27 | aurel32 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); |
8220 | 57951c27 | aurel32 | |
8221 | 57951c27 | aurel32 | /* SPE misc */
|
8222 | 636aa200 | Blue Swirl | static inline void gen_brinc(DisasContext *ctx) |
8223 | 57951c27 | aurel32 | { |
8224 | 57951c27 | aurel32 | /* Note: brinc is usable even if SPE is disabled */
|
8225 | a7812ae4 | pbrook | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
8226 | a7812ae4 | pbrook | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8227 | 0487d6a8 | j_mayer | } |
8228 | 636aa200 | Blue Swirl | static inline void gen_evmergelo(DisasContext *ctx) |
8229 | 57951c27 | aurel32 | { |
8230 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8231 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8232 | 57951c27 | aurel32 | return;
|
8233 | 57951c27 | aurel32 | } |
8234 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8235 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
8236 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
8237 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
8238 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
8239 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
8240 | 57951c27 | aurel32 | tcg_temp_free(t0); |
8241 | 57951c27 | aurel32 | tcg_temp_free(t1); |
8242 | 57951c27 | aurel32 | #else
|
8243 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8244 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8245 | 57951c27 | aurel32 | #endif
|
8246 | 57951c27 | aurel32 | } |
8247 | 636aa200 | Blue Swirl | static inline void gen_evmergehilo(DisasContext *ctx) |
8248 | 57951c27 | aurel32 | { |
8249 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8250 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8251 | 57951c27 | aurel32 | return;
|
8252 | 57951c27 | aurel32 | } |
8253 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8254 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
8255 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
8256 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
8257 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
|
8258 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
8259 | 57951c27 | aurel32 | tcg_temp_free(t0); |
8260 | 57951c27 | aurel32 | tcg_temp_free(t1); |
8261 | 57951c27 | aurel32 | #else
|
8262 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8263 | 57951c27 | aurel32 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
8264 | 57951c27 | aurel32 | #endif
|
8265 | 57951c27 | aurel32 | } |
8266 | 636aa200 | Blue Swirl | static inline void gen_evmergelohi(DisasContext *ctx) |
8267 | 57951c27 | aurel32 | { |
8268 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
8269 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8270 | 57951c27 | aurel32 | return;
|
8271 | 57951c27 | aurel32 | } |
8272 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8273 | a7812ae4 | pbrook | TCGv t0 = tcg_temp_new(); |
8274 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_new(); |
8275 | 57951c27 | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
|
8276 | 57951c27 | aurel32 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
|
8277 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); |
8278 | 57951c27 | aurel32 | tcg_temp_free(t0); |
8279 | 57951c27 | aurel32 | tcg_temp_free(t1); |
8280 | 57951c27 | aurel32 | #else
|
8281 | 33890b3e | Nathan Froyd | if (rD(ctx->opcode) == rA(ctx->opcode)) {
|
8282 | 33890b3e | Nathan Froyd | TCGv_i32 tmp = tcg_temp_new_i32(); |
8283 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]); |
8284 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8285 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp); |
8286 | 33890b3e | Nathan Froyd | tcg_temp_free_i32(tmp); |
8287 | 33890b3e | Nathan Froyd | } else {
|
8288 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8289 | 33890b3e | Nathan Froyd | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8290 | 33890b3e | Nathan Froyd | } |
8291 | 57951c27 | aurel32 | #endif
|
8292 | 57951c27 | aurel32 | } |
8293 | 636aa200 | Blue Swirl | static inline void gen_evsplati(DisasContext *ctx) |
8294 | 57951c27 | aurel32 | { |
8295 | ae01847f | Nathan Froyd | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
8296 | 0487d6a8 | j_mayer | |
8297 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8298 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
8299 | 57951c27 | aurel32 | #else
|
8300 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
8301 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
8302 | 57951c27 | aurel32 | #endif
|
8303 | 57951c27 | aurel32 | } |
8304 | 636aa200 | Blue Swirl | static inline void gen_evsplatfi(DisasContext *ctx) |
8305 | 0487d6a8 | j_mayer | { |
8306 | ae01847f | Nathan Froyd | uint64_t imm = rA(ctx->opcode) << 27;
|
8307 | 0487d6a8 | j_mayer | |
8308 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8309 | 38d14952 | aurel32 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
|
8310 | 57951c27 | aurel32 | #else
|
8311 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); |
8312 | 57951c27 | aurel32 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); |
8313 | 57951c27 | aurel32 | #endif
|
8314 | 0487d6a8 | j_mayer | } |
8315 | 0487d6a8 | j_mayer | |
8316 | 636aa200 | Blue Swirl | static inline void gen_evsel(DisasContext *ctx) |
8317 | 57951c27 | aurel32 | { |
8318 | 57951c27 | aurel32 | int l1 = gen_new_label();
|
8319 | 57951c27 | aurel32 | int l2 = gen_new_label();
|
8320 | 57951c27 | aurel32 | int l3 = gen_new_label();
|
8321 | 57951c27 | aurel32 | int l4 = gen_new_label();
|
8322 | a7812ae4 | pbrook | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
8323 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8324 | a7812ae4 | pbrook | TCGv t1 = tcg_temp_local_new(); |
8325 | a7812ae4 | pbrook | TCGv t2 = tcg_temp_local_new(); |
8326 | 57951c27 | aurel32 | #endif
|
8327 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
8328 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
|
8329 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8330 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
8331 | 57951c27 | aurel32 | #else
|
8332 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
8333 | 57951c27 | aurel32 | #endif
|
8334 | 57951c27 | aurel32 | tcg_gen_br(l2); |
8335 | 57951c27 | aurel32 | gen_set_label(l1); |
8336 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8337 | 57951c27 | aurel32 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
|
8338 | 57951c27 | aurel32 | #else
|
8339 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8340 | 57951c27 | aurel32 | #endif
|
8341 | 57951c27 | aurel32 | gen_set_label(l2); |
8342 | 57951c27 | aurel32 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); |
8343 | 57951c27 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
|
8344 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8345 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); |
8346 | 57951c27 | aurel32 | #else
|
8347 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8348 | 57951c27 | aurel32 | #endif
|
8349 | 57951c27 | aurel32 | tcg_gen_br(l4); |
8350 | 57951c27 | aurel32 | gen_set_label(l3); |
8351 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8352 | 17d9b3af | Aurelien Jarno | tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); |
8353 | 57951c27 | aurel32 | #else
|
8354 | 57951c27 | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8355 | 57951c27 | aurel32 | #endif
|
8356 | 57951c27 | aurel32 | gen_set_label(l4); |
8357 | a7812ae4 | pbrook | tcg_temp_free_i32(t0); |
8358 | 57951c27 | aurel32 | #if defined(TARGET_PPC64)
|
8359 | 57951c27 | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); |
8360 | 57951c27 | aurel32 | tcg_temp_free(t1); |
8361 | 57951c27 | aurel32 | tcg_temp_free(t2); |
8362 | 57951c27 | aurel32 | #endif
|
8363 | 57951c27 | aurel32 | } |
8364 | e8eaa2c0 | Blue Swirl | |
8365 | e8eaa2c0 | Blue Swirl | static void gen_evsel0(DisasContext *ctx) |
8366 | 57951c27 | aurel32 | { |
8367 | 57951c27 | aurel32 | gen_evsel(ctx); |
8368 | 57951c27 | aurel32 | } |
8369 | e8eaa2c0 | Blue Swirl | |
8370 | e8eaa2c0 | Blue Swirl | static void gen_evsel1(DisasContext *ctx) |
8371 | 57951c27 | aurel32 | { |
8372 | 57951c27 | aurel32 | gen_evsel(ctx); |
8373 | 57951c27 | aurel32 | } |
8374 | e8eaa2c0 | Blue Swirl | |
8375 | e8eaa2c0 | Blue Swirl | static void gen_evsel2(DisasContext *ctx) |
8376 | 57951c27 | aurel32 | { |
8377 | 57951c27 | aurel32 | gen_evsel(ctx); |
8378 | 57951c27 | aurel32 | } |
8379 | e8eaa2c0 | Blue Swirl | |
8380 | e8eaa2c0 | Blue Swirl | static void gen_evsel3(DisasContext *ctx) |
8381 | 57951c27 | aurel32 | { |
8382 | 57951c27 | aurel32 | gen_evsel(ctx); |
8383 | 57951c27 | aurel32 | } |
8384 | 0487d6a8 | j_mayer | |
8385 | a0e13900 | Fabien Chouteau | /* Multiply */
|
8386 | a0e13900 | Fabien Chouteau | |
8387 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumi(DisasContext *ctx) |
8388 | a0e13900 | Fabien Chouteau | { |
8389 | a0e13900 | Fabien Chouteau | TCGv_i64 t0, t1; |
8390 | a0e13900 | Fabien Chouteau | |
8391 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
8392 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8393 | a0e13900 | Fabien Chouteau | return;
|
8394 | a0e13900 | Fabien Chouteau | } |
8395 | a0e13900 | Fabien Chouteau | |
8396 | a0e13900 | Fabien Chouteau | t0 = tcg_temp_new_i64(); |
8397 | a0e13900 | Fabien Chouteau | t1 = tcg_temp_new_i64(); |
8398 | a0e13900 | Fabien Chouteau | |
8399 | a0e13900 | Fabien Chouteau | /* t0 := rA; t1 := rB */
|
8400 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
8401 | a0e13900 | Fabien Chouteau | tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
8402 | a0e13900 | Fabien Chouteau | tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
8403 | a0e13900 | Fabien Chouteau | #else
|
8404 | a0e13900 | Fabien Chouteau | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
8405 | a0e13900 | Fabien Chouteau | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
8406 | a0e13900 | Fabien Chouteau | #endif
|
8407 | a0e13900 | Fabien Chouteau | |
8408 | a0e13900 | Fabien Chouteau | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
|
8409 | a0e13900 | Fabien Chouteau | |
8410 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
|
8411 | a0e13900 | Fabien Chouteau | |
8412 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t0); |
8413 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t1); |
8414 | a0e13900 | Fabien Chouteau | } |
8415 | a0e13900 | Fabien Chouteau | |
8416 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumia(DisasContext *ctx) |
8417 | a0e13900 | Fabien Chouteau | { |
8418 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
8419 | a0e13900 | Fabien Chouteau | |
8420 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
8421 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8422 | a0e13900 | Fabien Chouteau | return;
|
8423 | a0e13900 | Fabien Chouteau | } |
8424 | a0e13900 | Fabien Chouteau | |
8425 | a0e13900 | Fabien Chouteau | gen_evmwumi(ctx); /* rD := rA * rB */
|
8426 | a0e13900 | Fabien Chouteau | |
8427 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
8428 | a0e13900 | Fabien Chouteau | |
8429 | a0e13900 | Fabien Chouteau | /* acc := rD */
|
8430 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
8431 | 1328c2bf | Andreas Färber | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
8432 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
8433 | a0e13900 | Fabien Chouteau | } |
8434 | a0e13900 | Fabien Chouteau | |
8435 | a0e13900 | Fabien Chouteau | static inline void gen_evmwumiaa(DisasContext *ctx) |
8436 | a0e13900 | Fabien Chouteau | { |
8437 | a0e13900 | Fabien Chouteau | TCGv_i64 acc; |
8438 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
8439 | a0e13900 | Fabien Chouteau | |
8440 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
8441 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8442 | a0e13900 | Fabien Chouteau | return;
|
8443 | a0e13900 | Fabien Chouteau | } |
8444 | a0e13900 | Fabien Chouteau | |
8445 | a0e13900 | Fabien Chouteau | gen_evmwumi(ctx); /* rD := rA * rB */
|
8446 | a0e13900 | Fabien Chouteau | |
8447 | a0e13900 | Fabien Chouteau | acc = tcg_temp_new_i64(); |
8448 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
8449 | a0e13900 | Fabien Chouteau | |
8450 | a0e13900 | Fabien Chouteau | /* tmp := rD */
|
8451 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
8452 | a0e13900 | Fabien Chouteau | |
8453 | a0e13900 | Fabien Chouteau | /* Load acc */
|
8454 | 1328c2bf | Andreas Färber | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
8455 | a0e13900 | Fabien Chouteau | |
8456 | a0e13900 | Fabien Chouteau | /* acc := tmp + acc */
|
8457 | a0e13900 | Fabien Chouteau | tcg_gen_add_i64(acc, acc, tmp); |
8458 | a0e13900 | Fabien Chouteau | |
8459 | a0e13900 | Fabien Chouteau | /* Store acc */
|
8460 | 1328c2bf | Andreas Färber | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
8461 | a0e13900 | Fabien Chouteau | |
8462 | a0e13900 | Fabien Chouteau | /* rD := acc */
|
8463 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), acc); |
8464 | a0e13900 | Fabien Chouteau | |
8465 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(acc); |
8466 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
8467 | a0e13900 | Fabien Chouteau | } |
8468 | a0e13900 | Fabien Chouteau | |
8469 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmi(DisasContext *ctx) |
8470 | a0e13900 | Fabien Chouteau | { |
8471 | a0e13900 | Fabien Chouteau | TCGv_i64 t0, t1; |
8472 | a0e13900 | Fabien Chouteau | |
8473 | a0e13900 | Fabien Chouteau | if (unlikely(!ctx->spe_enabled)) {
|
8474 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
8475 | a0e13900 | Fabien Chouteau | return;
|
8476 | a0e13900 | Fabien Chouteau | } |
8477 | a0e13900 | Fabien Chouteau | |
8478 | a0e13900 | Fabien Chouteau | t0 = tcg_temp_new_i64(); |
8479 | a0e13900 | Fabien Chouteau | t1 = tcg_temp_new_i64(); |
8480 | a0e13900 | Fabien Chouteau | |
8481 | a0e13900 | Fabien Chouteau | /* t0 := rA; t1 := rB */
|
8482 | a0e13900 | Fabien Chouteau | #if defined(TARGET_PPC64)
|
8483 | a0e13900 | Fabien Chouteau | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
8484 | a0e13900 | Fabien Chouteau | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
8485 | a0e13900 | Fabien Chouteau | #else
|
8486 | a0e13900 | Fabien Chouteau | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
8487 | a0e13900 | Fabien Chouteau | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
8488 | a0e13900 | Fabien Chouteau | #endif
|
8489 | a0e13900 | Fabien Chouteau | |
8490 | a0e13900 | Fabien Chouteau | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
|
8491 | a0e13900 | Fabien Chouteau | |
8492 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
|
8493 | a0e13900 | Fabien Chouteau | |
8494 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t0); |
8495 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(t1); |
8496 | a0e13900 | Fabien Chouteau | } |
8497 | a0e13900 | Fabien Chouteau | |
8498 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmia(DisasContext *ctx) |
8499 | a0e13900 | Fabien Chouteau | { |
8500 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp; |
8501 | a0e13900 | Fabien Chouteau | |
8502 | a0e13900 | Fabien Chouteau | gen_evmwsmi(ctx); /* rD := rA * rB */
|
8503 | a0e13900 | Fabien Chouteau | |
8504 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
8505 | a0e13900 | Fabien Chouteau | |
8506 | a0e13900 | Fabien Chouteau | /* acc := rD */
|
8507 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
8508 | 1328c2bf | Andreas Färber | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
8509 | a0e13900 | Fabien Chouteau | |
8510 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
8511 | a0e13900 | Fabien Chouteau | } |
8512 | a0e13900 | Fabien Chouteau | |
8513 | a0e13900 | Fabien Chouteau | static inline void gen_evmwsmiaa(DisasContext *ctx) |
8514 | a0e13900 | Fabien Chouteau | { |
8515 | a0e13900 | Fabien Chouteau | TCGv_i64 acc = tcg_temp_new_i64(); |
8516 | a0e13900 | Fabien Chouteau | TCGv_i64 tmp = tcg_temp_new_i64(); |
8517 | a0e13900 | Fabien Chouteau | |
8518 | a0e13900 | Fabien Chouteau | gen_evmwsmi(ctx); /* rD := rA * rB */
|
8519 | a0e13900 | Fabien Chouteau | |
8520 | a0e13900 | Fabien Chouteau | acc = tcg_temp_new_i64(); |
8521 | a0e13900 | Fabien Chouteau | tmp = tcg_temp_new_i64(); |
8522 | a0e13900 | Fabien Chouteau | |
8523 | a0e13900 | Fabien Chouteau | /* tmp := rD */
|
8524 | a0e13900 | Fabien Chouteau | gen_load_gpr64(tmp, rD(ctx->opcode)); |
8525 | a0e13900 | Fabien Chouteau | |
8526 | a0e13900 | Fabien Chouteau | /* Load acc */
|
8527 | 1328c2bf | Andreas Färber | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
8528 | a0e13900 | Fabien Chouteau | |
8529 | a0e13900 | Fabien Chouteau | /* acc := tmp + acc */
|
8530 | a0e13900 | Fabien Chouteau | tcg_gen_add_i64(acc, acc, tmp); |
8531 | a0e13900 | Fabien Chouteau | |
8532 | a0e13900 | Fabien Chouteau | /* Store acc */
|
8533 | 1328c2bf | Andreas Färber | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
8534 | a0e13900 | Fabien Chouteau | |
8535 | a0e13900 | Fabien Chouteau | /* rD := acc */
|
8536 | a0e13900 | Fabien Chouteau | gen_store_gpr64(rD(ctx->opcode), acc); |
8537 | a0e13900 | Fabien Chouteau | |
8538 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(acc); |
8539 | a0e13900 | Fabien Chouteau | tcg_temp_free_i64(tmp); |
8540 | a0e13900 | Fabien Chouteau | } |
8541 | a0e13900 | Fabien Chouteau | |
8542 | 70560da7 | Fabien Chouteau | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8543 | 70560da7 | Fabien Chouteau | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
8544 | 70560da7 | Fabien Chouteau | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8545 | 70560da7 | Fabien Chouteau | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
8546 | 70560da7 | Fabien Chouteau | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// |
8547 | 70560da7 | Fabien Chouteau | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// |
8548 | 70560da7 | Fabien Chouteau | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// |
8549 | 70560da7 | Fabien Chouteau | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // |
8550 | 70560da7 | Fabien Chouteau | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); |
8551 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// |
8552 | 70560da7 | Fabien Chouteau | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8553 | 70560da7 | Fabien Chouteau | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
8554 | 70560da7 | Fabien Chouteau | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
8555 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); |
8556 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); |
8557 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); |
8558 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// |
8559 | 70560da7 | Fabien Chouteau | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8560 | 70560da7 | Fabien Chouteau | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
8561 | 70560da7 | Fabien Chouteau | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); |
8562 | 70560da7 | Fabien Chouteau | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8563 | 70560da7 | Fabien Chouteau | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); |
8564 | 70560da7 | Fabien Chouteau | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // |
8565 | 70560da7 | Fabien Chouteau | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); |
8566 | 70560da7 | Fabien Chouteau | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
8567 | 70560da7 | Fabien Chouteau | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// |
8568 | 70560da7 | Fabien Chouteau | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// |
8569 | 70560da7 | Fabien Chouteau | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// |
8570 | 70560da7 | Fabien Chouteau | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// |
8571 | 0487d6a8 | j_mayer | |
8572 | 6a6ae23f | aurel32 | /* SPE load and stores */
|
8573 | 636aa200 | Blue Swirl | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
8574 | 6a6ae23f | aurel32 | { |
8575 | 6a6ae23f | aurel32 | target_ulong uimm = rB(ctx->opcode); |
8576 | 6a6ae23f | aurel32 | |
8577 | 76db3ba4 | aurel32 | if (rA(ctx->opcode) == 0) { |
8578 | 6a6ae23f | aurel32 | tcg_gen_movi_tl(EA, uimm << sh); |
8579 | 76db3ba4 | aurel32 | } else {
|
8580 | 6a6ae23f | aurel32 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
8581 | c791fe84 | Richard Henderson | if (NARROW_MODE(ctx)) {
|
8582 | 76db3ba4 | aurel32 | tcg_gen_ext32u_tl(EA, EA); |
8583 | 76db3ba4 | aurel32 | } |
8584 | 76db3ba4 | aurel32 | } |
8585 | 0487d6a8 | j_mayer | } |
8586 | 6a6ae23f | aurel32 | |
8587 | 636aa200 | Blue Swirl | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
8588 | 6a6ae23f | aurel32 | { |
8589 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8590 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
8591 | 6a6ae23f | aurel32 | #else
|
8592 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
8593 | 76db3ba4 | aurel32 | gen_qemu_ld64(ctx, t0, addr); |
8594 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
8595 | 6a6ae23f | aurel32 | tcg_gen_shri_i64(t0, t0, 32);
|
8596 | 6a6ae23f | aurel32 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); |
8597 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
8598 | 6a6ae23f | aurel32 | #endif
|
8599 | 0487d6a8 | j_mayer | } |
8600 | 6a6ae23f | aurel32 | |
8601 | 636aa200 | Blue Swirl | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
8602 | 6a6ae23f | aurel32 | { |
8603 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
8604 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8605 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
8606 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
8607 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
8608 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
8609 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8610 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8611 | 6a6ae23f | aurel32 | #else
|
8612 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
8613 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
8614 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
8615 | 6a6ae23f | aurel32 | #endif
|
8616 | 0487d6a8 | j_mayer | } |
8617 | 6a6ae23f | aurel32 | |
8618 | 636aa200 | Blue Swirl | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
8619 | 6a6ae23f | aurel32 | { |
8620 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8621 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8622 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8623 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
8624 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8625 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8626 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
8627 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8628 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8629 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8630 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
8631 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8632 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8633 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8634 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8635 | 0487d6a8 | j_mayer | #else
|
8636 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8637 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
8638 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8639 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8640 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
8641 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8642 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8643 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
8644 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8645 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8646 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8647 | 0487d6a8 | j_mayer | #endif
|
8648 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8649 | 0487d6a8 | j_mayer | } |
8650 | 0487d6a8 | j_mayer | |
8651 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
8652 | 6a6ae23f | aurel32 | { |
8653 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8654 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8655 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8656 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
8657 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
8658 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8659 | 6a6ae23f | aurel32 | #else
|
8660 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
8661 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
8662 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
8663 | 6a6ae23f | aurel32 | #endif
|
8664 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8665 | 0487d6a8 | j_mayer | } |
8666 | 0487d6a8 | j_mayer | |
8667 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
8668 | 6a6ae23f | aurel32 | { |
8669 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8670 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8671 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8672 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
8673 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8674 | 6a6ae23f | aurel32 | #else
|
8675 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
8676 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
8677 | 6a6ae23f | aurel32 | #endif
|
8678 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8679 | 0487d6a8 | j_mayer | } |
8680 | 0487d6a8 | j_mayer | |
8681 | 636aa200 | Blue Swirl | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
8682 | 6a6ae23f | aurel32 | { |
8683 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8684 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
8685 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8686 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
8687 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(t0, t0); |
8688 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8689 | 6a6ae23f | aurel32 | #else
|
8690 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
8691 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
8692 | 6a6ae23f | aurel32 | #endif
|
8693 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8694 | 6a6ae23f | aurel32 | } |
8695 | 6a6ae23f | aurel32 | |
8696 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
8697 | 6a6ae23f | aurel32 | { |
8698 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8699 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8700 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8701 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
8702 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8703 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8704 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
8705 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8706 | 6a6ae23f | aurel32 | #else
|
8707 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8708 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
8709 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8710 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8711 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
8712 | 6a6ae23f | aurel32 | #endif
|
8713 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8714 | 6a6ae23f | aurel32 | } |
8715 | 6a6ae23f | aurel32 | |
8716 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
8717 | 6a6ae23f | aurel32 | { |
8718 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8719 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8720 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
8721 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8722 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8723 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
8724 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8725 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8726 | 6a6ae23f | aurel32 | #else
|
8727 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
8728 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8729 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
8730 | 6a6ae23f | aurel32 | #endif
|
8731 | 6a6ae23f | aurel32 | } |
8732 | 6a6ae23f | aurel32 | |
8733 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
8734 | 6a6ae23f | aurel32 | { |
8735 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8736 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8737 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
8738 | 6a6ae23f | aurel32 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
8739 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8740 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, t0, addr); |
8741 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
8742 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8743 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8744 | 6a6ae23f | aurel32 | #else
|
8745 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
8746 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8747 | 76db3ba4 | aurel32 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
8748 | 6a6ae23f | aurel32 | #endif
|
8749 | 6a6ae23f | aurel32 | } |
8750 | 6a6ae23f | aurel32 | |
8751 | 636aa200 | Blue Swirl | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
8752 | 6a6ae23f | aurel32 | { |
8753 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8754 | 76db3ba4 | aurel32 | gen_qemu_ld32u(ctx, t0, addr); |
8755 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
8756 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
|
8757 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8758 | 6a6ae23f | aurel32 | #else
|
8759 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
8760 | 6a6ae23f | aurel32 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
8761 | 6a6ae23f | aurel32 | #endif
|
8762 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8763 | 6a6ae23f | aurel32 | } |
8764 | 6a6ae23f | aurel32 | |
8765 | 636aa200 | Blue Swirl | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
8766 | 6a6ae23f | aurel32 | { |
8767 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8768 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8769 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8770 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
|
8771 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 32);
|
8772 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8773 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8774 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8775 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8776 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(t0, t0, 16);
|
8777 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
8778 | 6a6ae23f | aurel32 | #else
|
8779 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8780 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
|
8781 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
8782 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8783 | 76db3ba4 | aurel32 | gen_qemu_ld16u(ctx, t0, addr); |
8784 | 6a6ae23f | aurel32 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
|
8785 | 6a6ae23f | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
8786 | 0487d6a8 | j_mayer | #endif
|
8787 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8788 | 6a6ae23f | aurel32 | } |
8789 | 6a6ae23f | aurel32 | |
8790 | 636aa200 | Blue Swirl | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
8791 | 6a6ae23f | aurel32 | { |
8792 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8793 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
8794 | 0487d6a8 | j_mayer | #else
|
8795 | 6a6ae23f | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); |
8796 | 6a6ae23f | aurel32 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); |
8797 | 76db3ba4 | aurel32 | gen_qemu_st64(ctx, t0, addr); |
8798 | 6a6ae23f | aurel32 | tcg_temp_free_i64(t0); |
8799 | 6a6ae23f | aurel32 | #endif
|
8800 | 6a6ae23f | aurel32 | } |
8801 | 6a6ae23f | aurel32 | |
8802 | 636aa200 | Blue Swirl | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
8803 | 6a6ae23f | aurel32 | { |
8804 | 0487d6a8 | j_mayer | #if defined(TARGET_PPC64)
|
8805 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8806 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
8807 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
8808 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8809 | 6a6ae23f | aurel32 | #else
|
8810 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
8811 | 6a6ae23f | aurel32 | #endif
|
8812 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 4);
|
8813 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
8814 | 6a6ae23f | aurel32 | } |
8815 | 6a6ae23f | aurel32 | |
8816 | 636aa200 | Blue Swirl | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
8817 | 6a6ae23f | aurel32 | { |
8818 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8819 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8820 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
8821 | 6a6ae23f | aurel32 | #else
|
8822 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
8823 | 6a6ae23f | aurel32 | #endif
|
8824 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
8825 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8826 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8827 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
8828 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
8829 | 6a6ae23f | aurel32 | #else
|
8830 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
8831 | 6a6ae23f | aurel32 | #endif
|
8832 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8833 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
8834 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
8835 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8836 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8837 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
8838 | 6a6ae23f | aurel32 | } |
8839 | 6a6ae23f | aurel32 | |
8840 | 636aa200 | Blue Swirl | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
8841 | 6a6ae23f | aurel32 | { |
8842 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8843 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8844 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
|
8845 | 6a6ae23f | aurel32 | #else
|
8846 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
|
8847 | 6a6ae23f | aurel32 | #endif
|
8848 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
8849 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8850 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
|
8851 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
8852 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8853 | 6a6ae23f | aurel32 | } |
8854 | 6a6ae23f | aurel32 | |
8855 | 636aa200 | Blue Swirl | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
8856 | 6a6ae23f | aurel32 | { |
8857 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8858 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8859 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
8860 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, t0, addr); |
8861 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8862 | 6a6ae23f | aurel32 | #else
|
8863 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
8864 | 6a6ae23f | aurel32 | #endif
|
8865 | 76db3ba4 | aurel32 | gen_addr_add(ctx, addr, addr, 2);
|
8866 | 76db3ba4 | aurel32 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
8867 | 6a6ae23f | aurel32 | } |
8868 | 6a6ae23f | aurel32 | |
8869 | 636aa200 | Blue Swirl | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
8870 | 6a6ae23f | aurel32 | { |
8871 | 6a6ae23f | aurel32 | #if defined(TARGET_PPC64)
|
8872 | 6a6ae23f | aurel32 | TCGv t0 = tcg_temp_new(); |
8873 | 6a6ae23f | aurel32 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
|
8874 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, t0, addr); |
8875 | 6a6ae23f | aurel32 | tcg_temp_free(t0); |
8876 | 6a6ae23f | aurel32 | #else
|
8877 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
8878 | 6a6ae23f | aurel32 | #endif
|
8879 | 6a6ae23f | aurel32 | } |
8880 | 6a6ae23f | aurel32 | |
8881 | 636aa200 | Blue Swirl | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
8882 | 6a6ae23f | aurel32 | { |
8883 | 76db3ba4 | aurel32 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
8884 | 6a6ae23f | aurel32 | } |
8885 | 6a6ae23f | aurel32 | |
8886 | 6a6ae23f | aurel32 | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
8887 | 99e300ef | Blue Swirl | static void glue(gen_, name)(DisasContext *ctx) \ |
8888 | 6a6ae23f | aurel32 | { \ |
8889 | 6a6ae23f | aurel32 | TCGv t0; \ |
8890 | 6a6ae23f | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
8891 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
8892 | 6a6ae23f | aurel32 | return; \
|
8893 | 6a6ae23f | aurel32 | } \ |
8894 | 76db3ba4 | aurel32 | gen_set_access_type(ctx, ACCESS_INT); \ |
8895 | 6a6ae23f | aurel32 | t0 = tcg_temp_new(); \ |
8896 | 6a6ae23f | aurel32 | if (Rc(ctx->opcode)) { \
|
8897 | 76db3ba4 | aurel32 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
8898 | 6a6ae23f | aurel32 | } else { \
|
8899 | 76db3ba4 | aurel32 | gen_addr_reg_index(ctx, t0); \ |
8900 | 6a6ae23f | aurel32 | } \ |
8901 | 6a6ae23f | aurel32 | gen_op_##name(ctx, t0); \ |
8902 | 6a6ae23f | aurel32 | tcg_temp_free(t0); \ |
8903 | 6a6ae23f | aurel32 | } |
8904 | 6a6ae23f | aurel32 | |
8905 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldd, 0x00, 3); |
8906 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldw, 0x01, 3); |
8907 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evldh, 0x02, 3); |
8908 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); |
8909 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); |
8910 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); |
8911 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); |
8912 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); |
8913 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); |
8914 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); |
8915 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); |
8916 | 6a6ae23f | aurel32 | |
8917 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdd, 0x10, 3); |
8918 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdw, 0x11, 3); |
8919 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstdh, 0x12, 3); |
8920 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); |
8921 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); |
8922 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); |
8923 | 6a6ae23f | aurel32 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); |
8924 | 0487d6a8 | j_mayer | |
8925 | 0487d6a8 | j_mayer | /* Multiply and add - TODO */
|
8926 | 0487d6a8 | j_mayer | #if 0
|
8927 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
|
8928 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8929 | 70560da7 | Fabien Chouteau | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
|
8930 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8931 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
|
8932 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8933 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8934 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8935 | 70560da7 | Fabien Chouteau | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
|
8936 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8937 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
|
8938 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8939 | 70560da7 | Fabien Chouteau | |
8940 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8941 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
|
8942 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
|
8943 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8944 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8945 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8946 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8947 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
|
8948 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
|
8949 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8950 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8951 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8952 | 70560da7 | Fabien Chouteau | |
8953 | 70560da7 | Fabien Chouteau | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
|
8954 | 70560da7 | Fabien Chouteau | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
|
8955 | 70560da7 | Fabien Chouteau | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
|
8956 | 70560da7 | Fabien Chouteau | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
|
8957 | 70560da7 | Fabien Chouteau | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
|
8958 | 70560da7 | Fabien Chouteau | |
8959 | 70560da7 | Fabien Chouteau | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
|
8960 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8961 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
|
8962 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8963 | 70560da7 | Fabien Chouteau | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
|
8964 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8965 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
|
8966 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8967 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
|
8968 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8969 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
|
8970 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8971 | 70560da7 | Fabien Chouteau | |
8972 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
|
8973 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
|
8974 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8975 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8976 | 70560da7 | Fabien Chouteau | |
8977 | 70560da7 | Fabien Chouteau | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
|
8978 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8979 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
|
8980 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8981 | 70560da7 | Fabien Chouteau | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
|
8982 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8983 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
|
8984 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8985 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
|
8986 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8987 | 70560da7 | Fabien Chouteau | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
|
8988 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8989 | 70560da7 | Fabien Chouteau | |
8990 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
|
8991 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
|
8992 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8993 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
|
8994 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
|
8995 | 0487d6a8 | j_mayer | #endif
|
8996 | 0487d6a8 | j_mayer | |
8997 | 0487d6a8 | j_mayer | /*** SPE floating-point extension ***/
|
8998 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
8999 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
9000 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9001 | 0487d6a8 | j_mayer | { \ |
9002 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
9003 | 1c97856d | aurel32 | TCGv t1; \ |
9004 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
9005 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
9006 | 8e703949 | Blue Swirl | gen_helper_##name(t0, cpu_env, t0); \ |
9007 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
9008 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
9009 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
9010 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
9011 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
9012 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
9013 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
9014 | 0487d6a8 | j_mayer | } |
9015 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
9016 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9017 | 1c97856d | aurel32 | { \ |
9018 | 1c97856d | aurel32 | TCGv_i32 t0; \ |
9019 | 1c97856d | aurel32 | TCGv t1; \ |
9020 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
9021 | 8e703949 | Blue Swirl | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
9022 | 1c97856d | aurel32 | t1 = tcg_temp_new(); \ |
9023 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t1, t0); \ |
9024 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
9025 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
9026 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
9027 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ |
9028 | 1c97856d | aurel32 | tcg_temp_free(t1); \ |
9029 | 1c97856d | aurel32 | } |
9030 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
9031 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9032 | 1c97856d | aurel32 | { \ |
9033 | 1c97856d | aurel32 | TCGv_i32 t0 = tcg_temp_new_i32(); \ |
9034 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
9035 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
9036 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
9037 | 1c97856d | aurel32 | } |
9038 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
9039 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9040 | 1c97856d | aurel32 | { \ |
9041 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
9042 | 8e703949 | Blue Swirl | cpu_gpr[rB(ctx->opcode)]); \ |
9043 | 1c97856d | aurel32 | } |
9044 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
9045 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9046 | 57951c27 | aurel32 | { \ |
9047 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
9048 | 1c97856d | aurel32 | TCGv_i64 t2; \ |
9049 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9050 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9051 | 57951c27 | aurel32 | return; \
|
9052 | 57951c27 | aurel32 | } \ |
9053 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
9054 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
9055 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
9056 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
9057 | 8e703949 | Blue Swirl | gen_helper_##name(t0, cpu_env, t0, t1); \ |
9058 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
9059 | 1c97856d | aurel32 | t2 = tcg_temp_new(); \ |
9060 | 1c97856d | aurel32 | tcg_gen_extu_i32_tl(t2, t0); \ |
9061 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
9062 | 1c97856d | aurel32 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ |
9063 | 1c97856d | aurel32 | 0xFFFFFFFF00000000ULL); \
|
9064 | 1c97856d | aurel32 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ |
9065 | 1c97856d | aurel32 | tcg_temp_free(t2); \ |
9066 | 57951c27 | aurel32 | } |
9067 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
9068 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9069 | 57951c27 | aurel32 | { \ |
9070 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9071 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9072 | 57951c27 | aurel32 | return; \
|
9073 | 57951c27 | aurel32 | } \ |
9074 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
9075 | 8e703949 | Blue Swirl | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
9076 | 57951c27 | aurel32 | } |
9077 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
9078 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9079 | 57951c27 | aurel32 | { \ |
9080 | 1c97856d | aurel32 | TCGv_i32 t0, t1; \ |
9081 | 57951c27 | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9082 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9083 | 57951c27 | aurel32 | return; \
|
9084 | 57951c27 | aurel32 | } \ |
9085 | 1c97856d | aurel32 | t0 = tcg_temp_new_i32(); \ |
9086 | 1c97856d | aurel32 | t1 = tcg_temp_new_i32(); \ |
9087 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
9088 | 1c97856d | aurel32 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ |
9089 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
9090 | 1c97856d | aurel32 | tcg_temp_free_i32(t0); \ |
9091 | 1c97856d | aurel32 | tcg_temp_free_i32(t1); \ |
9092 | 1c97856d | aurel32 | } |
9093 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
9094 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9095 | 1c97856d | aurel32 | { \ |
9096 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9097 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9098 | 1c97856d | aurel32 | return; \
|
9099 | 1c97856d | aurel32 | } \ |
9100 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
9101 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
9102 | 1c97856d | aurel32 | } |
9103 | 1c97856d | aurel32 | #else
|
9104 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_32(name) \
|
9105 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9106 | 1c97856d | aurel32 | { \ |
9107 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
9108 | 8e703949 | Blue Swirl | cpu_gpr[rB(ctx->opcode)]); \ |
9109 | 57951c27 | aurel32 | } |
9110 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_32_64(name) \
|
9111 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9112 | 1c97856d | aurel32 | { \ |
9113 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
9114 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
9115 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \ |
9116 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
9117 | 1c97856d | aurel32 | } |
9118 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_32(name) \
|
9119 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9120 | 1c97856d | aurel32 | { \ |
9121 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
9122 | 8e703949 | Blue Swirl | gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \ |
9123 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9124 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
9125 | 1c97856d | aurel32 | } |
9126 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_CONV_64_64(name) \
|
9127 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9128 | 1c97856d | aurel32 | { \ |
9129 | 1c97856d | aurel32 | TCGv_i64 t0 = tcg_temp_new_i64(); \ |
9130 | 1c97856d | aurel32 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
9131 | 8e703949 | Blue Swirl | gen_helper_##name(t0, cpu_env, t0); \ |
9132 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9133 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
9134 | 1c97856d | aurel32 | } |
9135 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \
|
9136 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9137 | 1c97856d | aurel32 | { \ |
9138 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9139 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9140 | 1c97856d | aurel32 | return; \
|
9141 | 1c97856d | aurel32 | } \ |
9142 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
9143 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
9144 | 1c97856d | aurel32 | } |
9145 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \
|
9146 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9147 | 1c97856d | aurel32 | { \ |
9148 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
9149 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9150 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9151 | 1c97856d | aurel32 | return; \
|
9152 | 1c97856d | aurel32 | } \ |
9153 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
9154 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
9155 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
9156 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
9157 | 8e703949 | Blue Swirl | gen_helper_##name(t0, cpu_env, t0, t1); \ |
9158 | 1c97856d | aurel32 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9159 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
9160 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
9161 | 1c97856d | aurel32 | } |
9162 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_32(name) \
|
9163 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9164 | 1c97856d | aurel32 | { \ |
9165 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9166 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9167 | 1c97856d | aurel32 | return; \
|
9168 | 1c97856d | aurel32 | } \ |
9169 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \ |
9170 | 1c97856d | aurel32 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
9171 | 1c97856d | aurel32 | } |
9172 | 1c97856d | aurel32 | #define GEN_SPEFPUOP_COMP_64(name) \
|
9173 | 636aa200 | Blue Swirl | static inline void gen_##name(DisasContext *ctx) \ |
9174 | 1c97856d | aurel32 | { \ |
9175 | 1c97856d | aurel32 | TCGv_i64 t0, t1; \ |
9176 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) { \
|
9177 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
9178 | 1c97856d | aurel32 | return; \
|
9179 | 1c97856d | aurel32 | } \ |
9180 | 1c97856d | aurel32 | t0 = tcg_temp_new_i64(); \ |
9181 | 1c97856d | aurel32 | t1 = tcg_temp_new_i64(); \ |
9182 | 1c97856d | aurel32 | gen_load_gpr64(t0, rA(ctx->opcode)); \ |
9183 | 1c97856d | aurel32 | gen_load_gpr64(t1, rB(ctx->opcode)); \ |
9184 | 8e703949 | Blue Swirl | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
9185 | 1c97856d | aurel32 | tcg_temp_free_i64(t0); \ |
9186 | 1c97856d | aurel32 | tcg_temp_free_i64(t1); \ |
9187 | 1c97856d | aurel32 | } |
9188 | 1c97856d | aurel32 | #endif
|
9189 | 57951c27 | aurel32 | |
9190 | 0487d6a8 | j_mayer | /* Single precision floating-point vectors operations */
|
9191 | 0487d6a8 | j_mayer | /* Arithmetic */
|
9192 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
9193 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); |
9194 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); |
9195 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); |
9196 | 636aa200 | Blue Swirl | static inline void gen_evfsabs(DisasContext *ctx) |
9197 | 1c97856d | aurel32 | { |
9198 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9199 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9200 | 1c97856d | aurel32 | return;
|
9201 | 1c97856d | aurel32 | } |
9202 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
9203 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
|
9204 | 1c97856d | aurel32 | #else
|
9205 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
|
9206 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
9207 | 1c97856d | aurel32 | #endif
|
9208 | 1c97856d | aurel32 | } |
9209 | 636aa200 | Blue Swirl | static inline void gen_evfsnabs(DisasContext *ctx) |
9210 | 1c97856d | aurel32 | { |
9211 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9212 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9213 | 1c97856d | aurel32 | return;
|
9214 | 1c97856d | aurel32 | } |
9215 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
9216 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
9217 | 1c97856d | aurel32 | #else
|
9218 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
9219 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
9220 | 1c97856d | aurel32 | #endif
|
9221 | 1c97856d | aurel32 | } |
9222 | 636aa200 | Blue Swirl | static inline void gen_evfsneg(DisasContext *ctx) |
9223 | 1c97856d | aurel32 | { |
9224 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9225 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9226 | 1c97856d | aurel32 | return;
|
9227 | 1c97856d | aurel32 | } |
9228 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
9229 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
|
9230 | 1c97856d | aurel32 | #else
|
9231 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
9232 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
9233 | 1c97856d | aurel32 | #endif
|
9234 | 1c97856d | aurel32 | } |
9235 | 1c97856d | aurel32 | |
9236 | 0487d6a8 | j_mayer | /* Conversion */
|
9237 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
9238 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); |
9239 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); |
9240 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); |
9241 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctui); |
9242 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); |
9243 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); |
9244 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); |
9245 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); |
9246 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); |
9247 | 1c97856d | aurel32 | |
9248 | 0487d6a8 | j_mayer | /* Comparison */
|
9249 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
9250 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmplt); |
9251 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfscmpeq); |
9252 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststgt); |
9253 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststlt); |
9254 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(evfststeq); |
9255 | 0487d6a8 | j_mayer | |
9256 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
9257 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9258 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // |
9259 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9260 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9261 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
9262 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9263 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9264 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9265 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9266 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9267 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9268 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9269 | 70560da7 | Fabien Chouteau | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
9270 | 70560da7 | Fabien Chouteau | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9271 | 0487d6a8 | j_mayer | |
9272 | 0487d6a8 | j_mayer | /* Single precision floating-point operations */
|
9273 | 0487d6a8 | j_mayer | /* Arithmetic */
|
9274 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
9275 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efssub); |
9276 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); |
9277 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); |
9278 | 636aa200 | Blue Swirl | static inline void gen_efsabs(DisasContext *ctx) |
9279 | 1c97856d | aurel32 | { |
9280 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9281 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9282 | 1c97856d | aurel32 | return;
|
9283 | 1c97856d | aurel32 | } |
9284 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
|
9285 | 1c97856d | aurel32 | } |
9286 | 636aa200 | Blue Swirl | static inline void gen_efsnabs(DisasContext *ctx) |
9287 | 1c97856d | aurel32 | { |
9288 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9289 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9290 | 1c97856d | aurel32 | return;
|
9291 | 1c97856d | aurel32 | } |
9292 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
9293 | 1c97856d | aurel32 | } |
9294 | 636aa200 | Blue Swirl | static inline void gen_efsneg(DisasContext *ctx) |
9295 | 1c97856d | aurel32 | { |
9296 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9297 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9298 | 1c97856d | aurel32 | return;
|
9299 | 1c97856d | aurel32 | } |
9300 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
|
9301 | 1c97856d | aurel32 | } |
9302 | 1c97856d | aurel32 | |
9303 | 0487d6a8 | j_mayer | /* Conversion */
|
9304 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
9305 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsi); |
9306 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfuf); |
9307 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efscfsf); |
9308 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctui); |
9309 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsi); |
9310 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuf); |
9311 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsf); |
9312 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); |
9313 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); |
9314 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efscfd); |
9315 | 1c97856d | aurel32 | |
9316 | 0487d6a8 | j_mayer | /* Comparison */
|
9317 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
9318 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmplt); |
9319 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efscmpeq); |
9320 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststgt); |
9321 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststlt); |
9322 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_32(efststeq); |
9323 | 0487d6a8 | j_mayer | |
9324 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
9325 | 70560da7 | Fabien Chouteau | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9326 | 70560da7 | Fabien Chouteau | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // |
9327 | 70560da7 | Fabien Chouteau | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9328 | 70560da7 | Fabien Chouteau | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9329 | 70560da7 | Fabien Chouteau | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
9330 | 70560da7 | Fabien Chouteau | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // |
9331 | 70560da7 | Fabien Chouteau | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9332 | 70560da7 | Fabien Chouteau | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9333 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9334 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // |
9335 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9336 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9337 | 70560da7 | Fabien Chouteau | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // |
9338 | 70560da7 | Fabien Chouteau | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // |
9339 | 0487d6a8 | j_mayer | |
9340 | 0487d6a8 | j_mayer | /* Double precision floating-point operations */
|
9341 | 0487d6a8 | j_mayer | /* Arithmetic */
|
9342 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
9343 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); |
9344 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); |
9345 | 1c97856d | aurel32 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); |
9346 | 636aa200 | Blue Swirl | static inline void gen_efdabs(DisasContext *ctx) |
9347 | 1c97856d | aurel32 | { |
9348 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9349 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9350 | 1c97856d | aurel32 | return;
|
9351 | 1c97856d | aurel32 | } |
9352 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
9353 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
|
9354 | 1c97856d | aurel32 | #else
|
9355 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9356 | 6d5c34fa | Mike Pall | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
|
9357 | 1c97856d | aurel32 | #endif
|
9358 | 1c97856d | aurel32 | } |
9359 | 636aa200 | Blue Swirl | static inline void gen_efdnabs(DisasContext *ctx) |
9360 | 1c97856d | aurel32 | { |
9361 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9362 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9363 | 1c97856d | aurel32 | return;
|
9364 | 1c97856d | aurel32 | } |
9365 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
9366 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
9367 | 1c97856d | aurel32 | #else
|
9368 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9369 | 6d5c34fa | Mike Pall | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
9370 | 1c97856d | aurel32 | #endif
|
9371 | 1c97856d | aurel32 | } |
9372 | 636aa200 | Blue Swirl | static inline void gen_efdneg(DisasContext *ctx) |
9373 | 1c97856d | aurel32 | { |
9374 | 1c97856d | aurel32 | if (unlikely(!ctx->spe_enabled)) {
|
9375 | 27a69bb0 | Alexander Graf | gen_exception(ctx, POWERPC_EXCP_SPEU); |
9376 | 1c97856d | aurel32 | return;
|
9377 | 1c97856d | aurel32 | } |
9378 | 1c97856d | aurel32 | #if defined(TARGET_PPC64)
|
9379 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
|
9380 | 1c97856d | aurel32 | #else
|
9381 | 6d5c34fa | Mike Pall | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9382 | 6d5c34fa | Mike Pall | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
|
9383 | 1c97856d | aurel32 | #endif
|
9384 | 1c97856d | aurel32 | } |
9385 | 1c97856d | aurel32 | |
9386 | 0487d6a8 | j_mayer | /* Conversion */
|
9387 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
9388 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); |
9389 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); |
9390 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); |
9391 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctui); |
9392 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsi); |
9393 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuf); |
9394 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsf); |
9395 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); |
9396 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); |
9397 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_32(efdcfs); |
9398 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); |
9399 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); |
9400 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); |
9401 | 1c97856d | aurel32 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); |
9402 | 0487d6a8 | j_mayer | |
9403 | 0487d6a8 | j_mayer | /* Comparison */
|
9404 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
9405 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmplt); |
9406 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdcmpeq); |
9407 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstgt); |
9408 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtstlt); |
9409 | 1c97856d | aurel32 | GEN_SPEFPUOP_COMP_64(efdtsteq); |
9410 | 0487d6a8 | j_mayer | |
9411 | 0487d6a8 | j_mayer | /* Opcodes definitions */
|
9412 | 70560da7 | Fabien Chouteau | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
9413 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
9414 | 70560da7 | Fabien Chouteau | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // |
9415 | 70560da7 | Fabien Chouteau | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
9416 | 70560da7 | Fabien Chouteau | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
9417 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
9418 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // |
9419 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // |
9420 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
9421 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
9422 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
9423 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // |
9424 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
9425 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
9426 | 70560da7 | Fabien Chouteau | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // |
9427 | 70560da7 | Fabien Chouteau | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // |
9428 | 0487d6a8 | j_mayer | |
9429 | c227f099 | Anthony Liguori | static opcode_t opcodes[] = {
|
9430 | 5c55ff99 | Blue Swirl | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
9431 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
9432 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
9433 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), |
9434 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
9435 | fcfda20f | Aurelien Jarno | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
9436 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
9437 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9438 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9439 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9440 | 5c55ff99 | Blue Swirl | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9441 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
9442 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), |
9443 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), |
9444 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), |
9445 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9446 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9447 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), |
9448 | 5c55ff99 | Blue Swirl | #endif
|
9449 | 5c55ff99 | Blue Swirl | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), |
9450 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), |
9451 | 5c55ff99 | Blue Swirl | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9452 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9453 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9454 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), |
9455 | 5c55ff99 | Blue Swirl | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
9456 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), |
9457 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9458 | 5c55ff99 | Blue Swirl | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9459 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9460 | 5c55ff99 | Blue Swirl | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9461 | 5c55ff99 | Blue Swirl | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB), |
9462 | eaabeef2 | David Gibson | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
9463 | 725bcec2 | Aurelien Jarno | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
9464 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9465 | eaabeef2 | David Gibson | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
9466 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
9467 | 725bcec2 | Aurelien Jarno | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
9468 | 86ba37ed | Tom Musta | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
9469 | 5c55ff99 | Blue Swirl | #endif
|
9470 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9471 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9472 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9473 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), |
9474 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), |
9475 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), |
9476 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), |
9477 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9478 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), |
9479 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), |
9480 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), |
9481 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), |
9482 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), |
9483 | 5c55ff99 | Blue Swirl | #endif
|
9484 | 5c55ff99 | Blue Swirl | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), |
9485 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
9486 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), |
9487 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), |
9488 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), |
9489 | bf45a2e6 | Aurelien Jarno | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
9490 | 5c55ff99 | Blue Swirl | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
9491 | bf45a2e6 | Aurelien Jarno | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
9492 | bf45a2e6 | Aurelien Jarno | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), |
9493 | f0332888 | Aurelien Jarno | GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), |
9494 | 097ec5d8 | Tom Musta | GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), |
9495 | 097ec5d8 | Tom Musta | GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), |
9496 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
9497 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), |
9498 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), |
9499 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), |
9500 | 7d08d856 | Aurelien Jarno | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), |
9501 | 7d08d856 | Aurelien Jarno | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), |
9502 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9503 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), |
9504 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), |
9505 | 5c55ff99 | Blue Swirl | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), |
9506 | 5c55ff99 | Blue Swirl | #endif
|
9507 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9508 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
9509 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), |
9510 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), |
9511 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), |
9512 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), |
9513 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), |
9514 | 5c55ff99 | Blue Swirl | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
9515 | 5c77a786 | Tom Musta | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9516 | 5c77a786 | Tom Musta | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9517 | f844c817 | Alexander Graf | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
9518 | 587c51f7 | Tom Musta | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9519 | 587c51f7 | Tom Musta | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9520 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
9521 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9522 | f844c817 | Alexander Graf | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9523 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
9524 | 5c55ff99 | Blue Swirl | #endif
|
9525 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), |
9526 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), |
9527 | 5c55ff99 | Blue Swirl | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
9528 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
9529 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), |
9530 | 5c55ff99 | Blue Swirl | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), |
9531 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
9532 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), |
9533 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9534 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), |
9535 | 5c55ff99 | Blue Swirl | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
9536 | 5c55ff99 | Blue Swirl | #endif
|
9537 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), |
9538 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
9539 | 5c55ff99 | Blue Swirl | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
9540 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9541 | 5c55ff99 | Blue Swirl | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), |
9542 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), |
9543 | 5c55ff99 | Blue Swirl | #endif
|
9544 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), |
9545 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), |
9546 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), |
9547 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), |
9548 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), |
9549 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), |
9550 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9551 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), |
9552 | 5c55ff99 | Blue Swirl | #endif
|
9553 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), |
9554 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), |
9555 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
9556 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
9557 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |
9558 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), |
9559 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), |
9560 | 8e33944f | Alexander Graf | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
9561 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
9562 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), |
9563 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
9564 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), |
9565 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
9566 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), |
9567 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), |
9568 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), |
9569 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), |
9570 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9571 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), |
9572 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, |
9573 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
9574 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), |
9575 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, |
9576 | 5c55ff99 | Blue Swirl | PPC_SEGMENT_64B), |
9577 | efdef95f | David Gibson | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
9578 | efdef95f | David Gibson | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), |
9579 | efdef95f | David Gibson | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), |
9580 | 5c55ff99 | Blue Swirl | #endif
|
9581 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), |
9582 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), |
9583 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), |
9584 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
9585 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9586 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), |
9587 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
9588 | 5c55ff99 | Blue Swirl | #endif
|
9589 | 5c55ff99 | Blue Swirl | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
9590 | 5c55ff99 | Blue Swirl | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), |
9591 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), |
9592 | 5c55ff99 | Blue Swirl | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), |
9593 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), |
9594 | 5c55ff99 | Blue Swirl | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), |
9595 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), |
9596 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), |
9597 | 5c55ff99 | Blue Swirl | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), |
9598 | 5c55ff99 | Blue Swirl | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), |
9599 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), |
9600 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
9601 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), |
9602 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), |
9603 | 5c55ff99 | Blue Swirl | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), |
9604 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), |
9605 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), |
9606 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), |
9607 | 5c55ff99 | Blue Swirl | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), |
9608 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
9609 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), |
9610 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), |
9611 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), |
9612 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), |
9613 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), |
9614 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), |
9615 | 5c55ff99 | Blue Swirl | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), |
9616 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), |
9617 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), |
9618 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), |
9619 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), |
9620 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), |
9621 | 5c55ff99 | Blue Swirl | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), |
9622 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), |
9623 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), |
9624 | 5c55ff99 | Blue Swirl | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), |
9625 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), |
9626 | 5c55ff99 | Blue Swirl | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), |
9627 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), |
9628 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
9629 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), |
9630 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), |
9631 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), |
9632 | 5c55ff99 | Blue Swirl | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), |
9633 | 5c55ff99 | Blue Swirl | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), |
9634 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), |
9635 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), |
9636 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), |
9637 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), |
9638 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
9639 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
9640 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), |
9641 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), |
9642 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
9643 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
9644 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), |
9645 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), |
9646 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
9647 | 5c55ff99 | Blue Swirl | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), |
9648 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), |
9649 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), |
9650 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), |
9651 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), |
9652 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), |
9653 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), |
9654 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
9655 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), |
9656 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), |
9657 | 5c55ff99 | Blue Swirl | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), |
9658 | 5c55ff99 | Blue Swirl | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), |
9659 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), |
9660 | 01662f3e | Alexander Graf | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
9661 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
9662 | 5c55ff99 | Blue Swirl | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), |
9663 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), |
9664 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), |
9665 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), |
9666 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), |
9667 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), |
9668 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), |
9669 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
9670 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
9671 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, |
9672 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
9673 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, |
9674 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
9675 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, |
9676 | 01662f3e | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
9677 | 6d3db821 | Alexander Graf | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
9678 | 6d3db821 | Alexander Graf | PPC_NONE, PPC2_BOOKE206), |
9679 | d5d11a39 | Alexander Graf | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
9680 | d5d11a39 | Alexander Graf | PPC_NONE, PPC2_PRCNTL), |
9681 | 9e0b5cb1 | Alexander Graf | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
9682 | 9e0b5cb1 | Alexander Graf | PPC_NONE, PPC2_PRCNTL), |
9683 | 5c55ff99 | Blue Swirl | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
9684 | fbe73008 | Baojun Wang | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
9685 | 5c55ff99 | Blue Swirl | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
9686 | 01662f3e | Alexander Graf | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
9687 | 01662f3e | Alexander Graf | PPC_BOOKE, PPC2_BOOKE206), |
9688 | dcb2b9e1 | Alexander Graf | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
9689 | 01662f3e | Alexander Graf | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
9690 | 01662f3e | Alexander Graf | PPC_BOOKE, PPC2_BOOKE206), |
9691 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
9692 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), |
9693 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), |
9694 | 5c55ff99 | Blue Swirl | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), |
9695 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), |
9696 | 5c55ff99 | Blue Swirl | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
9697 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), |
9698 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), |
9699 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), |
9700 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), |
9701 | 5c55ff99 | Blue Swirl | |
9702 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD
|
9703 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_ADD_CONST
|
9704 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
|
9705 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), |
9706 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
|
9707 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
9708 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), |
9709 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
9710 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
9711 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
9712 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
9713 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
9714 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
9715 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
9716 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
9717 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
9718 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
9719 | 5c55ff99 | Blue Swirl | |
9720 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVW
|
9721 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
|
9722 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) |
9723 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), |
9724 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), |
9725 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), |
9726 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), |
9727 | a98eb9e9 | Tom Musta | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9728 | a98eb9e9 | Tom Musta | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9729 | 6a4fda33 | Tom Musta | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9730 | 6a4fda33 | Tom Musta | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9731 | 5c55ff99 | Blue Swirl | |
9732 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9733 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_DIVD
|
9734 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
|
9735 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
9736 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), |
9737 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), |
9738 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), |
9739 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), |
9740 | 5c55ff99 | Blue Swirl | |
9741 | 98d1eb27 | Tom Musta | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9742 | 98d1eb27 | Tom Musta | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9743 | e44259b6 | Tom Musta | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9744 | e44259b6 | Tom Musta | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9745 | 98d1eb27 | Tom Musta | |
9746 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_MUL_HELPER
|
9747 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
|
9748 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
9749 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
|
9750 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
|
9751 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
|
9752 | 5c55ff99 | Blue Swirl | #endif
|
9753 | 5c55ff99 | Blue Swirl | |
9754 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF
|
9755 | 5c55ff99 | Blue Swirl | #undef GEN_INT_ARITH_SUBF_CONST
|
9756 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
|
9757 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), |
9758 | 5c55ff99 | Blue Swirl | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
|
9759 | 5c55ff99 | Blue Swirl | add_ca, compute_ca, compute_ov) \ |
9760 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), |
9761 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
9762 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
9763 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
9764 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
9765 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
9766 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
9767 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
9768 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
9769 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
9770 | 5c55ff99 | Blue Swirl | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
9771 | 5c55ff99 | Blue Swirl | |
9772 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL1
|
9773 | 5c55ff99 | Blue Swirl | #undef GEN_LOGICAL2
|
9774 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL2(name, tcg_op, opc, type) \
|
9775 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) |
9776 | 5c55ff99 | Blue Swirl | #define GEN_LOGICAL1(name, tcg_op, opc, type) \
|
9777 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) |
9778 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
|
9779 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
|
9780 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
|
9781 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
|
9782 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
|
9783 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
|
9784 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
|
9785 | 5c55ff99 | Blue Swirl | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
|
9786 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9787 | 5c55ff99 | Blue Swirl | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
|
9788 | 5c55ff99 | Blue Swirl | #endif
|
9789 | 5c55ff99 | Blue Swirl | |
9790 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9791 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R2
|
9792 | 5c55ff99 | Blue Swirl | #undef GEN_PPC64_R4
|
9793 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R2(name, opc1, opc2) \
|
9794 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
9795 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
9796 | 5c55ff99 | Blue Swirl | PPC_64B) |
9797 | 5c55ff99 | Blue Swirl | #define GEN_PPC64_R4(name, opc1, opc2) \
|
9798 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
9799 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
9800 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
9801 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
9802 | 5c55ff99 | Blue Swirl | PPC_64B), \ |
9803 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
9804 | 5c55ff99 | Blue Swirl | PPC_64B) |
9805 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicl, 0x1E, 0x00), |
9806 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldicr, 0x1E, 0x02), |
9807 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldic, 0x1E, 0x04), |
9808 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcl, 0x1E, 0x08), |
9809 | 5c55ff99 | Blue Swirl | GEN_PPC64_R2(rldcr, 0x1E, 0x09), |
9810 | 5c55ff99 | Blue Swirl | GEN_PPC64_R4(rldimi, 0x1E, 0x06), |
9811 | 5c55ff99 | Blue Swirl | #endif
|
9812 | 5c55ff99 | Blue Swirl | |
9813 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_ACB
|
9814 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_ACB
|
9815 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AB
|
9816 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AB
|
9817 | 5c55ff99 | Blue Swirl | #undef _GEN_FLOAT_AC
|
9818 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_AC
|
9819 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_B
|
9820 | 5c55ff99 | Blue Swirl | #undef GEN_FLOAT_BS
|
9821 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
|
9822 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) |
9823 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
|
9824 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ |
9825 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) |
9826 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
9827 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
9828 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
|
9829 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
9830 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
9831 | 5c55ff99 | Blue Swirl | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
|
9832 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) |
9833 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
|
9834 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ |
9835 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) |
9836 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
|
9837 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) |
9838 | 5c55ff99 | Blue Swirl | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
|
9839 | 5c55ff99 | Blue Swirl | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) |
9840 | 5c55ff99 | Blue Swirl | |
9841 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), |
9842 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), |
9843 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), |
9844 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), |
9845 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), |
9846 | 5c55ff99 | Blue Swirl | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), |
9847 | 5c55ff99 | Blue Swirl | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), |
9848 | 5c55ff99 | Blue Swirl | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), |
9849 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), |
9850 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), |
9851 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), |
9852 | 5c55ff99 | Blue Swirl | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), |
9853 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
9854 | fab7fe42 | Tom Musta | GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
9855 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
9856 | fab7fe42 | Tom Musta | GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
9857 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
9858 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9859 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), |
9860 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
9861 | fab7fe42 | Tom Musta | GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
9862 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
9863 | fab7fe42 | Tom Musta | GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
9864 | 5c55ff99 | Blue Swirl | #endif
|
9865 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), |
9866 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), |
9867 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), |
9868 | 5c55ff99 | Blue Swirl | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), |
9869 | 5c55ff99 | Blue Swirl | |
9870 | 5c55ff99 | Blue Swirl | #undef GEN_LD
|
9871 | 5c55ff99 | Blue Swirl | #undef GEN_LDU
|
9872 | 5c55ff99 | Blue Swirl | #undef GEN_LDUX
|
9873 | cd6e9320 | Thomas Huth | #undef GEN_LDX_E
|
9874 | 5c55ff99 | Blue Swirl | #undef GEN_LDS
|
9875 | 5c55ff99 | Blue Swirl | #define GEN_LD(name, ldop, opc, type) \
|
9876 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
9877 | 5c55ff99 | Blue Swirl | #define GEN_LDU(name, ldop, opc, type) \
|
9878 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
9879 | 5c55ff99 | Blue Swirl | #define GEN_LDUX(name, ldop, opc2, opc3, type) \
|
9880 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
9881 | cd6e9320 | Thomas Huth | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
|
9882 | cd6e9320 | Thomas Huth | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
9883 | 5c55ff99 | Blue Swirl | #define GEN_LDS(name, ldop, op, type) \
|
9884 | 5c55ff99 | Blue Swirl | GEN_LD(name, ldop, op | 0x20, type) \
|
9885 | 5c55ff99 | Blue Swirl | GEN_LDU(name, ldop, op | 0x21, type) \
|
9886 | 5c55ff99 | Blue Swirl | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ |
9887 | 5c55ff99 | Blue Swirl | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
9888 | 5c55ff99 | Blue Swirl | |
9889 | 5c55ff99 | Blue Swirl | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
|
9890 | 5c55ff99 | Blue Swirl | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
|
9891 | 5c55ff99 | Blue Swirl | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
|
9892 | 5c55ff99 | Blue Swirl | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
|
9893 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9894 | 5c55ff99 | Blue Swirl | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) |
9895 | 5c55ff99 | Blue Swirl | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) |
9896 | 5c55ff99 | Blue Swirl | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) |
9897 | 5c55ff99 | Blue Swirl | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) |
9898 | cd6e9320 | Thomas Huth | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
9899 | 5c55ff99 | Blue Swirl | #endif
|
9900 | 5c55ff99 | Blue Swirl | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) |
9901 | 5c55ff99 | Blue Swirl | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) |
9902 | 5c55ff99 | Blue Swirl | |
9903 | 5c55ff99 | Blue Swirl | #undef GEN_ST
|
9904 | 5c55ff99 | Blue Swirl | #undef GEN_STU
|
9905 | 5c55ff99 | Blue Swirl | #undef GEN_STUX
|
9906 | cd6e9320 | Thomas Huth | #undef GEN_STX_E
|
9907 | 5c55ff99 | Blue Swirl | #undef GEN_STS
|
9908 | 5c55ff99 | Blue Swirl | #define GEN_ST(name, stop, opc, type) \
|
9909 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
9910 | 5c55ff99 | Blue Swirl | #define GEN_STU(name, stop, opc, type) \
|
9911 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), |
9912 | 5c55ff99 | Blue Swirl | #define GEN_STUX(name, stop, opc2, opc3, type) \
|
9913 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
9914 | cd6e9320 | Thomas Huth | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
|
9915 | cd6e9320 | Thomas Huth | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
9916 | 5c55ff99 | Blue Swirl | #define GEN_STS(name, stop, op, type) \
|
9917 | 5c55ff99 | Blue Swirl | GEN_ST(name, stop, op | 0x20, type) \
|
9918 | 5c55ff99 | Blue Swirl | GEN_STU(name, stop, op | 0x21, type) \
|
9919 | 5c55ff99 | Blue Swirl | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ |
9920 | 5c55ff99 | Blue Swirl | GEN_STX(name, stop, 0x17, op | 0x00, type) |
9921 | 5c55ff99 | Blue Swirl | |
9922 | 5c55ff99 | Blue Swirl | GEN_STS(stb, st8, 0x06, PPC_INTEGER)
|
9923 | 5c55ff99 | Blue Swirl | GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
|
9924 | 5c55ff99 | Blue Swirl | GEN_STS(stw, st32, 0x04, PPC_INTEGER)
|
9925 | 5c55ff99 | Blue Swirl | #if defined(TARGET_PPC64)
|
9926 | 5c55ff99 | Blue Swirl | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) |
9927 | 5c55ff99 | Blue Swirl | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) |
9928 | cd6e9320 | Thomas Huth | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
9929 | 5c55ff99 | Blue Swirl | #endif
|
9930 | 5c55ff99 | Blue Swirl | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) |
9931 | 5c55ff99 | Blue Swirl | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) |
9932 | 5c55ff99 | Blue Swirl | |
9933 | 5c55ff99 | Blue Swirl | #undef GEN_LDF
|
9934 | 5c55ff99 | Blue Swirl | #undef GEN_LDUF
|
9935 | 5c55ff99 | Blue Swirl | #undef GEN_LDUXF
|
9936 | 5c55ff99 | Blue Swirl | #undef GEN_LDXF
|
9937 | 5c55ff99 | Blue Swirl | #undef GEN_LDFS
|
9938 | 5c55ff99 | Blue Swirl | #define GEN_LDF(name, ldop, opc, type) \
|
9939 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
9940 | 5c55ff99 | Blue Swirl | #define GEN_LDUF(name, ldop, opc, type) \
|
9941 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
9942 | 5c55ff99 | Blue Swirl | #define GEN_LDUXF(name, ldop, opc, type) \
|
9943 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
9944 | 5c55ff99 | Blue Swirl | #define GEN_LDXF(name, ldop, opc2, opc3, type) \
|
9945 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
9946 | 5c55ff99 | Blue Swirl | #define GEN_LDFS(name, ldop, op, type) \
|
9947 | 5c55ff99 | Blue Swirl | GEN_LDF(name, ldop, op | 0x20, type) \
|
9948 | 5c55ff99 | Blue Swirl | GEN_LDUF(name, ldop, op | 0x21, type) \
|
9949 | 5c55ff99 | Blue Swirl | GEN_LDUXF(name, ldop, op | 0x01, type) \
|
9950 | 5c55ff99 | Blue Swirl | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) |
9951 | 5c55ff99 | Blue Swirl | |
9952 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
9953 | 5c55ff99 | Blue Swirl | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
9954 | 199f830d | Aurelien Jarno | GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), |
9955 | 05050ee8 | Aurelien Jarno | GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
9956 | 05050ee8 | Aurelien Jarno | GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), |
9957 | 5c55ff99 | Blue Swirl | |
9958 | 5c55ff99 | Blue Swirl | #undef GEN_STF
|
9959 | 5c55ff99 | Blue Swirl | #undef GEN_STUF
|
9960 | 5c55ff99 | Blue Swirl | #undef GEN_STUXF
|
9961 | 5c55ff99 | Blue Swirl | #undef GEN_STXF
|
9962 | 5c55ff99 | Blue Swirl | #undef GEN_STFS
|
9963 | 5c55ff99 | Blue Swirl | #define GEN_STF(name, stop, opc, type) \
|
9964 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
9965 | 5c55ff99 | Blue Swirl | #define GEN_STUF(name, stop, opc, type) \
|
9966 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
9967 | 5c55ff99 | Blue Swirl | #define GEN_STUXF(name, stop, opc, type) \
|
9968 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), |
9969 | 5c55ff99 | Blue Swirl | #define GEN_STXF(name, stop, opc2, opc3, type) \
|
9970 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), |
9971 | 5c55ff99 | Blue Swirl | #define GEN_STFS(name, stop, op, type) \
|
9972 | 5c55ff99 | Blue Swirl | GEN_STF(name, stop, op | 0x20, type) \
|
9973 | 5c55ff99 | Blue Swirl | GEN_STUF(name, stop, op | 0x21, type) \
|
9974 | 5c55ff99 | Blue Swirl | GEN_STUXF(name, stop, op | 0x01, type) \
|
9975 | 5c55ff99 | Blue Swirl | GEN_STXF(name, stop, 0x17, op | 0x00, type) |
9976 | 5c55ff99 | Blue Swirl | |
9977 | 5c55ff99 | Blue Swirl | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
|
9978 | 5c55ff99 | Blue Swirl | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
|
9979 | 5c55ff99 | Blue Swirl | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) |
9980 | 44bc0c4d | Aurelien Jarno | GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
9981 | 44bc0c4d | Aurelien Jarno | GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), |
9982 | 5c55ff99 | Blue Swirl | |
9983 | 5c55ff99 | Blue Swirl | #undef GEN_CRLOGIC
|
9984 | 5c55ff99 | Blue Swirl | #define GEN_CRLOGIC(name, tcg_op, opc) \
|
9985 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) |
9986 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
|
9987 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
|
9988 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
|
9989 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
|
9990 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
|
9991 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
|
9992 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
|
9993 | 5c55ff99 | Blue Swirl | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
|
9994 | 5c55ff99 | Blue Swirl | |
9995 | 5c55ff99 | Blue Swirl | #undef GEN_MAC_HANDLER
|
9996 | 5c55ff99 | Blue Swirl | #define GEN_MAC_HANDLER(name, opc2, opc3) \
|
9997 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) |
9998 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), |
9999 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), |
10000 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), |
10001 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), |
10002 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), |
10003 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), |
10004 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), |
10005 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), |
10006 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), |
10007 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), |
10008 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), |
10009 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), |
10010 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), |
10011 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), |
10012 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), |
10013 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), |
10014 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), |
10015 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), |
10016 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), |
10017 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), |
10018 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), |
10019 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), |
10020 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), |
10021 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), |
10022 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), |
10023 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), |
10024 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), |
10025 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), |
10026 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), |
10027 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), |
10028 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), |
10029 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), |
10030 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), |
10031 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), |
10032 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), |
10033 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), |
10034 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), |
10035 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), |
10036 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), |
10037 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), |
10038 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), |
10039 | 5c55ff99 | Blue Swirl | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), |
10040 | 5c55ff99 | Blue Swirl | |
10041 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LDX
|
10042 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STX
|
10043 | 5c55ff99 | Blue Swirl | #undef GEN_VR_LVE
|
10044 | 5c55ff99 | Blue Swirl | #undef GEN_VR_STVE
|
10045 | 5c55ff99 | Blue Swirl | #define GEN_VR_LDX(name, opc2, opc3) \
|
10046 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
10047 | 5c55ff99 | Blue Swirl | #define GEN_VR_STX(name, opc2, opc3) \
|
10048 | 5c55ff99 | Blue Swirl | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
10049 | 5c55ff99 | Blue Swirl | #define GEN_VR_LVE(name, opc2, opc3) \
|
10050 | 5c55ff99 | Blue Swirl | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
10051 | 5c55ff99 | Blue Swirl | #define GEN_VR_STVE(name, opc2, opc3) \
|
10052 | 5c55ff99 | Blue Swirl | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) |
10053 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvx, 0x07, 0x03), |
10054 | 5c55ff99 | Blue Swirl | GEN_VR_LDX(lvxl, 0x07, 0x0B), |
10055 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(bx, 0x07, 0x00), |
10056 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(hx, 0x07, 0x01), |
10057 | 5c55ff99 | Blue Swirl | GEN_VR_LVE(wx, 0x07, 0x02), |
10058 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svx, 0x07, 0x07), |
10059 | 5c55ff99 | Blue Swirl | GEN_VR_STX(svxl, 0x07, 0x0F), |
10060 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(bx, 0x07, 0x04), |
10061 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(hx, 0x07, 0x05), |
10062 | 5c55ff99 | Blue Swirl | GEN_VR_STVE(wx, 0x07, 0x06), |
10063 | 5c55ff99 | Blue Swirl | |
10064 | 5c55ff99 | Blue Swirl | #undef GEN_VX_LOGICAL
|
10065 | 5c55ff99 | Blue Swirl | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
|
10066 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
10067 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
10068 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), |
10069 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), |
10070 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), |
10071 | 5c55ff99 | Blue Swirl | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), |
10072 | 5c55ff99 | Blue Swirl | |
10073 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM
|
10074 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM(name, opc2, opc3) \
|
10075 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
10076 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubm, 0, 0), |
10077 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhm, 0, 1), |
10078 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduwm, 0, 2), |
10079 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububm, 0, 16), |
10080 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhm, 0, 17), |
10081 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuwm, 0, 18), |
10082 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxub, 1, 0), |
10083 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuh, 1, 1), |
10084 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxuw, 1, 2), |
10085 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsb, 1, 4), |
10086 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsh, 1, 5), |
10087 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxsw, 1, 6), |
10088 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminub, 1, 8), |
10089 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuh, 1, 9), |
10090 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminuw, 1, 10), |
10091 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsb, 1, 12), |
10092 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsh, 1, 13), |
10093 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminsw, 1, 14), |
10094 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgub, 1, 16), |
10095 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguh, 1, 17), |
10096 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavguw, 1, 18), |
10097 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsb, 1, 20), |
10098 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsh, 1, 21), |
10099 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vavgsw, 1, 22), |
10100 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghb, 6, 0), |
10101 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghh, 6, 1), |
10102 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrghw, 6, 2), |
10103 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglb, 6, 4), |
10104 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglh, 6, 5), |
10105 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmrglw, 6, 6), |
10106 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuloub, 4, 0), |
10107 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulouh, 4, 1), |
10108 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosb, 4, 4), |
10109 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulosh, 4, 5), |
10110 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleub, 4, 8), |
10111 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmuleuh, 4, 9), |
10112 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesb, 4, 12), |
10113 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmulesh, 4, 13), |
10114 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslb, 2, 4), |
10115 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslh, 2, 5), |
10116 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslw, 2, 6), |
10117 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrb, 2, 8), |
10118 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrh, 2, 9), |
10119 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrw, 2, 10), |
10120 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrab, 2, 12), |
10121 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsrah, 2, 13), |
10122 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsraw, 2, 14), |
10123 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vslo, 6, 16), |
10124 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsro, 6, 17), |
10125 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddcuw, 0, 6), |
10126 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubcuw, 0, 22), |
10127 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddubs, 0, 8), |
10128 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduhs, 0, 9), |
10129 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vadduws, 0, 10), |
10130 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsbs, 0, 12), |
10131 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddshs, 0, 13), |
10132 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddsws, 0, 14), |
10133 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsububs, 0, 24), |
10134 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuhs, 0, 25), |
10135 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubuws, 0, 26), |
10136 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsbs, 0, 28), |
10137 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubshs, 0, 29), |
10138 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubsws, 0, 30), |
10139 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlb, 2, 0), |
10140 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlh, 2, 1), |
10141 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vrlw, 2, 2), |
10142 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsl, 2, 7), |
10143 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsr, 2, 11), |
10144 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhum, 7, 0), |
10145 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwum, 7, 1), |
10146 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuhus, 7, 2), |
10147 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkuwus, 7, 3), |
10148 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshus, 7, 4), |
10149 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswus, 7, 5), |
10150 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkshss, 7, 6), |
10151 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkswss, 7, 7), |
10152 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vpkpx, 7, 12), |
10153 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4ubs, 4, 24), |
10154 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4sbs, 4, 28), |
10155 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum4shs, 4, 25), |
10156 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsum2sws, 4, 26), |
10157 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsumsws, 4, 30), |
10158 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vaddfp, 5, 0), |
10159 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vsubfp, 5, 1), |
10160 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vmaxfp, 5, 16), |
10161 | 5c55ff99 | Blue Swirl | GEN_VXFORM(vminfp, 5, 17), |
10162 | 5c55ff99 | Blue Swirl | |
10163 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM1
|
10164 | 5c55ff99 | Blue Swirl | #undef GEN_VXRFORM
|
10165 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
|
10166 | 5c55ff99 | Blue Swirl | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), |
10167 | 5c55ff99 | Blue Swirl | #define GEN_VXRFORM(name, opc2, opc3) \
|
10168 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name, name, #name, opc2, opc3) \
|
10169 | 5c55ff99 | Blue Swirl | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) |
10170 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequb, 3, 0) |
10171 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequh, 3, 1) |
10172 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpequw, 3, 2) |
10173 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsb, 3, 12) |
10174 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsh, 3, 13) |
10175 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtsw, 3, 14) |
10176 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtub, 3, 8) |
10177 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuh, 3, 9) |
10178 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtuw, 3, 10) |
10179 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpeqfp, 3, 3) |
10180 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgefp, 3, 7) |
10181 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpgtfp, 3, 11) |
10182 | 5c55ff99 | Blue Swirl | GEN_VXRFORM(vcmpbfp, 3, 15) |
10183 | 5c55ff99 | Blue Swirl | |
10184 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_SIMM
|
10185 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_SIMM(name, opc2, opc3) \
|
10186 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
10187 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisb, 6, 12), |
10188 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltish, 6, 13), |
10189 | 5c55ff99 | Blue Swirl | GEN_VXFORM_SIMM(vspltisw, 6, 14), |
10190 | 5c55ff99 | Blue Swirl | |
10191 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_NOA
|
10192 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_NOA(name, opc2, opc3) \
|
10193 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) |
10194 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsb, 7, 8), |
10195 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhsh, 7, 9), |
10196 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsb, 7, 10), |
10197 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklsh, 7, 11), |
10198 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
10199 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vupklpx, 7, 15), |
10200 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrefp, 5, 4), |
10201 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), |
10202 | 0bffbc6c | Aurelien Jarno | GEN_VXFORM_NOA(vexptefp, 5, 6), |
10203 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vlogefp, 5, 7), |
10204 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfim, 5, 8), |
10205 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfin, 5, 9), |
10206 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfip, 5, 10), |
10207 | 5c55ff99 | Blue Swirl | GEN_VXFORM_NOA(vrfiz, 5, 11), |
10208 | 5c55ff99 | Blue Swirl | |
10209 | 5c55ff99 | Blue Swirl | #undef GEN_VXFORM_UIMM
|
10210 | 5c55ff99 | Blue Swirl | #define GEN_VXFORM_UIMM(name, opc2, opc3) \
|
10211 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) |
10212 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltb, 6, 8), |
10213 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vsplth, 6, 9), |
10214 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vspltw, 6, 10), |
10215 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfux, 5, 12), |
10216 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vcfsx, 5, 13), |
10217 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctuxs, 5, 14), |
10218 | 5c55ff99 | Blue Swirl | GEN_VXFORM_UIMM(vctsxs, 5, 15), |
10219 | 5c55ff99 | Blue Swirl | |
10220 | 5c55ff99 | Blue Swirl | #undef GEN_VAFORM_PAIRED
|
10221 | 5c55ff99 | Blue Swirl | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
|
10222 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) |
10223 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
|
10224 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
|
10225 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
|
10226 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
|
10227 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vsel, vperm, 21),
|
10228 | 5c55ff99 | Blue Swirl | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
|
10229 | 5c55ff99 | Blue Swirl | |
10230 | fa1832d7 | Tom Musta | GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), |
10231 | cac7f0ba | Tom Musta | GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), |
10232 | cac7f0ba | Tom Musta | GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), |
10233 | cac7f0ba | Tom Musta | GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), |
10234 | 304af367 | Tom Musta | GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), |
10235 | ca03b467 | Tom Musta | GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), |
10236 | 897e61d1 | Tom Musta | GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), |
10237 | 304af367 | Tom Musta | |
10238 | 9231ba9e | Tom Musta | GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), |
10239 | e16a626b | Tom Musta | GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), |
10240 | e16a626b | Tom Musta | GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), |
10241 | fbed2478 | Tom Musta | GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |
10242 | 86e61ce3 | Tom Musta | GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), |
10243 | fbed2478 | Tom Musta | |
10244 | f5c0f7f9 | Tom Musta | GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10245 | f5c0f7f9 | Tom Musta | GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10246 | f5c0f7f9 | Tom Musta | GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10247 | f5c0f7f9 | Tom Musta | #if defined(TARGET_PPC64)
|
10248 | f5c0f7f9 | Tom Musta | GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10249 | f5c0f7f9 | Tom Musta | GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10250 | f5c0f7f9 | Tom Musta | #endif
|
10251 | f5c0f7f9 | Tom Musta | |
10252 | df020ce0 | Tom Musta | #undef GEN_XX2FORM
|
10253 | df020ce0 | Tom Musta | #define GEN_XX2FORM(name, opc2, opc3, fl2) \
|
10254 | df020ce0 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ |
10255 | df020ce0 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) |
10256 | df020ce0 | Tom Musta | |
10257 | df020ce0 | Tom Musta | #undef GEN_XX3FORM
|
10258 | df020ce0 | Tom Musta | #define GEN_XX3FORM(name, opc2, opc3, fl2) \
|
10259 | df020ce0 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ |
10260 | df020ce0 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ |
10261 | df020ce0 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ |
10262 | df020ce0 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) |
10263 | df020ce0 | Tom Musta | |
10264 | 354a6dec | Tom Musta | #undef GEN_XX3_RC_FORM
|
10265 | 354a6dec | Tom Musta | #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
|
10266 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \ |
10267 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \ |
10268 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \ |
10269 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \ |
10270 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \ |
10271 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \ |
10272 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \ |
10273 | 354a6dec | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2) |
10274 | 354a6dec | Tom Musta | |
10275 | cd73f2c9 | Tom Musta | #undef GEN_XX3FORM_DM
|
10276 | cd73f2c9 | Tom Musta | #define GEN_XX3FORM_DM(name, opc2, opc3) \
|
10277 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ |
10278 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ |
10279 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ |
10280 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ |
10281 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ |
10282 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ |
10283 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ |
10284 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ |
10285 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ |
10286 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ |
10287 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ |
10288 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ |
10289 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ |
10290 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ |
10291 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ |
10292 | cd73f2c9 | Tom Musta | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) |
10293 | cd73f2c9 | Tom Musta | |
10294 | df020ce0 | Tom Musta | GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), |
10295 | df020ce0 | Tom Musta | GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), |
10296 | df020ce0 | Tom Musta | GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), |
10297 | df020ce0 | Tom Musta | GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), |
10298 | df020ce0 | Tom Musta | |
10299 | be574920 | Tom Musta | GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), |
10300 | be574920 | Tom Musta | GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), |
10301 | be574920 | Tom Musta | GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), |
10302 | be574920 | Tom Musta | GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), |
10303 | be574920 | Tom Musta | GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), |
10304 | be574920 | Tom Musta | GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), |
10305 | be574920 | Tom Musta | GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), |
10306 | be574920 | Tom Musta | GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), |
10307 | 79ca8a6a | Tom Musta | |
10308 | ee6e02c0 | Tom Musta | GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), |
10309 | ee6e02c0 | Tom Musta | GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), |
10310 | 5e591d88 | Tom Musta | GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), |
10311 | 4b98eeef | Tom Musta | GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), |
10312 | 2009227f | Tom Musta | GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), |
10313 | d32404fe | Tom Musta | GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), |
10314 | d3f9df8f | Tom Musta | GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), |
10315 | bc80838f | Tom Musta | GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), |
10316 | 5cb151ac | Tom Musta | GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), |
10317 | 595c6eef | Tom Musta | GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX), |
10318 | 595c6eef | Tom Musta | GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX), |
10319 | 595c6eef | Tom Musta | GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX), |
10320 | 595c6eef | Tom Musta | GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX), |
10321 | 595c6eef | Tom Musta | GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX), |
10322 | 595c6eef | Tom Musta | GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX), |
10323 | 595c6eef | Tom Musta | GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX), |
10324 | 595c6eef | Tom Musta | GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX), |
10325 | 4f17e9c7 | Tom Musta | GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), |
10326 | 4f17e9c7 | Tom Musta | GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), |
10327 | 959e9c9d | Tom Musta | GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), |
10328 | 959e9c9d | Tom Musta | GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), |
10329 | ed8ac568 | Tom Musta | GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), |
10330 | 7ee19fb9 | Tom Musta | GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), |
10331 | ed8ac568 | Tom Musta | GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), |
10332 | 7ee19fb9 | Tom Musta | GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207), |
10333 | 5177d2ca | Tom Musta | GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX), |
10334 | 5177d2ca | Tom Musta | GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX), |
10335 | 5177d2ca | Tom Musta | GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX), |
10336 | 5177d2ca | Tom Musta | GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX), |
10337 | 5177d2ca | Tom Musta | GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX), |
10338 | 5177d2ca | Tom Musta | GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX), |
10339 | 88e33d08 | Tom Musta | GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX), |
10340 | 88e33d08 | Tom Musta | GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX), |
10341 | 88e33d08 | Tom Musta | GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), |
10342 | 88e33d08 | Tom Musta | GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), |
10343 | 88e33d08 | Tom Musta | GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), |
10344 | ee6e02c0 | Tom Musta | |
10345 | 3fd0aadf | Tom Musta | GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), |
10346 | 3fd0aadf | Tom Musta | GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), |
10347 | ab9408a2 | Tom Musta | GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), |
10348 | b24d0b47 | Tom Musta | GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), |
10349 | 2c0c52ae | Tom Musta | GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), |
10350 | 3d1140bf | Tom Musta | GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), |
10351 | cea4e574 | Tom Musta | GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), |
10352 | 968e76bc | Tom Musta | GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), |
10353 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207), |
10354 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207), |
10355 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207), |
10356 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207), |
10357 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207), |
10358 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207), |
10359 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207), |
10360 | f53f81e0 | Tom Musta | GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207), |
10361 | 74698350 | Tom Musta | GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), |
10362 | 74698350 | Tom Musta | GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), |
10363 | 3fd0aadf | Tom Musta | |
10364 | ee6e02c0 | Tom Musta | GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), |
10365 | ee6e02c0 | Tom Musta | GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), |
10366 | 5e591d88 | Tom Musta | GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), |
10367 | 4b98eeef | Tom Musta | GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), |
10368 | 2009227f | Tom Musta | GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), |
10369 | d32404fe | Tom Musta | GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), |
10370 | d3f9df8f | Tom Musta | GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), |
10371 | bc80838f | Tom Musta | GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), |
10372 | 5cb151ac | Tom Musta | GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), |
10373 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX), |
10374 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX), |
10375 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX), |
10376 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX), |
10377 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX), |
10378 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX), |
10379 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX), |
10380 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX), |
10381 | 959e9c9d | Tom Musta | GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), |
10382 | 959e9c9d | Tom Musta | GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), |
10383 | 354a6dec | Tom Musta | GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), |
10384 | 354a6dec | Tom Musta | GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX), |
10385 | 354a6dec | Tom Musta | GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX), |
10386 | ed8ac568 | Tom Musta | GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX), |
10387 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX), |
10388 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX), |
10389 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX), |
10390 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX), |
10391 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX), |
10392 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX), |
10393 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX), |
10394 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX), |
10395 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX), |
10396 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX), |
10397 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX), |
10398 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX), |
10399 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX), |
10400 | ee6e02c0 | Tom Musta | |
10401 | ee6e02c0 | Tom Musta | GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), |
10402 | ee6e02c0 | Tom Musta | GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), |
10403 | 5e591d88 | Tom Musta | GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), |
10404 | 4b98eeef | Tom Musta | GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), |
10405 | 2009227f | Tom Musta | GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), |
10406 | d32404fe | Tom Musta | GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), |
10407 | d3f9df8f | Tom Musta | GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), |
10408 | bc80838f | Tom Musta | GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), |
10409 | 5cb151ac | Tom Musta | GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), |
10410 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX), |
10411 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX), |
10412 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX), |
10413 | 595c6eef | Tom Musta | GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX), |
10414 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX), |
10415 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX), |
10416 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX), |
10417 | 595c6eef | Tom Musta | GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX), |
10418 | 959e9c9d | Tom Musta | GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), |
10419 | 959e9c9d | Tom Musta | GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), |
10420 | 354a6dec | Tom Musta | GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), |
10421 | 354a6dec | Tom Musta | GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX), |
10422 | 354a6dec | Tom Musta | GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX), |
10423 | ed8ac568 | Tom Musta | GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX), |
10424 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX), |
10425 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX), |
10426 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX), |
10427 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX), |
10428 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX), |
10429 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX), |
10430 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX), |
10431 | 5177d2ca | Tom Musta | GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX), |
10432 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX), |
10433 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX), |
10434 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX), |
10435 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX), |
10436 | 88e33d08 | Tom Musta | GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX), |
10437 | ee6e02c0 | Tom Musta | |
10438 | 79ca8a6a | Tom Musta | #undef VSX_LOGICAL
|
10439 | 79ca8a6a | Tom Musta | #define VSX_LOGICAL(name, opc2, opc3, fl2) \
|
10440 | 79ca8a6a | Tom Musta | GEN_XX3FORM(name, opc2, opc3, fl2) |
10441 | 79ca8a6a | Tom Musta | |
10442 | 79ca8a6a | Tom Musta | VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), |
10443 | 79ca8a6a | Tom Musta | VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), |
10444 | 79ca8a6a | Tom Musta | VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), |
10445 | 79ca8a6a | Tom Musta | VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), |
10446 | 79ca8a6a | Tom Musta | VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), |
10447 | 67a33f37 | Tom Musta | VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207), |
10448 | 67a33f37 | Tom Musta | VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), |
10449 | 67a33f37 | Tom Musta | VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), |
10450 | ce577d2e | Tom Musta | GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), |
10451 | ce577d2e | Tom Musta | GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), |
10452 | 76c15fe0 | Tom Musta | GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), |
10453 | acc42968 | Tom Musta | GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), |
10454 | 79ca8a6a | Tom Musta | |
10455 | 551e3ef7 | Tom Musta | #define GEN_XXSEL_ROW(opc3) \
|
10456 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10457 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10458 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10459 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10460 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10461 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10462 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10463 | 551e3ef7 | Tom Musta | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ |
10464 | 551e3ef7 | Tom Musta | |
10465 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x00)
|
10466 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x01)
|
10467 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x02)
|
10468 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x03)
|
10469 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x04)
|
10470 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x05)
|
10471 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x06)
|
10472 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x07)
|
10473 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x08)
|
10474 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x09)
|
10475 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x0A)
|
10476 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x0B)
|
10477 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x0C)
|
10478 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x0D)
|
10479 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x0E)
|
10480 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x0F)
|
10481 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x10)
|
10482 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x11)
|
10483 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x12)
|
10484 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x13)
|
10485 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x14)
|
10486 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x15)
|
10487 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x16)
|
10488 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x17)
|
10489 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x18)
|
10490 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x19)
|
10491 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x1A)
|
10492 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x1B)
|
10493 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x1C)
|
10494 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x1D)
|
10495 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x1E)
|
10496 | 551e3ef7 | Tom Musta | GEN_XXSEL_ROW(0x1F)
|
10497 | 551e3ef7 | Tom Musta | |
10498 | cd73f2c9 | Tom Musta | GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), |
10499 | cd73f2c9 | Tom Musta | |
10500 | 5c55ff99 | Blue Swirl | #undef GEN_SPE
|
10501 | 70560da7 | Fabien Chouteau | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
|
10502 | 70560da7 | Fabien Chouteau | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) |
10503 | 70560da7 | Fabien Chouteau | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10504 | 70560da7 | Fabien Chouteau | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10505 | 70560da7 | Fabien Chouteau | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10506 | 70560da7 | Fabien Chouteau | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10507 | 70560da7 | Fabien Chouteau | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), |
10508 | 70560da7 | Fabien Chouteau | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), |
10509 | 70560da7 | Fabien Chouteau | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), |
10510 | 70560da7 | Fabien Chouteau | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), |
10511 | 70560da7 | Fabien Chouteau | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), |
10512 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), |
10513 | 70560da7 | Fabien Chouteau | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10514 | 70560da7 | Fabien Chouteau | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
10515 | 70560da7 | Fabien Chouteau | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
10516 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), |
10517 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), |
10518 | 70560da7 | Fabien Chouteau | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), |
10519 | 70560da7 | Fabien Chouteau | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), |
10520 | 70560da7 | Fabien Chouteau | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10521 | 70560da7 | Fabien Chouteau | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
10522 | 70560da7 | Fabien Chouteau | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
10523 | 70560da7 | Fabien Chouteau | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10524 | 70560da7 | Fabien Chouteau | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), |
10525 | 70560da7 | Fabien Chouteau | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), |
10526 | 70560da7 | Fabien Chouteau | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), |
10527 | 70560da7 | Fabien Chouteau | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
10528 | 70560da7 | Fabien Chouteau | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), |
10529 | 70560da7 | Fabien Chouteau | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), |
10530 | 70560da7 | Fabien Chouteau | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), |
10531 | 70560da7 | Fabien Chouteau | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), |
10532 | 70560da7 | Fabien Chouteau | |
10533 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
10534 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), |
10535 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10536 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
10537 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
10538 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10539 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10540 | 70560da7 | Fabien Chouteau | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10541 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10542 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10543 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10544 | 70560da7 | Fabien Chouteau | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10545 | 70560da7 | Fabien Chouteau | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
10546 | 70560da7 | Fabien Chouteau | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10547 | 70560da7 | Fabien Chouteau | |
10548 | 70560da7 | Fabien Chouteau | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
10549 | 70560da7 | Fabien Chouteau | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), |
10550 | 70560da7 | Fabien Chouteau | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10551 | 70560da7 | Fabien Chouteau | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), |
10552 | 70560da7 | Fabien Chouteau | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
10553 | 70560da7 | Fabien Chouteau | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), |
10554 | 70560da7 | Fabien Chouteau | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10555 | 70560da7 | Fabien Chouteau | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10556 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10557 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), |
10558 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10559 | 70560da7 | Fabien Chouteau | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10560 | 70560da7 | Fabien Chouteau | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), |
10561 | 70560da7 | Fabien Chouteau | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), |
10562 | 70560da7 | Fabien Chouteau | |
10563 | 70560da7 | Fabien Chouteau | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), |
10564 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
10565 | 70560da7 | Fabien Chouteau | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), |
10566 | 70560da7 | Fabien Chouteau | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
10567 | 70560da7 | Fabien Chouteau | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), |
10568 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
10569 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), |
10570 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), |
10571 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
10572 | 70560da7 | Fabien Chouteau | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
10573 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
10574 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), |
10575 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
10576 | 70560da7 | Fabien Chouteau | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
10577 | 70560da7 | Fabien Chouteau | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), |
10578 | 70560da7 | Fabien Chouteau | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), |
10579 | 5c55ff99 | Blue Swirl | |
10580 | 5c55ff99 | Blue Swirl | #undef GEN_SPEOP_LDST
|
10581 | 5c55ff99 | Blue Swirl | #define GEN_SPEOP_LDST(name, opc2, sh) \
|
10582 | 5c55ff99 | Blue Swirl | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) |
10583 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldd, 0x00, 3), |
10584 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldw, 0x01, 3), |
10585 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evldh, 0x02, 3), |
10586 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), |
10587 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), |
10588 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), |
10589 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhe, 0x08, 2), |
10590 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), |
10591 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), |
10592 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), |
10593 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), |
10594 | 5c55ff99 | Blue Swirl | |
10595 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdd, 0x10, 3), |
10596 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdw, 0x11, 3), |
10597 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstdh, 0x12, 3), |
10598 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwhe, 0x18, 2), |
10599 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwho, 0x1A, 2), |
10600 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), |
10601 | 5c55ff99 | Blue Swirl | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), |
10602 | 5c55ff99 | Blue Swirl | }; |
10603 | 5c55ff99 | Blue Swirl | |
10604 | 0411a972 | j_mayer | #include "helper_regs.h" |
10605 | a1389542 | Andreas Färber | #include "translate_init.c" |
10606 | 79aceca5 | bellard | |
10607 | 9a64fbe4 | bellard | /*****************************************************************************/
|
10608 | 3fc6c082 | bellard | /* Misc PowerPC helpers */
|
10609 | 878096ee | Andreas Färber | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
|
10610 | 878096ee | Andreas Färber | int flags)
|
10611 | 79aceca5 | bellard | { |
10612 | 3fc6c082 | bellard | #define RGPL 4 |
10613 | 3fc6c082 | bellard | #define RFPL 4 |
10614 | 3fc6c082 | bellard | |
10615 | 878096ee | Andreas Färber | PowerPCCPU *cpu = POWERPC_CPU(cs); |
10616 | 878096ee | Andreas Färber | CPUPPCState *env = &cpu->env; |
10617 | 79aceca5 | bellard | int i;
|
10618 | 79aceca5 | bellard | |
10619 | 90e189ec | Blue Swirl | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
10620 | 9a78eead | Stefan Weil | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
10621 | da91a00f | Richard Henderson | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
10622 | 90e189ec | Blue Swirl | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
10623 | 90e189ec | Blue Swirl | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
|
10624 | 90e189ec | Blue Swirl | env->hflags, env->mmu_idx); |
10625 | d9bce9d9 | j_mayer | #if !defined(NO_TIMER_DUMP)
|
10626 | 9a78eead | Stefan Weil | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
10627 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
10628 | 9a78eead | Stefan Weil | " DECR %08" PRIu32
|
10629 | 76a66253 | j_mayer | #endif
|
10630 | 76a66253 | j_mayer | "\n",
|
10631 | 077fc206 | j_mayer | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
10632 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
10633 | 76a66253 | j_mayer | , cpu_ppc_load_decr(env) |
10634 | 76a66253 | j_mayer | #endif
|
10635 | 76a66253 | j_mayer | ); |
10636 | 077fc206 | j_mayer | #endif
|
10637 | 76a66253 | j_mayer | for (i = 0; i < 32; i++) { |
10638 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == 0) |
10639 | 3fc6c082 | bellard | cpu_fprintf(f, "GPR%02d", i);
|
10640 | b11ebf64 | Blue Swirl | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
|
10641 | 3fc6c082 | bellard | if ((i & (RGPL - 1)) == (RGPL - 1)) |
10642 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
10643 | 76a66253 | j_mayer | } |
10644 | 3fc6c082 | bellard | cpu_fprintf(f, "CR ");
|
10645 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) |
10646 | 7fe48483 | bellard | cpu_fprintf(f, "%01x", env->crf[i]);
|
10647 | 7fe48483 | bellard | cpu_fprintf(f, " [");
|
10648 | 76a66253 | j_mayer | for (i = 0; i < 8; i++) { |
10649 | 76a66253 | j_mayer | char a = '-'; |
10650 | 76a66253 | j_mayer | if (env->crf[i] & 0x08) |
10651 | 76a66253 | j_mayer | a = 'L';
|
10652 | 76a66253 | j_mayer | else if (env->crf[i] & 0x04) |
10653 | 76a66253 | j_mayer | a = 'G';
|
10654 | 76a66253 | j_mayer | else if (env->crf[i] & 0x02) |
10655 | 76a66253 | j_mayer | a = 'E';
|
10656 | 7fe48483 | bellard | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
10657 | 76a66253 | j_mayer | } |
10658 | 90e189ec | Blue Swirl | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
10659 | 90e189ec | Blue Swirl | env->reserve_addr); |
10660 | 3fc6c082 | bellard | for (i = 0; i < 32; i++) { |
10661 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == 0) |
10662 | 3fc6c082 | bellard | cpu_fprintf(f, "FPR%02d", i);
|
10663 | 26a76461 | bellard | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
|
10664 | 3fc6c082 | bellard | if ((i & (RFPL - 1)) == (RFPL - 1)) |
10665 | 7fe48483 | bellard | cpu_fprintf(f, "\n");
|
10666 | 79aceca5 | bellard | } |
10667 | 30304420 | David Gibson | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
10668 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
10669 | 90dc8812 | Scott Wood | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
10670 | 90dc8812 | Scott Wood | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", |
10671 | 90dc8812 | Scott Wood | env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
10672 | 90dc8812 | Scott Wood | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); |
10673 | 90dc8812 | Scott Wood | |
10674 | 90dc8812 | Scott Wood | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx |
10675 | 90dc8812 | Scott Wood | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", |
10676 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], |
10677 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); |
10678 | 90dc8812 | Scott Wood | |
10679 | 90dc8812 | Scott Wood | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx |
10680 | 90dc8812 | Scott Wood | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", |
10681 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], |
10682 | 90dc8812 | Scott Wood | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); |
10683 | 90dc8812 | Scott Wood | |
10684 | 90dc8812 | Scott Wood | if (env->excp_model == POWERPC_EXCP_BOOKE) {
|
10685 | 90dc8812 | Scott Wood | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx |
10686 | 90dc8812 | Scott Wood | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", |
10687 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], |
10688 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
10689 | 90dc8812 | Scott Wood | |
10690 | 90dc8812 | Scott Wood | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx |
10691 | 90dc8812 | Scott Wood | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", |
10692 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], |
10693 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); |
10694 | 90dc8812 | Scott Wood | |
10695 | 90dc8812 | Scott Wood | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx |
10696 | 90dc8812 | Scott Wood | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", |
10697 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], |
10698 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); |
10699 | 90dc8812 | Scott Wood | |
10700 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx |
10701 | 90dc8812 | Scott Wood | " EPR " TARGET_FMT_lx "\n", |
10702 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], |
10703 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_EPR]); |
10704 | 90dc8812 | Scott Wood | |
10705 | 90dc8812 | Scott Wood | /* FSL-specific */
|
10706 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx |
10707 | 90dc8812 | Scott Wood | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", |
10708 | 90dc8812 | Scott Wood | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], |
10709 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); |
10710 | 90dc8812 | Scott Wood | |
10711 | 90dc8812 | Scott Wood | /*
|
10712 | 90dc8812 | Scott Wood | * IVORs are left out as they are large and do not change often --
|
10713 | 90dc8812 | Scott Wood | * they can be read with "p $ivor0", "p $ivor1", etc.
|
10714 | 90dc8812 | Scott Wood | */
|
10715 | 90dc8812 | Scott Wood | } |
10716 | 90dc8812 | Scott Wood | |
10717 | 697ab892 | David Gibson | #if defined(TARGET_PPC64)
|
10718 | 697ab892 | David Gibson | if (env->flags & POWERPC_FLAG_CFAR) {
|
10719 | 697ab892 | David Gibson | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); |
10720 | 697ab892 | David Gibson | } |
10721 | 697ab892 | David Gibson | #endif
|
10722 | 697ab892 | David Gibson | |
10723 | 90dc8812 | Scott Wood | switch (env->mmu_model) {
|
10724 | 90dc8812 | Scott Wood | case POWERPC_MMU_32B:
|
10725 | 90dc8812 | Scott Wood | case POWERPC_MMU_601:
|
10726 | 90dc8812 | Scott Wood | case POWERPC_MMU_SOFT_6xx:
|
10727 | 90dc8812 | Scott Wood | case POWERPC_MMU_SOFT_74xx:
|
10728 | 90dc8812 | Scott Wood | #if defined(TARGET_PPC64)
|
10729 | 90dc8812 | Scott Wood | case POWERPC_MMU_64B:
|
10730 | ca480de6 | Anton Blanchard | case POWERPC_MMU_2_06:
|
10731 | ca480de6 | Anton Blanchard | case POWERPC_MMU_2_06a:
|
10732 | ca480de6 | Anton Blanchard | case POWERPC_MMU_2_06d:
|
10733 | 90dc8812 | Scott Wood | #endif
|
10734 | ca480de6 | Anton Blanchard | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx |
10735 | ca480de6 | Anton Blanchard | " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], |
10736 | ca480de6 | Anton Blanchard | env->spr[SPR_DAR], env->spr[SPR_DSISR]); |
10737 | 90dc8812 | Scott Wood | break;
|
10738 | 01662f3e | Alexander Graf | case POWERPC_MMU_BOOKE206:
|
10739 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
10740 | 90dc8812 | Scott Wood | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", |
10741 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], |
10742 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); |
10743 | 90dc8812 | Scott Wood | |
10744 | 90dc8812 | Scott Wood | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx |
10745 | 90dc8812 | Scott Wood | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", |
10746 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], |
10747 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); |
10748 | 90dc8812 | Scott Wood | |
10749 | 90dc8812 | Scott Wood | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx |
10750 | 90dc8812 | Scott Wood | " TLB1CFG " TARGET_FMT_lx "\n", |
10751 | 90dc8812 | Scott Wood | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], |
10752 | 90dc8812 | Scott Wood | env->spr[SPR_BOOKE_TLB1CFG]); |
10753 | 90dc8812 | Scott Wood | break;
|
10754 | 90dc8812 | Scott Wood | default:
|
10755 | 90dc8812 | Scott Wood | break;
|
10756 | 90dc8812 | Scott Wood | } |
10757 | f2e63a42 | j_mayer | #endif
|
10758 | 79aceca5 | bellard | |
10759 | 3fc6c082 | bellard | #undef RGPL
|
10760 | 3fc6c082 | bellard | #undef RFPL
|
10761 | 79aceca5 | bellard | } |
10762 | 79aceca5 | bellard | |
10763 | 878096ee | Andreas Färber | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
|
10764 | 878096ee | Andreas Färber | fprintf_function cpu_fprintf, int flags)
|
10765 | 76a66253 | j_mayer | { |
10766 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
10767 | 878096ee | Andreas Färber | PowerPCCPU *cpu = POWERPC_CPU(cs); |
10768 | c227f099 | Anthony Liguori | opc_handler_t **t1, **t2, **t3, *handler; |
10769 | 76a66253 | j_mayer | int op1, op2, op3;
|
10770 | 76a66253 | j_mayer | |
10771 | 878096ee | Andreas Färber | t1 = cpu->env.opcodes; |
10772 | 76a66253 | j_mayer | for (op1 = 0; op1 < 64; op1++) { |
10773 | 76a66253 | j_mayer | handler = t1[op1]; |
10774 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
10775 | 76a66253 | j_mayer | t2 = ind_table(handler); |
10776 | 76a66253 | j_mayer | for (op2 = 0; op2 < 32; op2++) { |
10777 | 76a66253 | j_mayer | handler = t2[op2]; |
10778 | 76a66253 | j_mayer | if (is_indirect_opcode(handler)) {
|
10779 | 76a66253 | j_mayer | t3 = ind_table(handler); |
10780 | 76a66253 | j_mayer | for (op3 = 0; op3 < 32; op3++) { |
10781 | 76a66253 | j_mayer | handler = t3[op3]; |
10782 | 76a66253 | j_mayer | if (handler->count == 0) |
10783 | 76a66253 | j_mayer | continue;
|
10784 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
|
10785 | 0bfcd599 | Blue Swirl | "%016" PRIx64 " %" PRId64 "\n", |
10786 | 76a66253 | j_mayer | op1, op2, op3, op1, (op3 << 5) | op2,
|
10787 | 76a66253 | j_mayer | handler->oname, |
10788 | 76a66253 | j_mayer | handler->count, handler->count); |
10789 | 76a66253 | j_mayer | } |
10790 | 76a66253 | j_mayer | } else {
|
10791 | 76a66253 | j_mayer | if (handler->count == 0) |
10792 | 76a66253 | j_mayer | continue;
|
10793 | 76a66253 | j_mayer | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
|
10794 | 0bfcd599 | Blue Swirl | "%016" PRIx64 " %" PRId64 "\n", |
10795 | 76a66253 | j_mayer | op1, op2, op1, op2, handler->oname, |
10796 | 76a66253 | j_mayer | handler->count, handler->count); |
10797 | 76a66253 | j_mayer | } |
10798 | 76a66253 | j_mayer | } |
10799 | 76a66253 | j_mayer | } else {
|
10800 | 76a66253 | j_mayer | if (handler->count == 0) |
10801 | 76a66253 | j_mayer | continue;
|
10802 | 0bfcd599 | Blue Swirl | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
|
10803 | 0bfcd599 | Blue Swirl | " %" PRId64 "\n", |
10804 | 76a66253 | j_mayer | op1, op1, handler->oname, |
10805 | 76a66253 | j_mayer | handler->count, handler->count); |
10806 | 76a66253 | j_mayer | } |
10807 | 76a66253 | j_mayer | } |
10808 | 76a66253 | j_mayer | #endif
|
10809 | 76a66253 | j_mayer | } |
10810 | 76a66253 | j_mayer | |
10811 | 9a64fbe4 | bellard | /*****************************************************************************/
|
10812 | 213fe1f5 | Andreas Färber | static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, |
10813 | 636aa200 | Blue Swirl | TranslationBlock *tb, |
10814 | 213fe1f5 | Andreas Färber | bool search_pc)
|
10815 | 79aceca5 | bellard | { |
10816 | ed2803da | Andreas Färber | CPUState *cs = CPU(cpu); |
10817 | 213fe1f5 | Andreas Färber | CPUPPCState *env = &cpu->env; |
10818 | 9fddaa0c | bellard | DisasContext ctx, *ctxp = &ctx; |
10819 | c227f099 | Anthony Liguori | opc_handler_t **table, *handler; |
10820 | 0fa85d43 | bellard | target_ulong pc_start; |
10821 | 79aceca5 | bellard | uint16_t *gen_opc_end; |
10822 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
10823 | 79aceca5 | bellard | int j, lj = -1; |
10824 | 2e70f6ef | pbrook | int num_insns;
|
10825 | 2e70f6ef | pbrook | int max_insns;
|
10826 | 79aceca5 | bellard | |
10827 | 79aceca5 | bellard | pc_start = tb->pc; |
10828 | 92414b31 | Evgeny Voevodin | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
10829 | 046d6672 | bellard | ctx.nip = pc_start; |
10830 | 79aceca5 | bellard | ctx.tb = tb; |
10831 | e1833e1f | j_mayer | ctx.exception = POWERPC_EXCP_NONE; |
10832 | 3fc6c082 | bellard | ctx.spr_cb = env->spr_cb; |
10833 | 76db3ba4 | aurel32 | ctx.mem_idx = env->mmu_idx; |
10834 | 7d08d856 | Aurelien Jarno | ctx.insns_flags = env->insns_flags; |
10835 | 7d08d856 | Aurelien Jarno | ctx.insns_flags2 = env->insns_flags2; |
10836 | 76db3ba4 | aurel32 | ctx.access_type = -1;
|
10837 | 76db3ba4 | aurel32 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; |
10838 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
10839 | e42a61f1 | Alexander Graf | ctx.sf_mode = msr_is_64bit(env, env->msr); |
10840 | 697ab892 | David Gibson | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
10841 | 9a64fbe4 | bellard | #endif
|
10842 | 3cc62370 | bellard | ctx.fpu_enabled = msr_fp; |
10843 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
|
10844 | d26bfc9a | j_mayer | ctx.spe_enabled = msr_spe; |
10845 | d26bfc9a | j_mayer | else
|
10846 | d26bfc9a | j_mayer | ctx.spe_enabled = 0;
|
10847 | a9d9eb8f | j_mayer | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
|
10848 | a9d9eb8f | j_mayer | ctx.altivec_enabled = msr_vr; |
10849 | a9d9eb8f | j_mayer | else
|
10850 | a9d9eb8f | j_mayer | ctx.altivec_enabled = 0;
|
10851 | 1f29871c | Tom Musta | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
|
10852 | 1f29871c | Tom Musta | ctx.vsx_enabled = msr_vsx; |
10853 | 1f29871c | Tom Musta | } else {
|
10854 | 1f29871c | Tom Musta | ctx.vsx_enabled = 0;
|
10855 | 1f29871c | Tom Musta | } |
10856 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_SE) && msr_se)
|
10857 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
10858 | d26bfc9a | j_mayer | else
|
10859 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled = 0;
|
10860 | d26bfc9a | j_mayer | if ((env->flags & POWERPC_FLAG_BE) && msr_be)
|
10861 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
10862 | ed2803da | Andreas Färber | if (unlikely(cs->singlestep_enabled)) {
|
10863 | 8cbcb4fa | aurel32 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
10864 | ed2803da | Andreas Färber | } |
10865 | 3fc6c082 | bellard | #if defined (DO_SINGLE_STEP) && 0 |
10866 | 9a64fbe4 | bellard | /* Single step trace mode */
|
10867 | 9a64fbe4 | bellard | msr_se = 1;
|
10868 | 9a64fbe4 | bellard | #endif
|
10869 | 2e70f6ef | pbrook | num_insns = 0;
|
10870 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
10871 | 2e70f6ef | pbrook | if (max_insns == 0) |
10872 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
10873 | 2e70f6ef | pbrook | |
10874 | 806f352d | Peter Maydell | gen_tb_start(); |
10875 | 9a64fbe4 | bellard | /* Set env in case of segfault during code fetch */
|
10876 | efd7f486 | Evgeny Voevodin | while (ctx.exception == POWERPC_EXCP_NONE
|
10877 | efd7f486 | Evgeny Voevodin | && tcg_ctx.gen_opc_ptr < gen_opc_end) { |
10878 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
10879 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
10880 | a1d1bb31 | aliguori | if (bp->pc == ctx.nip) {
|
10881 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
10882 | ea4e754f | bellard | break;
|
10883 | ea4e754f | bellard | } |
10884 | ea4e754f | bellard | } |
10885 | ea4e754f | bellard | } |
10886 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
10887 | 92414b31 | Evgeny Voevodin | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
10888 | 79aceca5 | bellard | if (lj < j) {
|
10889 | 79aceca5 | bellard | lj++; |
10890 | 79aceca5 | bellard | while (lj < j)
|
10891 | ab1103de | Evgeny Voevodin | tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
10892 | 79aceca5 | bellard | } |
10893 | 25983cad | Evgeny Voevodin | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
10894 | ab1103de | Evgeny Voevodin | tcg_ctx.gen_opc_instr_start[lj] = 1;
|
10895 | c9c99c22 | Evgeny Voevodin | tcg_ctx.gen_opc_icount[lj] = num_insns; |
10896 | 79aceca5 | bellard | } |
10897 | d12d51d5 | aliguori | LOG_DISAS("----------------\n");
|
10898 | 90e189ec | Blue Swirl | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
10899 | d12d51d5 | aliguori | ctx.nip, ctx.mem_idx, (int)msr_ir);
|
10900 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
10901 | 2e70f6ef | pbrook | gen_io_start(); |
10902 | 76db3ba4 | aurel32 | if (unlikely(ctx.le_mode)) {
|
10903 | 2f5a189c | Blue Swirl | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
10904 | 056401ea | j_mayer | } else {
|
10905 | 2f5a189c | Blue Swirl | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
10906 | 111bfab3 | bellard | } |
10907 | d12d51d5 | aliguori | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
|
10908 | 9a64fbe4 | bellard | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
10909 | 476b6d16 | Andreas Färber | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
10910 | fdefe51c | Richard Henderson | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
|
10911 | 731c54f8 | Aurelien Jarno | tcg_gen_debug_insn_start(ctx.nip); |
10912 | fdefe51c | Richard Henderson | } |
10913 | 046d6672 | bellard | ctx.nip += 4;
|
10914 | 3fc6c082 | bellard | table = env->opcodes; |
10915 | 2e70f6ef | pbrook | num_insns++; |
10916 | 79aceca5 | bellard | handler = table[opc1(ctx.opcode)]; |
10917 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
10918 | 79aceca5 | bellard | table = ind_table(handler); |
10919 | 79aceca5 | bellard | handler = table[opc2(ctx.opcode)]; |
10920 | 79aceca5 | bellard | if (is_indirect_opcode(handler)) {
|
10921 | 79aceca5 | bellard | table = ind_table(handler); |
10922 | 79aceca5 | bellard | handler = table[opc3(ctx.opcode)]; |
10923 | 79aceca5 | bellard | } |
10924 | 79aceca5 | bellard | } |
10925 | 79aceca5 | bellard | /* Is opcode *REALLY* valid ? */
|
10926 | 76a66253 | j_mayer | if (unlikely(handler->handler == &gen_invalid)) {
|
10927 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
10928 | 93fcfe39 | aliguori | qemu_log("invalid/unsupported opcode: "
|
10929 | 90e189ec | Blue Swirl | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
10930 | 90e189ec | Blue Swirl | opc1(ctx.opcode), opc2(ctx.opcode), |
10931 | 90e189ec | Blue Swirl | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
10932 | 4b3686fa | bellard | } |
10933 | 76a66253 | j_mayer | } else {
|
10934 | 70560da7 | Fabien Chouteau | uint32_t inval; |
10935 | 70560da7 | Fabien Chouteau | |
10936 | 70560da7 | Fabien Chouteau | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
|
10937 | 70560da7 | Fabien Chouteau | inval = handler->inval2; |
10938 | 70560da7 | Fabien Chouteau | } else {
|
10939 | 70560da7 | Fabien Chouteau | inval = handler->inval1; |
10940 | 70560da7 | Fabien Chouteau | } |
10941 | 70560da7 | Fabien Chouteau | |
10942 | 70560da7 | Fabien Chouteau | if (unlikely((ctx.opcode & inval) != 0)) { |
10943 | 93fcfe39 | aliguori | if (qemu_log_enabled()) {
|
10944 | 93fcfe39 | aliguori | qemu_log("invalid bits: %08x for opcode: "
|
10945 | 90e189ec | Blue Swirl | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
10946 | 70560da7 | Fabien Chouteau | ctx.opcode & inval, opc1(ctx.opcode), |
10947 | 90e189ec | Blue Swirl | opc2(ctx.opcode), opc3(ctx.opcode), |
10948 | 90e189ec | Blue Swirl | ctx.opcode, ctx.nip - 4);
|
10949 | 76a66253 | j_mayer | } |
10950 | e06fcd75 | aurel32 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
10951 | 4b3686fa | bellard | break;
|
10952 | 79aceca5 | bellard | } |
10953 | 79aceca5 | bellard | } |
10954 | 4b3686fa | bellard | (*(handler->handler))(&ctx); |
10955 | 76a66253 | j_mayer | #if defined(DO_PPC_STATISTICS)
|
10956 | 76a66253 | j_mayer | handler->count++; |
10957 | 76a66253 | j_mayer | #endif
|
10958 | 9a64fbe4 | bellard | /* Check trace mode exceptions */
|
10959 | 8cbcb4fa | aurel32 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
|
10960 | 8cbcb4fa | aurel32 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && |
10961 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_SYSCALL && |
10962 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_TRAP && |
10963 | 8cbcb4fa | aurel32 | ctx.exception != POWERPC_EXCP_BRANCH)) { |
10964 | e06fcd75 | aurel32 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
10965 | d26bfc9a | j_mayer | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
10966 | ed2803da | Andreas Färber | (cs->singlestep_enabled) || |
10967 | 1b530a6d | aurel32 | singlestep || |
10968 | 2e70f6ef | pbrook | num_insns >= max_insns)) { |
10969 | d26bfc9a | j_mayer | /* if we reach a page boundary or are single stepping, stop
|
10970 | d26bfc9a | j_mayer | * generation
|
10971 | d26bfc9a | j_mayer | */
|
10972 | 8dd4983c | bellard | break;
|
10973 | 76a66253 | j_mayer | } |
10974 | 3fc6c082 | bellard | } |
10975 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
10976 | 2e70f6ef | pbrook | gen_io_end(); |
10977 | e1833e1f | j_mayer | if (ctx.exception == POWERPC_EXCP_NONE) {
|
10978 | c1942362 | bellard | gen_goto_tb(&ctx, 0, ctx.nip);
|
10979 | e1833e1f | j_mayer | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
10980 | ed2803da | Andreas Färber | if (unlikely(cs->singlestep_enabled)) {
|
10981 | e06fcd75 | aurel32 | gen_debug_exception(ctxp); |
10982 | 8cbcb4fa | aurel32 | } |
10983 | 76a66253 | j_mayer | /* Generate the return instruction */
|
10984 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
10985 | 9a64fbe4 | bellard | } |
10986 | 806f352d | Peter Maydell | gen_tb_end(tb, num_insns); |
10987 | efd7f486 | Evgeny Voevodin | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
10988 | 76a66253 | j_mayer | if (unlikely(search_pc)) {
|
10989 | 92414b31 | Evgeny Voevodin | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
10990 | 9a64fbe4 | bellard | lj++; |
10991 | 9a64fbe4 | bellard | while (lj <= j)
|
10992 | ab1103de | Evgeny Voevodin | tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
10993 | 9a64fbe4 | bellard | } else {
|
10994 | 046d6672 | bellard | tb->size = ctx.nip - pc_start; |
10995 | 2e70f6ef | pbrook | tb->icount = num_insns; |
10996 | 9a64fbe4 | bellard | } |
10997 | d9bce9d9 | j_mayer | #if defined(DEBUG_DISAS)
|
10998 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
10999 | 76a66253 | j_mayer | int flags;
|
11000 | 237c0af0 | j_mayer | flags = env->bfd_mach; |
11001 | 76db3ba4 | aurel32 | flags |= ctx.le_mode << 16;
|
11002 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
11003 | f4359b9f | Blue Swirl | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
11004 | 93fcfe39 | aliguori | qemu_log("\n");
|
11005 | 9fddaa0c | bellard | } |
11006 | 79aceca5 | bellard | #endif
|
11007 | 79aceca5 | bellard | } |
11008 | 79aceca5 | bellard | |
11009 | 1328c2bf | Andreas Färber | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
11010 | 79aceca5 | bellard | { |
11011 | 213fe1f5 | Andreas Färber | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
|
11012 | 79aceca5 | bellard | } |
11013 | 79aceca5 | bellard | |
11014 | 1328c2bf | Andreas Färber | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
11015 | 79aceca5 | bellard | { |
11016 | 213fe1f5 | Andreas Färber | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
|
11017 | 79aceca5 | bellard | } |
11018 | d2856f1a | aurel32 | |
11019 | 1328c2bf | Andreas Färber | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
11020 | d2856f1a | aurel32 | { |
11021 | 25983cad | Evgeny Voevodin | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
11022 | d2856f1a | aurel32 | } |