Archipelago » qemu

/*

 *  PowerPC emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *  Copyright (C) 2011 Freescale Semiconductor, Inc.

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include "cpu.h"

#include "disas/disas.h"

#include "tcg-op.h"

#include "qemu/host-utils.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

#define CPU_SINGLE_STEP 0x1

#define CPU_BRANCH_STEP 0x2

#define GDBSTUB_SINGLE_STEP 0x4

/* Include definitions for instructions classes and implementations flags */

//#define PPC_DEBUG_DISAS

//#define DO_PPC_STATISTICS

#ifdef PPC_DEBUG_DISAS

#  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)

#else

#  define LOG_DISAS(...) do { } while (0)

#endif

/*****************************************************************************/

/* Code translation helpers                                                  */

/* global register indexes */

static TCGv_ptr cpu_env;

static char cpu_reg_names[10*3 + 22*4 /* GPR */

#if !defined(TARGET_PPC64)

    + 10*4 + 22*5 /* SPE GPRh */

#endif

    + 10*4 + 22*5 /* FPR */

    + 2*(10*6 + 22*7) /* AVRh, AVRl */

    + 10*5 + 22*6 /* VSR */

    + 8*5 /* CRF */];

static TCGv cpu_gpr[32];

#if !defined(TARGET_PPC64)

static TCGv cpu_gprh[32];

#endif

static TCGv_i64 cpu_fpr[32];

static TCGv_i64 cpu_avrh[32], cpu_avrl[32];

static TCGv_i64 cpu_vsr[32];

static TCGv_i32 cpu_crf[8];

static TCGv cpu_nip;

static TCGv cpu_msr;

static TCGv cpu_ctr;

static TCGv cpu_lr;

#if defined(TARGET_PPC64)

static TCGv cpu_cfar;

#endif

static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;

static TCGv cpu_reserve;

static TCGv cpu_fpscr;

static TCGv_i32 cpu_access_type;

#include "exec/gen-icount.h"

void ppc_translate_init(void)

{

    int i;

    char* p;

    size_t cpu_reg_names_size;

    static int done_init = 0;

    if (done_init)

        return;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    p = cpu_reg_names;

    cpu_reg_names_size = sizeof(cpu_reg_names);

    for (i = 0; i < 8; i++) {

        snprintf(p, cpu_reg_names_size, "crf%d", i);

        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                            offsetof(CPUPPCState, crf[i]), p);

        p += 5;

        cpu_reg_names_size -= 5;

    }

    for (i = 0; i < 32; i++) {

        snprintf(p, cpu_reg_names_size, "r%d", i);

        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,

                                        offsetof(CPUPPCState, gpr[i]), p);

        p += (i < 10) ? 3 : 4;

        cpu_reg_names_size -= (i < 10) ? 3 : 4;

#if !defined(TARGET_PPC64)

        snprintf(p, cpu_reg_names_size, "r%dH", i);

        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                             offsetof(CPUPPCState, gprh[i]), p);

        p += (i < 10) ? 4 : 5;

        cpu_reg_names_size -= (i < 10) ? 4 : 5;

#endif

        snprintf(p, cpu_reg_names_size, "fp%d", i);

        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                            offsetof(CPUPPCState, fpr[i]), p);

        p += (i < 10) ? 4 : 5;

        cpu_reg_names_size -= (i < 10) ? 4 : 5;

        snprintf(p, cpu_reg_names_size, "avr%dH", i);

#ifdef HOST_WORDS_BIGENDIAN

        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                             offsetof(CPUPPCState, avr[i].u64[0]), p);

#else

        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                             offsetof(CPUPPCState, avr[i].u64[1]), p);

#endif

        p += (i < 10) ? 6 : 7;

        cpu_reg_names_size -= (i < 10) ? 6 : 7;

        snprintf(p, cpu_reg_names_size, "avr%dL", i);

#ifdef HOST_WORDS_BIGENDIAN

        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                             offsetof(CPUPPCState, avr[i].u64[1]), p);

#else

        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                             offsetof(CPUPPCState, avr[i].u64[0]), p);

#endif

        p += (i < 10) ? 6 : 7;

        cpu_reg_names_size -= (i < 10) ? 6 : 7;

        snprintf(p, cpu_reg_names_size, "vsr%d", i);

        cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                             offsetof(CPUPPCState, vsr[i]), p);

        p += (i < 10) ? 5 : 6;

        cpu_reg_names_size -= (i < 10) ? 5 : 6;

    }

    cpu_nip = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUPPCState, nip), "nip");

    cpu_msr = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUPPCState, msr), "msr");

    cpu_ctr = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUPPCState, ctr), "ctr");

    cpu_lr = tcg_global_mem_new(TCG_AREG0,

                                offsetof(CPUPPCState, lr), "lr");

#if defined(TARGET_PPC64)

    cpu_cfar = tcg_global_mem_new(TCG_AREG0,

                                  offsetof(CPUPPCState, cfar), "cfar");

#endif

    cpu_xer = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUPPCState, xer), "xer");

    cpu_so = tcg_global_mem_new(TCG_AREG0,

                                offsetof(CPUPPCState, so), "SO");

    cpu_ov = tcg_global_mem_new(TCG_AREG0,

                                offsetof(CPUPPCState, ov), "OV");

    cpu_ca = tcg_global_mem_new(TCG_AREG0,

                                offsetof(CPUPPCState, ca), "CA");

    cpu_reserve = tcg_global_mem_new(TCG_AREG0,

                                     offsetof(CPUPPCState, reserve_addr),

                                     "reserve_addr");

    cpu_fpscr = tcg_global_mem_new(TCG_AREG0,

                                   offsetof(CPUPPCState, fpscr), "fpscr");

    cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,

                                             offsetof(CPUPPCState, access_type), "access_type");

    done_init = 1;

}

/* internal defines */

typedef struct DisasContext {

    struct TranslationBlock *tb;

    target_ulong nip;

    uint32_t opcode;

    uint32_t exception;

    /* Routine used to access memory */

    int mem_idx;

    int access_type;

    /* Translation flags */

    int le_mode;

#if defined(TARGET_PPC64)

    int sf_mode;

    int has_cfar;

#endif

    int fpu_enabled;

    int altivec_enabled;

    int vsx_enabled;

    int spe_enabled;

    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */

    int singlestep_enabled;

    uint64_t insns_flags;

    uint64_t insns_flags2;

} DisasContext;

/* True when active word size < size of target_long.  */

#ifdef TARGET_PPC64

# define NARROW_MODE(C)  (!(C)->sf_mode)

#else

# define NARROW_MODE(C)  0

#endif

struct opc_handler_t {

    /* invalid bits for instruction 1 (Rc(opcode) == 0) */

    uint32_t inval1;

    /* invalid bits for instruction 2 (Rc(opcode) == 1) */

    uint32_t inval2;

    /* instruction type */

    uint64_t type;

    /* extended instruction type */

    uint64_t type2;

    /* handler */

    void (*handler)(DisasContext *ctx);

#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)

    const char *oname;

#endif

#if defined(DO_PPC_STATISTICS)

    uint64_t count;

#endif

};

static inline void gen_reset_fpstatus(void)

{

    gen_helper_reset_fpstatus(cpu_env);

}

static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)

{

    TCGv_i32 t0 = tcg_temp_new_i32();

    if (set_fprf != 0) {

        /* This case might be optimized later */

        tcg_gen_movi_i32(t0, 1);

        gen_helper_compute_fprf(t0, cpu_env, arg, t0);

        if (unlikely(set_rc)) {

            tcg_gen_mov_i32(cpu_crf[1], t0);

        }

        gen_helper_float_check_status(cpu_env);

    } else if (unlikely(set_rc)) {

        /* We always need to compute fpcc */

        tcg_gen_movi_i32(t0, 0);

        gen_helper_compute_fprf(t0, cpu_env, arg, t0);

        tcg_gen_mov_i32(cpu_crf[1], t0);

    }

    tcg_temp_free_i32(t0);

}

static inline void gen_set_access_type(DisasContext *ctx, int access_type)

{

    if (ctx->access_type != access_type) {

        tcg_gen_movi_i32(cpu_access_type, access_type);

        ctx->access_type = access_type;

    }

}

static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)

{

    if (NARROW_MODE(ctx)) {

        nip = (uint32_t)nip;

    }

    tcg_gen_movi_tl(cpu_nip, nip);

}

static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)

{

    TCGv_i32 t0, t1;

    if (ctx->exception == POWERPC_EXCP_NONE) {

        gen_update_nip(ctx, ctx->nip);

    }

    t0 = tcg_const_i32(excp);

    t1 = tcg_const_i32(error);

    gen_helper_raise_exception_err(cpu_env, t0, t1);

    tcg_temp_free_i32(t0);

    tcg_temp_free_i32(t1);

    ctx->exception = (excp);

}

static inline void gen_exception(DisasContext *ctx, uint32_t excp)

{

    TCGv_i32 t0;

    if (ctx->exception == POWERPC_EXCP_NONE) {

        gen_update_nip(ctx, ctx->nip);

    }

    t0 = tcg_const_i32(excp);

    gen_helper_raise_exception(cpu_env, t0);

    tcg_temp_free_i32(t0);

    ctx->exception = (excp);

}

static inline void gen_debug_exception(DisasContext *ctx)

{

    TCGv_i32 t0;

    if ((ctx->exception != POWERPC_EXCP_BRANCH) &&

        (ctx->exception != POWERPC_EXCP_SYNC)) {

        gen_update_nip(ctx, ctx->nip);

    }

    t0 = tcg_const_i32(EXCP_DEBUG);

    gen_helper_raise_exception(cpu_env, t0);

    tcg_temp_free_i32(t0);

}

static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)

{

    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);

}

/* Stop translation */

static inline void gen_stop_exception(DisasContext *ctx)

{

    gen_update_nip(ctx, ctx->nip);

    ctx->exception = POWERPC_EXCP_STOP;

}

/* No need to update nip here, as execution flow will change */

static inline void gen_sync_exception(DisasContext *ctx)

{

    ctx->exception = POWERPC_EXCP_SYNC;

}

#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \

GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)

#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2)             \

GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)

#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \

GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)

#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2)      \

GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)

typedef struct opcode_t {

    unsigned char opc1, opc2, opc3;

#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */

    unsigned char pad[5];

#else

    unsigned char pad[1];

#endif

    opc_handler_t handler;

    const char *oname;

} opcode_t;

/*****************************************************************************/

/***                           Instruction decoding                        ***/

#define EXTRACT_HELPER(name, shift, nb)                                       \

static inline uint32_t name(uint32_t opcode)                                  \

{                                                                             \

    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \

}

#define EXTRACT_SHELPER(name, shift, nb)                                      \

static inline int32_t name(uint32_t opcode)                                   \

{                                                                             \

    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \

}

#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2)                  \

static inline uint32_t name(uint32_t opcode)                                  \

{                                                                             \

    return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |             \

            ((opcode >> (shift2)) & ((1 << (nb2)) - 1));                      \

}

/* Opcode part 1 */

EXTRACT_HELPER(opc1, 26, 6);

/* Opcode part 2 */

EXTRACT_HELPER(opc2, 1, 5);

/* Opcode part 3 */

EXTRACT_HELPER(opc3, 6, 5);

/* Update Cr0 flags */

EXTRACT_HELPER(Rc, 0, 1);

/* Destination */

EXTRACT_HELPER(rD, 21, 5);

/* Source */

EXTRACT_HELPER(rS, 21, 5);

/* First operand */

EXTRACT_HELPER(rA, 16, 5);

/* Second operand */

EXTRACT_HELPER(rB, 11, 5);

/* Third operand */

EXTRACT_HELPER(rC, 6, 5);

/***                               Get CRn                                 ***/

EXTRACT_HELPER(crfD, 23, 3);

EXTRACT_HELPER(crfS, 18, 3);

EXTRACT_HELPER(crbD, 21, 5);

EXTRACT_HELPER(crbA, 16, 5);

EXTRACT_HELPER(crbB, 11, 5);

/* SPR / TBL */

EXTRACT_HELPER(_SPR, 11, 10);

static inline uint32_t SPR(uint32_t opcode)

{

    uint32_t sprn = _SPR(opcode);

    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);

}

/***                              Get constants                            ***/

EXTRACT_HELPER(IMM, 12, 8);

/* 16 bits signed immediate value */

EXTRACT_SHELPER(SIMM, 0, 16);

/* 16 bits unsigned immediate value */

EXTRACT_HELPER(UIMM, 0, 16);

/* 5 bits signed immediate value */

EXTRACT_HELPER(SIMM5, 16, 5);

/* 5 bits signed immediate value */

EXTRACT_HELPER(UIMM5, 16, 5);

/* Bit count */

EXTRACT_HELPER(NB, 11, 5);

/* Shift count */

EXTRACT_HELPER(SH, 11, 5);

/* Vector shift count */

EXTRACT_HELPER(VSH, 6, 4);

/* Mask start */

EXTRACT_HELPER(MB, 6, 5);

/* Mask end */

EXTRACT_HELPER(ME, 1, 5);

/* Trap operand */

EXTRACT_HELPER(TO, 21, 5);

EXTRACT_HELPER(CRM, 12, 8);

EXTRACT_HELPER(SR, 16, 4);

/* mtfsf/mtfsfi */

EXTRACT_HELPER(FPBF, 23, 3);

EXTRACT_HELPER(FPIMM, 12, 4);

EXTRACT_HELPER(FPL, 25, 1);

EXTRACT_HELPER(FPFLM, 17, 8);

EXTRACT_HELPER(FPW, 16, 1);

/***                            Jump target decoding                       ***/

/* Displacement */

EXTRACT_SHELPER(d, 0, 16);

/* Immediate address */

static inline target_ulong LI(uint32_t opcode)

{

    return (opcode >> 0) & 0x03FFFFFC;

}

static inline uint32_t BD(uint32_t opcode)

{

    return (opcode >> 0) & 0xFFFC;

}

EXTRACT_HELPER(BO, 21, 5);

EXTRACT_HELPER(BI, 16, 5);

/* Absolute/relative address */

EXTRACT_HELPER(AA, 1, 1);

/* Link */

EXTRACT_HELPER(LK, 0, 1);

/* Create a mask between <start> and <end> bits */

static inline target_ulong MASK(uint32_t start, uint32_t end)

{

    target_ulong ret;

#if defined(TARGET_PPC64)

    if (likely(start == 0)) {

        ret = UINT64_MAX << (63 - end);

    } else if (likely(end == 63)) {

        ret = UINT64_MAX >> start;

    }

#else

    if (likely(start == 0)) {

        ret = UINT32_MAX << (31  - end);

    } else if (likely(end == 31)) {

        ret = UINT32_MAX >> start;

    }

#endif

    else {

        ret = (((target_ulong)(-1ULL)) >> (start)) ^

            (((target_ulong)(-1ULL) >> (end)) >> 1);

        if (unlikely(start > end))

            return ~ret;

    }

    return ret;

}

EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);

EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);

EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);

EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);

EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);

EXTRACT_HELPER(DM, 8, 2);

EXTRACT_HELPER(UIM, 16, 2);

EXTRACT_HELPER(SHW, 8, 2);

/*****************************************************************************/

/* PowerPC instructions table                                                */

#if defined(DO_PPC_STATISTICS)

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \

{                                                                             \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval1  = invl,                                                      \

        .type = _typ,                                                         \

        .type2 = _typ2,                                                       \

        .handler = &gen_##name,                                               \

        .oname = stringify(name),                                             \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \

{                                                                             \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval1  = invl1,                                                     \

        .inval2  = invl2,                                                     \

        .type = _typ,                                                         \

        .type2 = _typ2,                                                       \

        .handler = &gen_##name,                                               \

        .oname = stringify(name),                                             \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \

{                                                                             \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval1  = invl,                                                      \

        .type = _typ,                                                         \

        .type2 = _typ2,                                                       \

        .handler = &gen_##name,                                               \

        .oname = onam,                                                        \

    },                                                                        \

    .oname = onam,                                                            \

}

#else

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \

{                                                                             \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval1  = invl,                                                      \

        .type = _typ,                                                         \

        .type2 = _typ2,                                                       \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \

{                                                                             \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval1  = invl1,                                                     \

        .inval2  = invl2,                                                     \

        .type = _typ,                                                         \

        .type2 = _typ2,                                                       \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \

{                                                                             \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval1  = invl,                                                      \

        .type = _typ,                                                         \

        .type2 = _typ2,                                                       \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = onam,                                                            \

}

#endif

/* SPR load/store helpers */

static inline void gen_load_spr(TCGv t, int reg)

{

    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));

}

static inline void gen_store_spr(int reg, TCGv t)

{

    tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));

}

/* Invalid instruction */

static void gen_invalid(DisasContext *ctx)

{

    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);

}

static opc_handler_t invalid_handler = {

    .inval1  = 0xFFFFFFFF,

    .inval2  = 0xFFFFFFFF,

    .type    = PPC_NONE,

    .type2   = PPC_NONE,

    .handler = gen_invalid,

};

/***                           Integer comparison                          ***/

static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)

{

    TCGv t0 = tcg_temp_new();

    TCGv_i32 t1 = tcg_temp_new_i32();

    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);

    tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);

    tcg_gen_trunc_tl_i32(t1, t0);

    tcg_gen_shli_i32(t1, t1, CRF_LT);

    tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);

    tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);

    tcg_gen_trunc_tl_i32(t1, t0);

    tcg_gen_shli_i32(t1, t1, CRF_GT);

    tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);

    tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);

    tcg_gen_trunc_tl_i32(t1, t0);

    tcg_gen_shli_i32(t1, t1, CRF_EQ);

    tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);

    tcg_temp_free(t0);

    tcg_temp_free_i32(t1);

}

static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)

{

    TCGv t0 = tcg_const_tl(arg1);

    gen_op_cmp(arg0, t0, s, crf);

    tcg_temp_free(t0);

}

static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)

{

    TCGv t0, t1;

    t0 = tcg_temp_new();

    t1 = tcg_temp_new();

    if (s) {

        tcg_gen_ext32s_tl(t0, arg0);

        tcg_gen_ext32s_tl(t1, arg1);

    } else {

        tcg_gen_ext32u_tl(t0, arg0);

        tcg_gen_ext32u_tl(t1, arg1);

    }

    gen_op_cmp(t0, t1, s, crf);

    tcg_temp_free(t1);

    tcg_temp_free(t0);

}

static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)

{

    TCGv t0 = tcg_const_tl(arg1);

    gen_op_cmp32(arg0, t0, s, crf);

    tcg_temp_free(t0);

}

static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)

{

    if (NARROW_MODE(ctx)) {

        gen_op_cmpi32(reg, 0, 1, 0);

    } else {

        gen_op_cmpi(reg, 0, 1, 0);

    }

}

/* cmp */

static void gen_cmp(DisasContext *ctx)

{

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                   1, crfD(ctx->opcode));

    } else {

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                     1, crfD(ctx->opcode));

    }

}

/* cmpi */

static void gen_cmpi(DisasContext *ctx)

{

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

                    1, crfD(ctx->opcode));

    } else {

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

                      1, crfD(ctx->opcode));

    }

}

/* cmpl */

static void gen_cmpl(DisasContext *ctx)

{

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                   0, crfD(ctx->opcode));

    } else {

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                     0, crfD(ctx->opcode));

    }

}

/* cmpli */

static void gen_cmpli(DisasContext *ctx)

{

    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

                    0, crfD(ctx->opcode));

    } else {

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

                      0, crfD(ctx->opcode));

    }

}

/* isel (PowerPC 2.03 specification) */

static void gen_isel(DisasContext *ctx)

{

    int l1, l2;

    uint32_t bi = rC(ctx->opcode);

    uint32_t mask;

    TCGv_i32 t0;

    l1 = gen_new_label();

    l2 = gen_new_label();

    mask = 1 << (3 - (bi & 0x03));

    t0 = tcg_temp_new_i32();

    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);

    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);

    if (rA(ctx->opcode) == 0)

        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);

    else

        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);

    gen_set_label(l2);

    tcg_temp_free_i32(t0);

}

/* cmpb: PowerPC 2.05 specification */

static void gen_cmpb(DisasContext *ctx)

{

    gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],

                    cpu_gpr[rB(ctx->opcode)]);

}

/***                           Integer arithmetic                          ***/

static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,

                                           TCGv arg1, TCGv arg2, int sub)

{

    TCGv t0 = tcg_temp_new();

    tcg_gen_xor_tl(cpu_ov, arg0, arg2);

    tcg_gen_xor_tl(t0, arg1, arg2);

    if (sub) {

        tcg_gen_and_tl(cpu_ov, cpu_ov, t0);

    } else {

        tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);

    }

    tcg_temp_free(t0);

    if (NARROW_MODE(ctx)) {

        tcg_gen_ext32s_tl(cpu_ov, cpu_ov);

    }

    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);

    tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);

}

/* Common add function */

static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,

                                    TCGv arg2, bool add_ca, bool compute_ca,

                                    bool compute_ov, bool compute_rc0)

{

    TCGv t0 = ret;

    if (compute_ca || compute_ov) {

        t0 = tcg_temp_new();

    }

    if (compute_ca) {

        if (NARROW_MODE(ctx)) {

            /* Caution: a non-obvious corner case of the spec is that we

               must produce the *entire* 64-bit addition, but produce the

               carry into bit 32.  */

            TCGv t1 = tcg_temp_new();

            tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */

            tcg_gen_add_tl(t0, arg1, arg2);

            if (add_ca) {

                tcg_gen_add_tl(t0, t0, cpu_ca);

            }

            tcg_gen_xor_tl(cpu_ca, t0, t1);        /* bits changed w/ carry */

            tcg_temp_free(t1);

            tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);   /* extract bit 32 */

            tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);

        } else {

            TCGv zero = tcg_const_tl(0);

            if (add_ca) {

                tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);

                tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);

            } else {

                tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);

            }

            tcg_temp_free(zero);

        }

    } else {

        tcg_gen_add_tl(t0, arg1, arg2);

        if (add_ca) {

            tcg_gen_add_tl(t0, t0, cpu_ca);

        }

    }

    if (compute_ov) {

        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);

    }

    if (unlikely(compute_rc0)) {

        gen_set_Rc0(ctx, t0);

    }

    if (!TCGV_EQUAL(t0, ret)) {

        tcg_gen_mov_tl(ret, t0);

        tcg_temp_free(t0);

    }

}

/* Add functions with two operands */

#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \

static void glue(gen_, name)(DisasContext *ctx)                               \

{                                                                             \

    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \

                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \

                     add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \

}

/* Add functions with one operand and one immediate */

#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \

                                add_ca, compute_ca, compute_ov)               \

static void glue(gen_, name)(DisasContext *ctx)                               \

{                                                                             \

    TCGv t0 = tcg_const_tl(const_val);                                        \

    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \

                     cpu_gpr[rA(ctx->opcode)], t0,                            \

                     add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \

    tcg_temp_free(t0);                                                        \

}

/* add  add.  addo  addo. */

GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)

GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)

/* addc  addc.  addco  addco. */

GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)

GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)

/* adde  adde.  addeo  addeo. */

GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)

GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)

/* addme  addme.  addmeo  addmeo.  */

GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)

GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)

/* addze  addze.  addzeo  addzeo.*/

GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)

GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)

/* addi */

static void gen_addi(DisasContext *ctx)

{

    target_long simm = SIMM(ctx->opcode);

    if (rA(ctx->opcode) == 0) {