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target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
This patch adds the byte and halfword variants of the Store Conditionalinstructions. A common macro is introduced and the existing implementationsof stwcx. and stdcx. are refactored to use this macro....
target-ppc: Add ISA2.06 Float to Integer Instructions
This patch adds the four floating point to integer conversion instructionsintroduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward...
target-ppc: Add ISA 2.06 divwe[o] Instructions
This patch addes the signed Divide Word Extended instructionswhich were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add ISA2.06 lbarx, lharx Instructions
This patch adds the byte and halfword variants of the Load andReserve instructions. Since there is much commonality amongall forms of Load and Reserve, a macro is provided and the existingimplementations of lwarx and ldarx are refactoried to use this...
target-ppc: Add ISA2.06 divdeu[o] Instructions
This patch adds the Divide Doubleword Extended Unsignedinstructions. This instruction requires dividing a 128-bitvalue by a 64 bit value. Since 128 bit integer division isnot supported in TCG, a helper is used. An architecture...
target-ppc: Add ISA2.06 divde[o] Instructions
This patch adds the Divide Doubleword Extended instructions.The implementation builds on the unsigned helper provided inthe previous patch.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-ppc: Add ISA 2.06 divweu[o] Instructions
This patch addes the Unsigned Divide Word Extended instructionswhich were introduced in Power ISA 2.06B.
target-ppc: Scalar Non-Signalling Conversions
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision Non-Signalling (xscvspdpn) - VSX Scalar Convert Double Precision to Single Precision...
target-ppc: Add ISA2.06 bpermd Instruction
This patch adds the Bit Permute Doubleword (bpermd) instruction,which was introduced in Power ISA 2.06 as part of the base 64-bitarchitecture.
target-ppc: Move To/From VSR Instructions
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). Theseinstructions are unusual in that they are considered a floatingpoint instruction if the indexed VSR is in the first half of the...
target-ppc: Floating Merge Word Instructions
This patch adds the Floating Merge Even Word (fmrgew) and FloatingMerge Odd Word (fmrgow) instructions.
target-ppc: Scalar Round to Single Precision
This patch adds the VSX Scalar Round to Single Precision (xsrsp)instruction.
target-ppc: VSX Stage 4: add xsrsqrtesp
This patch adds the VSX Scalar Reciprocal Square Root EstimateSingle Precision (xsrsqrtesp) instruction.
The existing VSX_RSQRTE() macro is modified to support roundingof the intermediate double-precision result to single precision....
target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
This patch adds the Single Precision VSX Scalar Fused Multiply-Addinstructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,xsnmaddmsp, xsnmsubasp, xsnmsubmsp.
The existing VSX_MADD() macro is modified to support rounding of the...
target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp
This patch adds the VSX Scalar Convert Unsigned Integer Doublewordto Floating Point Format and Round to Single Precision (xscvuxdsp)and VSX Scalar Convert Signed Integer Douglbeword to Floating Point...
target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc
This patchs adds the VSX Logical instructions that are new withISA V2.07:
- VSX Logical Equivalence (xxleqv) - VSX Logical NAND (xxlnand) - VSX Logical ORC (xxlorc)
Signed-off-by: Tom Musta <tommusta@gmail.com>...
target-ppc: VSX Stage 4: Add xsdivsp
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)instruction.
The existing VSX_DIV macro is modified to support rounding of theintermediate double precision result to single precision.
target-ppc: VSX Stage 4: Add xsresp
This patch adds the VSX Scalar Reciprocal Estimate Single Precision(xsresp) instruction.
The existing VSX_RE macro is modified to support rounding of theintermediate double precision result to single precision.
target-ppc: VSX Stage 4: Add xssqrtsp
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)instruction.
The existing VSX_SQRT() macro is modified to support rounding of theintermediate double-precision result to single-precision.
target-ppc: VSX Stage 4: Add stxsiwx and stxsspx
This patch adds two store scalar instructions:
- Store VSX Scalar as Integer Word Indexed (stxsiwx) - Store VSX Scalar Single-Precision Indexed (stxsspx)
target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) andVSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the roundingof the (intermediate) result to single-precision....
target-ppc: VSX Stage 4: Add xsmulsp
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)instruction.
The existing VSX_MUL macro is modified to support rounding of theintermediate result to single precision.
target-ppc: VSX Stage 4: Refactor lxsdx
This patch refactors the lxsdx generator. Resuable code is isolatedinto a macro. The macro will be used in subsequent patches in thisseries to implement other scalar load instructions.
target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
This patch adds the scalar load instructions introduced in ISAV2.07:
- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax) - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx) - Load VSX Scalar Single-Precision Indexed (lxsspx)...
target-ppc: VSX Stage 4: Refactor stxsdx
This patch refactors the stxsdx instruction. Reusable code isextracted into a macro which will be used in subsequent patchesin this series.
target-ppc: Add VSX ISA2.06 Integer Conversion Instructions
This patch adds the VSX Integer Conversion instructions defined byV2.06 of the PowerPC ISA:
- xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws...
target-ppc: Add VSX Rounding Instructions
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz...
target-ppc: Add VSX xmax/xmin Instructions
This patch adds the VSX floating point maximum and minimuminstructions:
- xsmaxdp, xvmaxdp, xvmaxsp - xsmindp, xvmindp, xvminsp
Because of the Power ISA definitions of maximum and minimumon various boundary cases, the standard softfloat comparison...
target-ppc: Add VSX Vector Compare Instructions
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.] - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions
This patch adds the VSX instructions that convert between floatingpoint formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
target-ppc: Add VSX ISA2.06 xtsqrt Instructions
This patch adds the VSX floating point test for software squareroot instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,xvtsqrtdp, xvtsqrtsp.
target-ppc: Add VSX ISA2.06 Multiply Add Instructions
This patch adds the VSX floating point multiply/add instructionsdefined by V2.06 of the PowerPC ISA:
- xsmaddadp, xvmaddadp, xvmaddasp - xsmaddmdp, xvmaddmdp, xvmaddmsp - xsmsubadp, xvmsubadp, xvmsubasp...
target-ppc: Add VSX xscmp*dp Instructions
This patch adds the VSX scalar floating point compare orderedand unordered instructions.
target-ppc: Add VSX ISA2.06 xre Instructions
This patch adds the VSX floating point reciprocal estimate instructionsdefined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
target-ppc: Add VSX ISA2.06 xsqrt Instructions
This patch adds the VSX floating point square root instructionsdefined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
target-ppc: Add VSX ISA2.06 xrsqrte Instructions
This patch adds the VSX floating point reciprocal square rootestimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,xvrsqrtedp, xvrsqrtesp.
target-ppc: Add VSX ISA2.06 xtdiv Instructions
This patch adds the VSX floating point test for software divideinstructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,and xvtdivsp.
target-ppc: Add VSX ISA2.06 xadd/xsub Instructions
This patch adds the floating point addition and subtractioninstructions defined by V2.06 of the PowerPC ISA: xssubdp,xvsubdp and xvsubsp.
target-ppc: Add VSX ISA2.06 xmul Instructions
This patch adds the VSX floating point multiply instructions definedby V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
target-ppc: Add VSX ISA2.06 xdiv Instructions
This patch adds the VSX floating point divide instructions definedby V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
target-ppc: General Support for VSX Helpers
This patch adds general support that will be used by the VSX helperroutines:
- a union describing the various VSR subfields. - access routines to get and set VSRs - VSX decoders - a general routine to generate a handler that invokes a VSX...
target-ppc: dump DAR and DSISR
The DAR and DSISR can be very useful when debugging issues, so addthem to ppc_cpu_dump_state. We had another bug in this area: allof the v2.06 MMU types were missing.
Signed-off-by: Anton Blanchard <anton@samba.org>Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Fix compilation with TCG debug
The recent VSX patches broken compilation of QEMU when configuratedwith --enable-debug, as it was treating "target long" TCG variablesas "i64" which is not true for 32bit targets.
This patch fixes all the places that the compiler has found to use...
Add xxsldwi
This patch adds the VSX Shift Left Double by Word Immediate(xxsldwi) instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Add xxspltw
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate fieldand consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Add xxsel
This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xCinstruction decoder is added.
The xxsel instruction is massively overloaded in the opcodetable since only bits 26 and 27 are opcode bits. This...
Add Power7 VSX Logical Instructions
This patch adds the VSX logical instructions that are definedby the Version 2.06 Power ISA (aka Power7):
- xxland - xxlandc - xxlor - xxlxor - xxlnor
Add xxmrgh/xxmrgl
This patch adds the VSX Merge High Word and VSX Merge Low Wordinstructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Add VSX Vector Move Instructions
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision...
Add VSX Scalar Move Instructions
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision)...
Add stxvw4x
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Add stxsdx
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)instruction.
Add lxvw4x
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>...
Add lxvdsx
This patch adds the Load VSX Vector Doubleword & Splat Indexed(lxvdsx) instruction.
Add lxsdx
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)instruction.
The lower 8 bytes of the target register are undefined; thisimplementation leaves those bytes unaltered.
Add xxpermdi
This patch adds the xxpermdi instruction. The instructionuses bits 22, 23, 29 and 30 for non-opcode fields (DM, AXand BX). This results in overloading of the opcode tablewith aliases, which can be seen in the GEN_XX3FORM_DMmacro.
Add stxvd2x
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>Signed-off-by: Anton Blanchard <anton@samba.org>Signed-off-by: Alexander Graf <agraf@suse.de>
Add lxvd2x
This patch adds the lxvd2x instruction.
Add VSR to Global Registers
This patch adds VSX VSRs to the the list of global register indices.More specifically, it adds the lower halves of the first 32 VSRs tothe list of global register indices. The upper halves of the first32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs...
Add VSX Instruction Decoders
This patch adds decoders for the VSX fields XT, XS, XA, XB andDM. The first four are split fields and a general helper forthese types of fields is also added.
Signed-off-by: Tom Musta <tommusta@gmail.com>Signed-off-by: Anton Blanchard <anton@samba.org>...
Add MSR VSX and Associated Exception
This patch adds support for the VSX bit of the PowerPC MachineState Register (MSR) as well as the corresponding VSX Unavailableexception.
The VSX bit is added to the defined bits masks of the Power7 andPower8 CPU models....
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
cpu: Move cpu state syncs up into cpu_dump_state()
The x86 and ppc targets call cpu_synchronize_state() from their*_cpu_dump_state() callbacks to ensure that up to date state is dumpedwhen KVM is enabled (for example when a KVM internal error occurs)....
Merge branch 'tcg-next' of git://github.com/rth7680/qemu
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
target-ppc: fix bit extraction for FPBF and FPL
Bit extraction for the FP BF and L field of the MTFSFI and MTFSFinstructions is wrong and doesn't match the reference manual (whichexplain the bit number in big endian format). It has been broken incommit 7d08d85645def18eac2a9d672c1868a35e0bcf79....
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
kvm: Change cpu_synchronize_state() argument to CPUState
Change Monitor::mon_cpu to CPUState as well.
Reviewed-by: liguang <lig.fnst@cn.fujitsu.com>Acked-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
PPC: Depend behavior of cmp instructions only on instruction encoding
When running an L=1 cmp instruction on a 64bit PPC CPU with SF off, itstill behaves identical to what it does when SF is on. Remove the implicitdifference in the code.
Also, on most 32bit CPUs we should always treat the compare as 32bit...
PPC: Fix rldcl
The implementation for rldcl tried to always fetch itsparameters from the opcode, even though the opcode wasalready passed in in decoded and different forms.
Use the parameters instead, fixing rldcl.
Reported-by: Torbjorn Granlund <tg@gmplib.org>...
target-ppc: Fix invalid SPR read/write warnings
Invalid and privileged SPR warnings currently print the wrongaddress. While fixing that, also make it clear that we areprinting both the decimal and hexadecimal SPR number.
Before:
Trying to read invalid spr 896 380 at 0000000000000714...
target-ppc: slightly optimize lfiwax
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: emulate lfiwax instruction
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix tcg debug error]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate load doubleword pair instructions
Needed for Power ISA version 2.05 compliance. The check for odd registerpairs is done using the invalid bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate store doubleword pair instructions
target-ppc: add support for extended mtfsf/mtfsfi forms
Power ISA 2.05 adds support for extended mtfsf/mtfsfi form, with a newW field to select the upper part of the FPCSR register.
For that the helper is changed to handle 64-bit input values and mask with...
target-ppc: optimize fabs, fnabs, fneg
fabs, fnabs and fneg are just flipping the bit sign of an FP register,this can be implemented in TCG instead of using softfloat.
target-ppc: emulate cmpb instruction
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate prtyw and prtyd instructions
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>[agraf: fix 32-bit host compile, simplify code]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: emulate fcpsgn instruction
target-ppc: fix nego and subf*o instructions
The overflow computation of nego and subf*o instructions has been brokenin commit ffe30937. Contrary to other targets, the instruction is subtractfrom an not subtract on PowerPC.
This patch fixes the issue by using the correct argument in the xor...
target-ppc: Fix narrow-mode add/sub carry output
Broken in b5a73f8d8a57e940f9bbeb399a9e47897522ee9a, the carry itself wasfixed in 79482e5ab38a05ca8869040b0d8b8f451f16ff62. But we still need toproduce the full 64-bit addition.
Simplify the conditions at the top of the functions for when we need a...
target-ppc: Fix add and subf carry generation in narrow mode
The set of computations used in b5a73f8d8a57e940f9bbeb399a9e47897522ee9aare only valid if the current word size == target_long size. This failedto take ppc64 in 32-bit (narrow) mode into account....
target-ppc: Use NARROW_MODE macro for branches
Removing conditional compilation in the process.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Use NARROW_MODE macro for comparisons
target-ppc: Use NARROW_MODE macro for addresses
target-ppc: Use NARROW_MODE macro for tlbie
target-ppc: Remove vestigial PowerPC 620 support
The PowerPC 620 was the very first 64-bit PowerPC implementation, buthardly anyone ever actually used the chips. qemu notionally supports the620, but since we don't actually have code to implement the segment table,...
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-ppc: Fix SUBFE carry
While ~T0+T1+CF = T1-T0+CF-1 is true for the low 32-bits,it does not produce the correct carry-out to bit 33. Doexactly what the manual says.
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>...
target-ppc: Use setcond in gen_op_cmp
Which means that callers need not copy data into local tmps.
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: Compute addition overflow without branches
target-ppc: Compute addition carry with setcond
target-ppc: Use add2 for carry generation
target-ppc: Implement neg in terms of subf
target-ppc: Compute arithmetic shift carry without branches
target-ppc: Compute mullwo without branches