target-xtensa: refactor standard core configuration
Coalesce all standard configuration sections into singleDEFAULT_SECTIONS macro for all cores. This allows to add new features ina single place: overlay_tool.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: provide HW confg ID registers
target-xtensa: add RRRI4 opcode format fields
This encoding is used by cache instructions.
target-xtensa: add basic checks to dcache opcodes
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,DIWBI, DPFL are privileged), memory accessibility for instructions thatreference memory (all DH* and DPFL) and windowed register validity for all...
target-xtensa: add basic checks to icache opcodes
Check privilege level for privileged instructions (IHU, III, IIU and IPFLare privileged), memory accessibility for instructions that reference memory(IH* and IPFL) and windowed register validity for all instruction cache...
exec: Make ldl_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
exec: Make tb_invalidate_phys_addr input an AS
No functional change.
target-xtensa: add missing DEBUG section to dc233c config
This fixes missing debug feature opcodes of dc233c core variant.
Cc: qemu-stable@nongnu.orgSigned-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add in_asm logging
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
target: Include softmmu_exec.h where forgotten
Several targets forgot to include softmmu_exec.h, which wouldbreak them with a header cleanup to follow.
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging
xtensa queue 2013-07-29
target-xtensa: avoid double-stopping at breakpoints
env->exception_taken is set every time an exception is taken. It is usedto allow single-stepping to stop at the first exception handlerinstruction. This however must exclude debug exceptions, as otherwise...
target-xtensa: don't generate dead code to access invalid SRs
This fixes the following test failure caused by access to undefined SR:
qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel ./test_sr.tst QEMU 1.4.50 monitor - type 'help' for more information...
target-xtensa: check register window inline
This lowers time spent in helper_window_check as reported by perf topfrom ~8% to ~0.15% accelerating register-intensive tests by ~20%.
target-xtensa: add fallthrough markers
Explicitly mark cases where we are deliberately falling through to thefollowing code.
cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"
Commit c643bed99 moved qemu_init_vcpu() calls to common CPUState code.This causes x86 cpu-add to fail with "KVM: setting VAPIC address failed".
The reason for the failure is that CPUClass::kvm_fd is not yet...
target-xtensa: Move cpu_gdb_{read,write}_register()
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Andreas Färber <afaerber@suse.de>
gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions
This avoids polluting the global namespace with a non-prefixed macro andmakes it obvious in the call sites that we return.
Semi-automatic conversion using, e.g., sed i 's/GET_REGL(/return gdb_get_regl(mem_buf, /g' target*/gdbstub.c...
cpu: Introduce CPUClass::gdb_{read,write}_register()
Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs
CPUState::gdb_num_regs replaces num_g_regs.CPUClass::gdb_num_core_regs replaces NUM_CORE_REGS.
Allows building gdb_register_coprocessor() for xtensa, too.
As a side effect this should fix coprocessor register numbering for SMP....
target-xtensa: Introduce XtensaCPU subclasses
Register a CPU type per core registered. Save the XtensaConfig inXtensaCPUClass and copy it from there to CPUXtensaState, to avoidtouching every env->config access for now.
Prepares for storing per-class GDB register count....
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
exec: Change cpu_memory_rw_debug() argument to CPUState
Propagate X86CPU in kvmvapic for simplicity.
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc()
This moves setting the Program Counter from gdbstub into target code.Use vaddr type as upper-bound replacement for target_ulong.
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-xtensa: gen_intermediate_code_internal() should be inlined
Cc: qemu-stable@nongnu.orgReported-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Drop unnecessary dynamic casts in *_env_get_cpu()
A transition from CPUFooState to FooCPU can be considered safe,just like FooCPU::env access in the opposite direction.The only benefit of the FOO_CPU() casts would be protection againstbogus CPUFooState pointers, but then surrounding code would likely...
cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specificcode that needs to generate TCG instructions which reference CPUStatefields given the cpu_env register that TCG targets set up with apointer to the CPUArchState struct....
target-xtensa: Use mul*2 for mul*hi
Cc: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: Use add2/sub2 for mac
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-xtensa: Move TCG initialization to XtensaCPU initfn
Combine this with breakpoint handler registration, guarding both withtcg_enabled() to suppress also TCG init for qtest. Rename the handler toxtensa_breakpoint_handler() since it needs to become global....
target-xtensa: Introduce QOM realizefn for XtensaCPU
Introduce realizefn and set realized = true in cpu_xtensa_init().
target-xtensa: Mark as unmigratable
There was no CPU_SAVE_VERSION defined, so neither "cpu_common" VMStatenor cpu_{save,load}() were registered. Their implementation was no-op.Therefore there is no backwards compatibility to keep, so mark XtensaCPUas unmigratable at device level....
target-xtensa: fix search_pc for the last TB opcode
Zero out tcg_ctx.gen_opc_instr_start for instructions representing thelast guest opcode in the TB.
Cc: qemu-stable@nongnu.orgSigned-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: fix ITLB/DTLB page protection flags
With MMU option xtensa architecture has two TLBs: ITLB and DTLB. ITLB isonly used for code access, DTLB is only for data. However TLB entries inboth TLBs have attribute field controlling write and exec access. These...
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memorytype. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and thecorresponding TLB management instructions are not available. Instead,functionality similar to the Region Protection Option is availablethrough the cache attribute register. See ISA, A.2.14 for details....
target-xtensa: restrict available SRs by enabled options
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,xsr) are associated with their corresponding SR and raise illegal opcodeexception in case the register is not configured for the core....
target-xtensa: better control rsr/wsr/xsr access to SRs
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagalopcode exception on illegal access to these SRs.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: implement MISC SR
The Miscellaneous Special Registers Option provides zero to four scratchregisters within the processor readable and writable by RSR, WSR, andXSR. These registers are privileged. They may be useful for someapplication-specific exception and interrupt processing tasks in the...
target-xtensa: use movcond where possible
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAXopcodes.
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
target-xtensa: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Andreas Färber <afaerber@suse.de>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
target-xtensa: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Cc: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-xtensa: de-optimize EXTUI
Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shiftare optimized in tcg/tcg-op.h there is no need to do it intarget-xtensa/translate.c.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement coprocessor context option
In case Coprocessor Context option is enabled CPENABLE SR bits controlwhether access to coprocessors is allowed or would rise one ofCoprocessorXDisabled exceptions.
See ISA, 4.4.5 for more details.
FP is coprocessor 0....
target-xtensa: handle boolean option in overlays
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status userregisters (fcr, fsr).
See ISA, 4.3.10 for more details.
target-xtensa: implement LSCX and LSCI groups
These are load/store instructions for FP registers with immediate orregister index and optional base post-update.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes.See ISA, 4.3.10 for more details.
Note that ISA description for utrunc.s is currently incorrect and willbe fixed in future revisions.
target-xtensa: fix extui shift amount
extui opcode only uses lowermost op1 bit for sa4.
Reported-by: malc <av1474@comtv.ru>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Cc: qemu-stable <qemu-stable@nongnu.org>Signed-off-by: malc <av1474@comtv.ru>
target-xtensa: don't emit extra tcg_gen_goto_tb
Unconditional gen_check_loop_end at the end of disas_xtensa_insncan emit tcg_gen_goto_tb with slot id already used in the TB (e.g. whenTB ends at LEND with a branch).
target-xtensa: fix missing errno codes for mingw32
Put the following errno value mappings under #ifdef:
xtensa-semi.c: In function 'errno_h2g':xtensa-semi.c:113: error: 'ENOTBLK' undeclared (first use in this function)xtensa-semi.c:113: error: (Each undeclared identifier is reported only once...
target-xtensa: convert host errno values to guest
Guest errno values are taken from the newlib. Convert only those errnovalues that can be returned from used system calls.
target-xtensa: return ENOSYS for unimplemented simcalls
This prevents guest from proceeding with uninitialised garbage returnedfrom unimplemented simcalls.
Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemu
target-xtensa: make default CPU depend on target endianness
This makes usable default for -cpu option both for qemu-system-xtensaand qemu-system-xtensaeb fixing the following error:
$ qemu-system-xtensaeb -M sim Unable to find CPU definition
target-xtensa: fix big-endian BBS/BBC implementation
Quote from ISA, 2.1:
For most Xtensa instructions, bit numbering is irrelevant; only the BBCand BBS instructions assign bit numbers to values on which the processoroperates. The BBC/BBS instructions use big-endian bit ordering (0 is the...
target-xtensa: drop usage of prev_debug_excp_handler
Chains of exception handlers are currently unused feature. Dropping itto be consistent with target-i386 but it may simplify qom-ifying CPUin future like for target-i386.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
target-xtensa: switch to AREG0-free mode
Add env parameter to every helper function that needs it, update'configure' script.
target-xtensa: add attributes to helper functions
Mark exception generating functions 'noreturn' and pure constantfunctions as such.
target-xtensa: remove unnecessary include of dyngen-exec.h
Signed-off-by: Peter Portante <peter.portante@redhat.com>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: fix CCOUNT for conditional branches
Taken conditional branches fail to update CCOUNT register becauseaccumulated ccount_delta is reset during translation of non-takenbranch. To fix it only update CCOUNT once per conditional branchinstruction translation....
target-xtensa: flush TLB page for new MMU mapping
Both old and new mappings need flushing because their VPN may bedifferent in MMU case.
target-xtensa: update EXCVADDR in case of page table lookup
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, evenif the miss is handled entirely by processor hardware.
target-xtensa: extract TLB entry setting method
target-xtensa: update autorefill TLB entries conditionally
This is to avoid interference of internal QEMU helpers(cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visibleTLB state.
target-xtensa: control page table lookup explicitly
Hardware pagetable walking may not be nested. Stop guessing and passexplicit flag to the get_physical_addr_mmu function that controls pagetable lookup.
build: move other target-*/ objects to nested Makefile.objs
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-xtensa: Let cpu_xtensa_init() return XtensaCPU
Make the include paths for cpu-qom.h consistent to allow using XtensaCPUin cpu.h.
Turn cpu_init macro into a static inline function returningCPUXtensaState for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Translation of LOOP instructions used to call LEND SR write handler toupdate LEND and invalidate relevant TBs. Now that LEND SR write handlerends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple...