root / target-arm / cpu.c @ feature-archipelago
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/*
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* QEMU ARM CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h" |
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#include "qemu-common.h" |
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#include "hw/qdev-properties.h" |
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#include "qapi/qmp/qerror.h" |
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h" |
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#endif
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#include "hw/arm/arm.h" |
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#include "sysemu/sysemu.h" |
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#include "sysemu/kvm.h" |
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static void arm_cpu_set_pc(CPUState *cs, vaddr value) |
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{ |
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ARMCPU *cpu = ARM_CPU(cs); |
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cpu->env.regs[15] = value;
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} |
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) |
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{ |
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value; |
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ARMCPU *cpu = opaque; |
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if (ri->type & ARM_CP_SPECIAL) {
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return;
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} |
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if (ri->resetfn) {
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ri->resetfn(&cpu->env, ri); |
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return;
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} |
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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*/
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if (!ri->fieldoffset) {
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return;
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} |
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if (cpreg_field_is_64bit(ri)) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; |
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} else {
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; |
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} |
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} |
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s) |
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{ |
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ARMCPU *cpu = ARM_CPU(s); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); |
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CPUARMState *env = &cpu->env; |
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acc->parent_reset(s); |
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); |
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; |
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; |
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; |
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} |
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64 bit CPUs always start in 64 bit mode */
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env->aarch64 = 1;
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#if defined(CONFIG_USER_ONLY)
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env->pstate = PSTATE_MODE_EL0t; |
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/* Userspace expects access to CTL_EL0 and the cache ops */
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env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; |
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#else
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env->pstate = PSTATE_MODE_EL1h; |
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#endif
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} |
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR; |
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; |
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
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env->cp15.c15_cpar = 1;
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} |
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC; |
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env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; |
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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if (IS_M(env)) {
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uint32_t pc; |
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uint8_t *rom; |
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env->daif &= ~PSTATE_I; |
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rom = rom_ptr(0);
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if (rom) {
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom) & 0xFFFFFFFC; |
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pc = ldl_p(rom + 4);
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env->thumb = pc & 1;
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env->regs[15] = pc & ~1; |
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} |
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} |
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if (env->cp15.c1_sys & SCTLR_V) {
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env->regs[15] = 0xFFFF0000; |
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} |
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.fp_status); |
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set_float_detect_tininess(float_tininess_before_rounding, |
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&env->vfp.standard_fp_status); |
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env); |
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} |
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#ifndef CONFIG_USER_ONLY
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static void arm_cpu_set_irq(void *opaque, int irq, int level) |
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{ |
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ARMCPU *cpu = opaque; |
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CPUState *cs = CPU(cpu); |
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switch (irq) {
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case ARM_CPU_IRQ:
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
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} |
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break;
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case ARM_CPU_FIQ:
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_FIQ); |
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); |
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} |
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break;
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default:
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hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
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} |
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} |
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static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) |
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{ |
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#ifdef CONFIG_KVM
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ARMCPU *cpu = opaque; |
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CPUState *cs = CPU(cpu); |
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int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
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switch (irq) {
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case ARM_CPU_IRQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; |
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break;
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case ARM_CPU_FIQ:
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kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; |
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break;
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default:
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hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
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} |
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kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; |
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kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); |
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#endif
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} |
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#endif
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static inline void set_feature(CPUARMState *env, int feature) |
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{ |
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env->features |= 1ULL << feature;
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} |
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static void arm_cpu_initfn(Object *obj) |
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{ |
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CPUState *cs = CPU(obj); |
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ARMCPU *cpu = ARM_CPU(obj); |
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static bool inited; |
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cs->env_ptr = &cpu->env; |
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cpu_exec_init(&cpu->env); |
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, |
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g_free, g_free); |
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#ifndef CONFIG_USER_ONLY
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/* Our inbound IRQ and FIQ lines */
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if (kvm_enabled()) {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
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} else {
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
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} |
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cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
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arm_gt_ptimer_cb, cpu); |
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cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, |
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arm_gt_vtimer_cb, cpu); |
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qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, |
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ARRAY_SIZE(cpu->gt_timer_outputs)); |
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#endif
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/* DTB consumers generally don't in fact care what the 'compatible'
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* string is, so always provide some string and trust that a hypothetical
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* picky DTB consumer will also provide a helpful error message.
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*/
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cpu->dtb_compatible = "qemu,unknown";
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; |
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if (tcg_enabled() && !inited) {
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inited = true;
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arm_translate_init(); |
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} |
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} |
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static Property arm_cpu_reset_cbar_property =
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DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0); |
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static Property arm_cpu_reset_hivecs_property =
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DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); |
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static void arm_cpu_post_init(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, |
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&error_abort); |
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} |
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if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, |
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&error_abort); |
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} |
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} |
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static void arm_cpu_finalizefn(Object *obj) |
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{ |
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ARMCPU *cpu = ARM_CPU(obj); |
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g_hash_table_destroy(cpu->cp_regs); |
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} |
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static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
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{ |
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CPUState *cs = CPU(dev); |
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ARMCPU *cpu = ARM_CPU(dev); |
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); |
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CPUARMState *env = &cpu->env; |
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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set_feature(env, ARM_FEATURE_V7); |
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set_feature(env, ARM_FEATURE_ARM_DIV); |
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set_feature(env, ARM_FEATURE_LPAE); |
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set_feature(env, ARM_FEATURE_V8_AES); |
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} |
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA); |
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set_feature(env, ARM_FEATURE_THUMB2); |
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set_feature(env, ARM_FEATURE_MPIDR); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K); |
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} else {
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set_feature(env, ARM_FEATURE_V6); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6); |
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set_feature(env, ARM_FEATURE_MVFR); |
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} |
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5); |
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR); |
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} |
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} |
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T); |
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} |
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3); |
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} |
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP); |
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} |
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP); |
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set_feature(env, ARM_FEATURE_PXN); |
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} |
328 |
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if (cpu->reset_hivecs) {
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cpu->reset_sctlr |= (1 << 13); |
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} |
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register_cp_regs_for_features(cpu); |
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arm_cpu_register_gdb_regs_for_features(cpu); |
335 |
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init_cpreg_list(cpu); |
337 |
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cpu_reset(cs); |
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qemu_init_vcpu(cs); |
340 |
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acc->parent_realize(dev, errp); |
342 |
} |
343 |
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static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) |
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{ |
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ObjectClass *oc; |
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char *typename;
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if (!cpu_model) {
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return NULL; |
351 |
} |
352 |
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typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
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oc = object_class_by_name(typename); |
355 |
g_free(typename); |
356 |
if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
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object_class_is_abstract(oc)) { |
358 |
return NULL; |
359 |
} |
360 |
return oc;
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} |
362 |
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363 |
/* CPU models. These are not needed for the AArch64 linux-user build. */
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#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
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365 |
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366 |
static void arm926_initfn(Object *obj) |
367 |
{ |
368 |
ARMCPU *cpu = ARM_CPU(obj); |
369 |
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cpu->dtb_compatible = "arm,arm926";
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set_feature(&cpu->env, ARM_FEATURE_V5); |
372 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
373 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
374 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
375 |
cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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379 |
} |
380 |
|
381 |
static void arm946_initfn(Object *obj) |
382 |
{ |
383 |
ARMCPU *cpu = ARM_CPU(obj); |
384 |
|
385 |
cpu->dtb_compatible = "arm,arm946";
|
386 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
387 |
set_feature(&cpu->env, ARM_FEATURE_MPU); |
388 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
389 |
cpu->midr = 0x41059461;
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390 |
cpu->ctr = 0x0f004006;
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391 |
cpu->reset_sctlr = 0x00000078;
|
392 |
} |
393 |
|
394 |
static void arm1026_initfn(Object *obj) |
395 |
{ |
396 |
ARMCPU *cpu = ARM_CPU(obj); |
397 |
|
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cpu->dtb_compatible = "arm,arm1026";
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set_feature(&cpu->env, ARM_FEATURE_V5); |
400 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
401 |
set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
402 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
403 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); |
404 |
cpu->midr = 0x4106a262;
|
405 |
cpu->reset_fpsid = 0x410110a0;
|
406 |
cpu->ctr = 0x1dd20d2;
|
407 |
cpu->reset_sctlr = 0x00090078;
|
408 |
cpu->reset_auxcr = 1;
|
409 |
{ |
410 |
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
|
411 |
ARMCPRegInfo ifar = { |
412 |
.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, |
413 |
.access = PL1_RW, |
414 |
.fieldoffset = offsetof(CPUARMState, cp15.c6_insn), |
415 |
.resetvalue = 0
|
416 |
}; |
417 |
define_one_arm_cp_reg(cpu, &ifar); |
418 |
} |
419 |
} |
420 |
|
421 |
static void arm1136_r2_initfn(Object *obj) |
422 |
{ |
423 |
ARMCPU *cpu = ARM_CPU(obj); |
424 |
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
|
425 |
* older core than plain "arm1136". In particular this does not
|
426 |
* have the v6K features.
|
427 |
* These ID register values are correct for 1136 but may be wrong
|
428 |
* for 1136_r2 (in particular r0p2 does not actually implement most
|
429 |
* of the ID registers).
|
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*/
|
431 |
|
432 |
cpu->dtb_compatible = "arm,arm1136";
|
433 |
set_feature(&cpu->env, ARM_FEATURE_V6); |
434 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
435 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
436 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
437 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
438 |
cpu->midr = 0x4107b362;
|
439 |
cpu->reset_fpsid = 0x410120b4;
|
440 |
cpu->mvfr0 = 0x11111111;
|
441 |
cpu->mvfr1 = 0x00000000;
|
442 |
cpu->ctr = 0x1dd20d2;
|
443 |
cpu->reset_sctlr = 0x00050078;
|
444 |
cpu->id_pfr0 = 0x111;
|
445 |
cpu->id_pfr1 = 0x1;
|
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cpu->id_dfr0 = 0x2;
|
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cpu->id_afr0 = 0x3;
|
448 |
cpu->id_mmfr0 = 0x01130003;
|
449 |
cpu->id_mmfr1 = 0x10030302;
|
450 |
cpu->id_mmfr2 = 0x01222110;
|
451 |
cpu->id_isar0 = 0x00140011;
|
452 |
cpu->id_isar1 = 0x12002111;
|
453 |
cpu->id_isar2 = 0x11231111;
|
454 |
cpu->id_isar3 = 0x01102131;
|
455 |
cpu->id_isar4 = 0x141;
|
456 |
cpu->reset_auxcr = 7;
|
457 |
} |
458 |
|
459 |
static void arm1136_initfn(Object *obj) |
460 |
{ |
461 |
ARMCPU *cpu = ARM_CPU(obj); |
462 |
|
463 |
cpu->dtb_compatible = "arm,arm1136";
|
464 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
465 |
set_feature(&cpu->env, ARM_FEATURE_V6); |
466 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
467 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
468 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
469 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
470 |
cpu->midr = 0x4117b363;
|
471 |
cpu->reset_fpsid = 0x410120b4;
|
472 |
cpu->mvfr0 = 0x11111111;
|
473 |
cpu->mvfr1 = 0x00000000;
|
474 |
cpu->ctr = 0x1dd20d2;
|
475 |
cpu->reset_sctlr = 0x00050078;
|
476 |
cpu->id_pfr0 = 0x111;
|
477 |
cpu->id_pfr1 = 0x1;
|
478 |
cpu->id_dfr0 = 0x2;
|
479 |
cpu->id_afr0 = 0x3;
|
480 |
cpu->id_mmfr0 = 0x01130003;
|
481 |
cpu->id_mmfr1 = 0x10030302;
|
482 |
cpu->id_mmfr2 = 0x01222110;
|
483 |
cpu->id_isar0 = 0x00140011;
|
484 |
cpu->id_isar1 = 0x12002111;
|
485 |
cpu->id_isar2 = 0x11231111;
|
486 |
cpu->id_isar3 = 0x01102131;
|
487 |
cpu->id_isar4 = 0x141;
|
488 |
cpu->reset_auxcr = 7;
|
489 |
} |
490 |
|
491 |
static void arm1176_initfn(Object *obj) |
492 |
{ |
493 |
ARMCPU *cpu = ARM_CPU(obj); |
494 |
|
495 |
cpu->dtb_compatible = "arm,arm1176";
|
496 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
497 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
498 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
499 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
500 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); |
501 |
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); |
502 |
cpu->midr = 0x410fb767;
|
503 |
cpu->reset_fpsid = 0x410120b5;
|
504 |
cpu->mvfr0 = 0x11111111;
|
505 |
cpu->mvfr1 = 0x00000000;
|
506 |
cpu->ctr = 0x1dd20d2;
|
507 |
cpu->reset_sctlr = 0x00050078;
|
508 |
cpu->id_pfr0 = 0x111;
|
509 |
cpu->id_pfr1 = 0x11;
|
510 |
cpu->id_dfr0 = 0x33;
|
511 |
cpu->id_afr0 = 0;
|
512 |
cpu->id_mmfr0 = 0x01130003;
|
513 |
cpu->id_mmfr1 = 0x10030302;
|
514 |
cpu->id_mmfr2 = 0x01222100;
|
515 |
cpu->id_isar0 = 0x0140011;
|
516 |
cpu->id_isar1 = 0x12002111;
|
517 |
cpu->id_isar2 = 0x11231121;
|
518 |
cpu->id_isar3 = 0x01102131;
|
519 |
cpu->id_isar4 = 0x01141;
|
520 |
cpu->reset_auxcr = 7;
|
521 |
} |
522 |
|
523 |
static void arm11mpcore_initfn(Object *obj) |
524 |
{ |
525 |
ARMCPU *cpu = ARM_CPU(obj); |
526 |
|
527 |
cpu->dtb_compatible = "arm,arm11mpcore";
|
528 |
set_feature(&cpu->env, ARM_FEATURE_V6K); |
529 |
set_feature(&cpu->env, ARM_FEATURE_VFP); |
530 |
set_feature(&cpu->env, ARM_FEATURE_VAPA); |
531 |
set_feature(&cpu->env, ARM_FEATURE_MPIDR); |
532 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
533 |
cpu->midr = 0x410fb022;
|
534 |
cpu->reset_fpsid = 0x410120b4;
|
535 |
cpu->mvfr0 = 0x11111111;
|
536 |
cpu->mvfr1 = 0x00000000;
|
537 |
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ |
538 |
cpu->id_pfr0 = 0x111;
|
539 |
cpu->id_pfr1 = 0x1;
|
540 |
cpu->id_dfr0 = 0;
|
541 |
cpu->id_afr0 = 0x2;
|
542 |
cpu->id_mmfr0 = 0x01100103;
|
543 |
cpu->id_mmfr1 = 0x10020302;
|
544 |
cpu->id_mmfr2 = 0x01222000;
|
545 |
cpu->id_isar0 = 0x00100011;
|
546 |
cpu->id_isar1 = 0x12002111;
|
547 |
cpu->id_isar2 = 0x11221011;
|
548 |
cpu->id_isar3 = 0x01102131;
|
549 |
cpu->id_isar4 = 0x141;
|
550 |
cpu->reset_auxcr = 1;
|
551 |
} |
552 |
|
553 |
static void cortex_m3_initfn(Object *obj) |
554 |
{ |
555 |
ARMCPU *cpu = ARM_CPU(obj); |
556 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
557 |
set_feature(&cpu->env, ARM_FEATURE_M); |
558 |
cpu->midr = 0x410fc231;
|
559 |
} |
560 |
|
561 |
static void arm_v7m_class_init(ObjectClass *oc, void *data) |
562 |
{ |
563 |
#ifndef CONFIG_USER_ONLY
|
564 |
CPUClass *cc = CPU_CLASS(oc); |
565 |
|
566 |
cc->do_interrupt = arm_v7m_cpu_do_interrupt; |
567 |
#endif
|
568 |
} |
569 |
|
570 |
static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |
571 |
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, |
572 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
573 |
{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
574 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
575 |
REGINFO_SENTINEL |
576 |
}; |
577 |
|
578 |
static void cortex_a8_initfn(Object *obj) |
579 |
{ |
580 |
ARMCPU *cpu = ARM_CPU(obj); |
581 |
|
582 |
cpu->dtb_compatible = "arm,cortex-a8";
|
583 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
584 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
585 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
586 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
587 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
588 |
cpu->midr = 0x410fc080;
|
589 |
cpu->reset_fpsid = 0x410330c0;
|
590 |
cpu->mvfr0 = 0x11110222;
|
591 |
cpu->mvfr1 = 0x00011100;
|
592 |
cpu->ctr = 0x82048004;
|
593 |
cpu->reset_sctlr = 0x00c50078;
|
594 |
cpu->id_pfr0 = 0x1031;
|
595 |
cpu->id_pfr1 = 0x11;
|
596 |
cpu->id_dfr0 = 0x400;
|
597 |
cpu->id_afr0 = 0;
|
598 |
cpu->id_mmfr0 = 0x31100003;
|
599 |
cpu->id_mmfr1 = 0x20000000;
|
600 |
cpu->id_mmfr2 = 0x01202000;
|
601 |
cpu->id_mmfr3 = 0x11;
|
602 |
cpu->id_isar0 = 0x00101111;
|
603 |
cpu->id_isar1 = 0x12112111;
|
604 |
cpu->id_isar2 = 0x21232031;
|
605 |
cpu->id_isar3 = 0x11112131;
|
606 |
cpu->id_isar4 = 0x00111142;
|
607 |
cpu->clidr = (1 << 27) | (2 << 24) | 3; |
608 |
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ |
609 |
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ |
610 |
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ |
611 |
cpu->reset_auxcr = 2;
|
612 |
define_arm_cp_regs(cpu, cortexa8_cp_reginfo); |
613 |
} |
614 |
|
615 |
static const ARMCPRegInfo cortexa9_cp_reginfo[] = { |
616 |
/* power_control should be set to maximum latency. Again,
|
617 |
* default to 0 and set by private hook
|
618 |
*/
|
619 |
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, |
620 |
.access = PL1_RW, .resetvalue = 0,
|
621 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, |
622 |
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, |
623 |
.access = PL1_RW, .resetvalue = 0,
|
624 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, |
625 |
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, |
626 |
.access = PL1_RW, .resetvalue = 0,
|
627 |
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, |
628 |
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, |
629 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
630 |
/* TLB lockdown control */
|
631 |
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, |
632 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
633 |
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, |
634 |
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
|
635 |
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, |
636 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
637 |
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, |
638 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
639 |
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, |
640 |
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
|
641 |
REGINFO_SENTINEL |
642 |
}; |
643 |
|
644 |
static void cortex_a9_initfn(Object *obj) |
645 |
{ |
646 |
ARMCPU *cpu = ARM_CPU(obj); |
647 |
|
648 |
cpu->dtb_compatible = "arm,cortex-a9";
|
649 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
650 |
set_feature(&cpu->env, ARM_FEATURE_VFP3); |
651 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
652 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
653 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
654 |
/* Note that A9 supports the MP extensions even for
|
655 |
* A9UP and single-core A9MP (which are both different
|
656 |
* and valid configurations; we don't model A9UP).
|
657 |
*/
|
658 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
659 |
set_feature(&cpu->env, ARM_FEATURE_CBAR); |
660 |
cpu->midr = 0x410fc090;
|
661 |
cpu->reset_fpsid = 0x41033090;
|
662 |
cpu->mvfr0 = 0x11110222;
|
663 |
cpu->mvfr1 = 0x01111111;
|
664 |
cpu->ctr = 0x80038003;
|
665 |
cpu->reset_sctlr = 0x00c50078;
|
666 |
cpu->id_pfr0 = 0x1031;
|
667 |
cpu->id_pfr1 = 0x11;
|
668 |
cpu->id_dfr0 = 0x000;
|
669 |
cpu->id_afr0 = 0;
|
670 |
cpu->id_mmfr0 = 0x00100103;
|
671 |
cpu->id_mmfr1 = 0x20000000;
|
672 |
cpu->id_mmfr2 = 0x01230000;
|
673 |
cpu->id_mmfr3 = 0x00002111;
|
674 |
cpu->id_isar0 = 0x00101111;
|
675 |
cpu->id_isar1 = 0x13112111;
|
676 |
cpu->id_isar2 = 0x21232041;
|
677 |
cpu->id_isar3 = 0x11112131;
|
678 |
cpu->id_isar4 = 0x00111142;
|
679 |
cpu->clidr = (1 << 27) | (1 << 24) | 3; |
680 |
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ |
681 |
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ |
682 |
define_arm_cp_regs(cpu, cortexa9_cp_reginfo); |
683 |
} |
684 |
|
685 |
#ifndef CONFIG_USER_ONLY
|
686 |
static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
687 |
{ |
688 |
/* Linux wants the number of processors from here.
|
689 |
* Might as well set the interrupt-controller bit too.
|
690 |
*/
|
691 |
return ((smp_cpus - 1) << 24) | (1 << 23); |
692 |
} |
693 |
#endif
|
694 |
|
695 |
static const ARMCPRegInfo cortexa15_cp_reginfo[] = { |
696 |
#ifndef CONFIG_USER_ONLY
|
697 |
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, |
698 |
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
|
699 |
.writefn = arm_cp_write_ignore, }, |
700 |
#endif
|
701 |
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, |
702 |
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
|
703 |
REGINFO_SENTINEL |
704 |
}; |
705 |
|
706 |
static void cortex_a15_initfn(Object *obj) |
707 |
{ |
708 |
ARMCPU *cpu = ARM_CPU(obj); |
709 |
|
710 |
cpu->dtb_compatible = "arm,cortex-a15";
|
711 |
set_feature(&cpu->env, ARM_FEATURE_V7); |
712 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
713 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
714 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
715 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
716 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
717 |
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
718 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
719 |
set_feature(&cpu->env, ARM_FEATURE_CBAR); |
720 |
set_feature(&cpu->env, ARM_FEATURE_LPAE); |
721 |
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; |
722 |
cpu->midr = 0x412fc0f1;
|
723 |
cpu->reset_fpsid = 0x410430f0;
|
724 |
cpu->mvfr0 = 0x10110222;
|
725 |
cpu->mvfr1 = 0x11111111;
|
726 |
cpu->ctr = 0x8444c004;
|
727 |
cpu->reset_sctlr = 0x00c50078;
|
728 |
cpu->id_pfr0 = 0x00001131;
|
729 |
cpu->id_pfr1 = 0x00011011;
|
730 |
cpu->id_dfr0 = 0x02010555;
|
731 |
cpu->id_afr0 = 0x00000000;
|
732 |
cpu->id_mmfr0 = 0x10201105;
|
733 |
cpu->id_mmfr1 = 0x20000000;
|
734 |
cpu->id_mmfr2 = 0x01240000;
|
735 |
cpu->id_mmfr3 = 0x02102211;
|
736 |
cpu->id_isar0 = 0x02101110;
|
737 |
cpu->id_isar1 = 0x13112111;
|
738 |
cpu->id_isar2 = 0x21232041;
|
739 |
cpu->id_isar3 = 0x11112131;
|
740 |
cpu->id_isar4 = 0x10011142;
|
741 |
cpu->clidr = 0x0a200023;
|
742 |
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ |
743 |
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ |
744 |
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ |
745 |
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); |
746 |
} |
747 |
|
748 |
static void ti925t_initfn(Object *obj) |
749 |
{ |
750 |
ARMCPU *cpu = ARM_CPU(obj); |
751 |
set_feature(&cpu->env, ARM_FEATURE_V4T); |
752 |
set_feature(&cpu->env, ARM_FEATURE_OMAPCP); |
753 |
cpu->midr = ARM_CPUID_TI925T; |
754 |
cpu->ctr = 0x5109149;
|
755 |
cpu->reset_sctlr = 0x00000070;
|
756 |
} |
757 |
|
758 |
static void sa1100_initfn(Object *obj) |
759 |
{ |
760 |
ARMCPU *cpu = ARM_CPU(obj); |
761 |
|
762 |
cpu->dtb_compatible = "intel,sa1100";
|
763 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
764 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
765 |
cpu->midr = 0x4401A11B;
|
766 |
cpu->reset_sctlr = 0x00000070;
|
767 |
} |
768 |
|
769 |
static void sa1110_initfn(Object *obj) |
770 |
{ |
771 |
ARMCPU *cpu = ARM_CPU(obj); |
772 |
set_feature(&cpu->env, ARM_FEATURE_STRONGARM); |
773 |
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); |
774 |
cpu->midr = 0x6901B119;
|
775 |
cpu->reset_sctlr = 0x00000070;
|
776 |
} |
777 |
|
778 |
static void pxa250_initfn(Object *obj) |
779 |
{ |
780 |
ARMCPU *cpu = ARM_CPU(obj); |
781 |
|
782 |
cpu->dtb_compatible = "marvell,xscale";
|
783 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
784 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
785 |
cpu->midr = 0x69052100;
|
786 |
cpu->ctr = 0xd172172;
|
787 |
cpu->reset_sctlr = 0x00000078;
|
788 |
} |
789 |
|
790 |
static void pxa255_initfn(Object *obj) |
791 |
{ |
792 |
ARMCPU *cpu = ARM_CPU(obj); |
793 |
|
794 |
cpu->dtb_compatible = "marvell,xscale";
|
795 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
796 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
797 |
cpu->midr = 0x69052d00;
|
798 |
cpu->ctr = 0xd172172;
|
799 |
cpu->reset_sctlr = 0x00000078;
|
800 |
} |
801 |
|
802 |
static void pxa260_initfn(Object *obj) |
803 |
{ |
804 |
ARMCPU *cpu = ARM_CPU(obj); |
805 |
|
806 |
cpu->dtb_compatible = "marvell,xscale";
|
807 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
808 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
809 |
cpu->midr = 0x69052903;
|
810 |
cpu->ctr = 0xd172172;
|
811 |
cpu->reset_sctlr = 0x00000078;
|
812 |
} |
813 |
|
814 |
static void pxa261_initfn(Object *obj) |
815 |
{ |
816 |
ARMCPU *cpu = ARM_CPU(obj); |
817 |
|
818 |
cpu->dtb_compatible = "marvell,xscale";
|
819 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
820 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
821 |
cpu->midr = 0x69052d05;
|
822 |
cpu->ctr = 0xd172172;
|
823 |
cpu->reset_sctlr = 0x00000078;
|
824 |
} |
825 |
|
826 |
static void pxa262_initfn(Object *obj) |
827 |
{ |
828 |
ARMCPU *cpu = ARM_CPU(obj); |
829 |
|
830 |
cpu->dtb_compatible = "marvell,xscale";
|
831 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
832 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
833 |
cpu->midr = 0x69052d06;
|
834 |
cpu->ctr = 0xd172172;
|
835 |
cpu->reset_sctlr = 0x00000078;
|
836 |
} |
837 |
|
838 |
static void pxa270a0_initfn(Object *obj) |
839 |
{ |
840 |
ARMCPU *cpu = ARM_CPU(obj); |
841 |
|
842 |
cpu->dtb_compatible = "marvell,xscale";
|
843 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
844 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
845 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
846 |
cpu->midr = 0x69054110;
|
847 |
cpu->ctr = 0xd172172;
|
848 |
cpu->reset_sctlr = 0x00000078;
|
849 |
} |
850 |
|
851 |
static void pxa270a1_initfn(Object *obj) |
852 |
{ |
853 |
ARMCPU *cpu = ARM_CPU(obj); |
854 |
|
855 |
cpu->dtb_compatible = "marvell,xscale";
|
856 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
857 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
858 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
859 |
cpu->midr = 0x69054111;
|
860 |
cpu->ctr = 0xd172172;
|
861 |
cpu->reset_sctlr = 0x00000078;
|
862 |
} |
863 |
|
864 |
static void pxa270b0_initfn(Object *obj) |
865 |
{ |
866 |
ARMCPU *cpu = ARM_CPU(obj); |
867 |
|
868 |
cpu->dtb_compatible = "marvell,xscale";
|
869 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
870 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
871 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
872 |
cpu->midr = 0x69054112;
|
873 |
cpu->ctr = 0xd172172;
|
874 |
cpu->reset_sctlr = 0x00000078;
|
875 |
} |
876 |
|
877 |
static void pxa270b1_initfn(Object *obj) |
878 |
{ |
879 |
ARMCPU *cpu = ARM_CPU(obj); |
880 |
|
881 |
cpu->dtb_compatible = "marvell,xscale";
|
882 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
883 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
884 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
885 |
cpu->midr = 0x69054113;
|
886 |
cpu->ctr = 0xd172172;
|
887 |
cpu->reset_sctlr = 0x00000078;
|
888 |
} |
889 |
|
890 |
static void pxa270c0_initfn(Object *obj) |
891 |
{ |
892 |
ARMCPU *cpu = ARM_CPU(obj); |
893 |
|
894 |
cpu->dtb_compatible = "marvell,xscale";
|
895 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
896 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
897 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
898 |
cpu->midr = 0x69054114;
|
899 |
cpu->ctr = 0xd172172;
|
900 |
cpu->reset_sctlr = 0x00000078;
|
901 |
} |
902 |
|
903 |
static void pxa270c5_initfn(Object *obj) |
904 |
{ |
905 |
ARMCPU *cpu = ARM_CPU(obj); |
906 |
|
907 |
cpu->dtb_compatible = "marvell,xscale";
|
908 |
set_feature(&cpu->env, ARM_FEATURE_V5); |
909 |
set_feature(&cpu->env, ARM_FEATURE_XSCALE); |
910 |
set_feature(&cpu->env, ARM_FEATURE_IWMMXT); |
911 |
cpu->midr = 0x69054117;
|
912 |
cpu->ctr = 0xd172172;
|
913 |
cpu->reset_sctlr = 0x00000078;
|
914 |
} |
915 |
|
916 |
#ifdef CONFIG_USER_ONLY
|
917 |
static void arm_any_initfn(Object *obj) |
918 |
{ |
919 |
ARMCPU *cpu = ARM_CPU(obj); |
920 |
set_feature(&cpu->env, ARM_FEATURE_V8); |
921 |
set_feature(&cpu->env, ARM_FEATURE_VFP4); |
922 |
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); |
923 |
set_feature(&cpu->env, ARM_FEATURE_NEON); |
924 |
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); |
925 |
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); |
926 |
set_feature(&cpu->env, ARM_FEATURE_V7MP); |
927 |
set_feature(&cpu->env, ARM_FEATURE_CRC); |
928 |
#ifdef TARGET_AARCH64
|
929 |
set_feature(&cpu->env, ARM_FEATURE_AARCH64); |
930 |
#endif
|
931 |
cpu->midr = 0xffffffff;
|
932 |
} |
933 |
#endif
|
934 |
|
935 |
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ |
936 |
|
937 |
typedef struct ARMCPUInfo { |
938 |
const char *name; |
939 |
void (*initfn)(Object *obj);
|
940 |
void (*class_init)(ObjectClass *oc, void *data); |
941 |
} ARMCPUInfo; |
942 |
|
943 |
static const ARMCPUInfo arm_cpus[] = { |
944 |
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
|
945 |
{ .name = "arm926", .initfn = arm926_initfn },
|
946 |
{ .name = "arm946", .initfn = arm946_initfn },
|
947 |
{ .name = "arm1026", .initfn = arm1026_initfn },
|
948 |
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
|
949 |
* older core than plain "arm1136". In particular this does not
|
950 |
* have the v6K features.
|
951 |
*/
|
952 |
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
|
953 |
{ .name = "arm1136", .initfn = arm1136_initfn },
|
954 |
{ .name = "arm1176", .initfn = arm1176_initfn },
|
955 |
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
|
956 |
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
957 |
.class_init = arm_v7m_class_init }, |
958 |
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
959 |
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
960 |
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
961 |
{ .name = "ti925t", .initfn = ti925t_initfn },
|
962 |
{ .name = "sa1100", .initfn = sa1100_initfn },
|
963 |
{ .name = "sa1110", .initfn = sa1110_initfn },
|
964 |
{ .name = "pxa250", .initfn = pxa250_initfn },
|
965 |
{ .name = "pxa255", .initfn = pxa255_initfn },
|
966 |
{ .name = "pxa260", .initfn = pxa260_initfn },
|
967 |
{ .name = "pxa261", .initfn = pxa261_initfn },
|
968 |
{ .name = "pxa262", .initfn = pxa262_initfn },
|
969 |
/* "pxa270" is an alias for "pxa270-a0" */
|
970 |
{ .name = "pxa270", .initfn = pxa270a0_initfn },
|
971 |
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
|
972 |
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
|
973 |
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
|
974 |
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
|
975 |
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
|
976 |
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
|
977 |
#ifdef CONFIG_USER_ONLY
|
978 |
{ .name = "any", .initfn = arm_any_initfn },
|
979 |
#endif
|
980 |
#endif
|
981 |
{ .name = NULL }
|
982 |
}; |
983 |
|
984 |
static Property arm_cpu_properties[] = {
|
985 |
DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), |
986 |
DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), |
987 |
DEFINE_PROP_END_OF_LIST() |
988 |
}; |
989 |
|
990 |
static void arm_cpu_class_init(ObjectClass *oc, void *data) |
991 |
{ |
992 |
ARMCPUClass *acc = ARM_CPU_CLASS(oc); |
993 |
CPUClass *cc = CPU_CLASS(acc); |
994 |
DeviceClass *dc = DEVICE_CLASS(oc); |
995 |
|
996 |
acc->parent_realize = dc->realize; |
997 |
dc->realize = arm_cpu_realizefn; |
998 |
dc->props = arm_cpu_properties; |
999 |
|
1000 |
acc->parent_reset = cc->reset; |
1001 |
cc->reset = arm_cpu_reset; |
1002 |
|
1003 |
cc->class_by_name = arm_cpu_class_by_name; |
1004 |
cc->do_interrupt = arm_cpu_do_interrupt; |
1005 |
cc->dump_state = arm_cpu_dump_state; |
1006 |
cc->set_pc = arm_cpu_set_pc; |
1007 |
cc->gdb_read_register = arm_cpu_gdb_read_register; |
1008 |
cc->gdb_write_register = arm_cpu_gdb_write_register; |
1009 |
#ifndef CONFIG_USER_ONLY
|
1010 |
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; |
1011 |
cc->vmsd = &vmstate_arm_cpu; |
1012 |
#endif
|
1013 |
cc->gdb_num_core_regs = 26;
|
1014 |
cc->gdb_core_xml_file = "arm-core.xml";
|
1015 |
} |
1016 |
|
1017 |
static void cpu_register(const ARMCPUInfo *info) |
1018 |
{ |
1019 |
TypeInfo type_info = { |
1020 |
.parent = TYPE_ARM_CPU, |
1021 |
.instance_size = sizeof(ARMCPU),
|
1022 |
.instance_init = info->initfn, |
1023 |
.class_size = sizeof(ARMCPUClass),
|
1024 |
.class_init = info->class_init, |
1025 |
}; |
1026 |
|
1027 |
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
1028 |
type_register(&type_info); |
1029 |
g_free((void *)type_info.name);
|
1030 |
} |
1031 |
|
1032 |
static const TypeInfo arm_cpu_type_info = { |
1033 |
.name = TYPE_ARM_CPU, |
1034 |
.parent = TYPE_CPU, |
1035 |
.instance_size = sizeof(ARMCPU),
|
1036 |
.instance_init = arm_cpu_initfn, |
1037 |
.instance_post_init = arm_cpu_post_init, |
1038 |
.instance_finalize = arm_cpu_finalizefn, |
1039 |
.abstract = true,
|
1040 |
.class_size = sizeof(ARMCPUClass),
|
1041 |
.class_init = arm_cpu_class_init, |
1042 |
}; |
1043 |
|
1044 |
static void arm_cpu_register_types(void) |
1045 |
{ |
1046 |
const ARMCPUInfo *info = arm_cpus;
|
1047 |
|
1048 |
type_register_static(&arm_cpu_type_info); |
1049 |
|
1050 |
while (info->name) {
|
1051 |
cpu_register(info); |
1052 |
info++; |
1053 |
} |
1054 |
} |
1055 |
|
1056 |
type_init(arm_cpu_register_types) |