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target-arm: convert void helpers
Add an explicit CPUState parameter instead of relying on AREG0.
For easier review, convert only op helpers which don't return any value.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: convert remaining helpers
Convert remaining helpers to AREG0 free mode: add an explicitCPUState parameter instead of relying on AREG0.
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.
target-arm: Fix typos in comments
Fix a variety of typos in comments in target-arm files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
arm: translate: comment typo - s/middel/middle/
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Fix TCG temp handling in 64 bit cp writes
Fix errors in the TCG temp handling in the 64 bit coprocessorwrite path: we were reusing a 32 bit temp after it had beenfreed by store_reg(), and failing to free a 64 bit temp.
This bug has no visible effect at this point because there...
target-arm: Fix CP15 based WFI
The coprocessor register rework broke cp15 based WFI instructions.We incorrectly fall through the normal register write case, whichincorrectly adds a forced block termination. We've already donea special version of this (DISAS_WFI), so return immediately....
target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,so it can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.This includes only providing them on the CPUs which implementedthem, rather than the previous blunderbuss approach of makingall MCRR instructions on all CPUs act as NOPs....
target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers tothe new scheme.
target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework
target-arm: Convert WFI/barriers special cases to cp_reginfo
Convert the various WFI and barrier instruction special cases to usecp_reginfo infrastructure.
target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR touse arm_cp_reginfo.
target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to thecp_reginfo scheme.
target-arm: Remove old cpu_arm_set_cp_io infrastructure
All the users of cpu_arm_set_cp_io have been converted, so wecan remove it and the infrastructure it used.
target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
target-arm: Make SETEND respect bswap_code (BE8) setting
Make the SETEND instruction respect the setting of bswap_code,so that in BE8 mode we UNDEF for attempts to switch intolittle-endian mode and nop for attempts to stay in big-endianmode. (This is the inverse of the existing handling of SETEND...
Userspace ARM BE8 support
Add support for ARM BE8 userspace binaries.i.e. big-endian data and little-endian code.In principle LE8 mode is also possible, but AFAIK has never actuallybeen implemented/used.
System emulation doesn't have any useable big-endian board models,...
ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registerswith a test for a new feature flag ARM_FEATURE_MVFR, and sets this featurefor all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu...
target-arm: Decode SETEND correctly in Thumb
Decode the SETEND instruction correctly in Thumb mode,rather than accidentally treating it like CPS. We don'tsupport BE8 mode, but this change brings the Thumb modein to line with behaviour in ARM mode: 'SETEND BE' is...
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>...
target-arm: Fix errors in decode of M profile CPS
Fix errors in the decode of M profile CPS: * the decode of the I (affects PRIMASK) and F (affects FAULTMASK) bits was reversed * the FAULTMASK system register number is 19, not 17
This fixes an issue reported as LP:913925....
target-arm/translate.c: Fix slightly misleading comment in Thumb decoder
Clarify some slightly misleading comments in the Thumb decoder'shandling of the memory hint space -- in particular one code pathmarked as 'UNPREDICTABLE or unallocated hint' also includes some...
target-arm: Implement VFPv4 fused multiply-accumulate insns
Implement the fused multiply-accumulate instructions (VFMA, VFMS,VFNMA, VFNMS) which are new in VFPv4.
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, tomake room for a new feature switch enabling DIV in the ARMencoding. (Cores may implement either (a) no divide insns(b) divide insns in Thumb encodings only (c) divide insns...
target-arm: Add ARM UDIV/SDIV support
Add support for UDIV and SDIV in ARM mode. This is a new optionalfeature for A profile cores (Thumb mode has had UDIV and SDIV forM profile cores for some time).
target-arm: v6 media multiply space: UNDEF on unassigned encodings
Clean up the decoding of the v6 media multiply space so that we UNDEFon unassigned encodings rather than randomly interpreting them assome instruction in this space.
target-arm: Support v6 barriers in linux-user mode
ARMv6 implemented various operations as special cases of cp15 accesseswhich are true instructions in v7; this includes barriers (DMB, DSB, ISB).Catch this special case at translate time, so that it works in linux-user...
target-arm: Handle UNDEF and UNPREDICTABLE cases for VLDM, VSTM
Handle the UNDEF and UNPREDICTABLE cases for VLDM and VSTM. Inparticular, we now generate an undef exception for overlarge imm8values rather than generating 1000+ TCG ops and hitting an assertion....
target-arm: UNDEF on a VCVTT/VCVTB UNPREDICTABLE to avoid TCG assert
VCVTT/VCVTB with bit 8 set is UNPREDICTABLE; we choose to UNDEF.This avoids a TCG assert later when the VCVTT/VCVTB code tries touse a source register that wasn't ever set up.
We pull the check for the presence of the half-precision extension...
target-arm: Don't print debug messages for various UNDEF cases
Remove some stray printfs for cases which don't generally happen(some VFP UNDEF cases, reads and writes to unknown cp14 registers);we should simply generate an UNDEF when the instruction is executed....
Merge branch 'for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Minimal implementation of performance counters
Newer Linux kernels assume the existence of the performance countercp15 registers. Provide a minimal implementation of these registers.We support no events. This should be compliant with the ARM ARM,...
Revert "target-arm: Use global env in neon_helper.c helpers"
This effectively reverts commit 2a3f75b42ac255be09ec2939b96c549ec830efd3so that we return to passing CPUState to helpers as an explicit parameter.(There were a number of conflicts in target-arm/translate.c which had...
target-arm: Pass fp status pointer explicitly to neon fp helpers
Make the Neon helpers for various floating point operations take anexplicit pointer to the float_status they use, so they don't rely onthe global environment pointer any more. This also allows us to drop...
target-arm: Make VFP binop helpers take pointer to fpstatus, not CPUState
Make the VFP binop helper functions take a pointer to the fp status, notthe entire CPUState. This will allow us to use them for Neon operations too.
target-arm: Add helper function to generate code to get fpstatus pointer
Add and use a helper function which returns a TCGv which is a pointerto the fp_status for either Neon or VFP operations.
Revert "target-arm: Use global env in iwmmxt_helper.c helpers"
This reverts commit 947a2fa21b61703802a660a938cabd7b3600ee79,returning the iwmmxt helpers to passing env in as a parameter.
target-arm: Fix compilation failure for 64 bit hosts
Use the correct _ptr aliases for manipulating the pointer tothe fp_status; this fixes a compilation failure on 64 bit hosts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Stefan Weil <weil@mail.berlios.de>...
target-arm: Use correct float status for Neon int-float conversions
The Neon versions of int-float conversions must use the "standard FPSCR" rather than the default FPSCR. Implement this by having the helperfunctions take a pointer to the appropriate float_status value rather...
target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNs
Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires thatwe implement the set of negations and additions specified by the ARM ARM;plausible looking simplifications like turning (-A + B) into (B - A) or...
Fix typos in comments (neccessary -> necessary)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix typos in comments and code (occured -> occurred and related)
The code changed here is an unused data type name (evt_flush_occurred).
target-arm: Don't update base register on abort in Thumb T1 LDM
Make sure the base register isn't updated if it is in the load listfor a Thumb LDM (T1 encoding) which aborts partway through the load.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: fix LDMIA bug on page boundarytarget-arm: fix LDMIA bug on page boundary
When consecutive memory locations are on page boundary, a base register may beloaded before page fault occurs. After page fault handling, it losts the memorylocation information. To solve this problem, loading a base register has to put back....
target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structures
Correctly UNDEF for Neon VLD/VST "multiple structures" forms where thealign field is not valid.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Handle UNDEFs for Neon single element load/stores
Handle the UNDEF and UNPREDICTABLE cases for Neon "single element toone lane" VLD and "single element from one lane" VST.
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
move helpers.h to helper.h
This provides a consistent naming scheme across all targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Handle UNDEF cases for Neon invalid modified-immediates
For Neon "one register and a modified immediate value" forms, thecombination op=1 cmode=1111 is unallocated and should UNDEF.All instructions of this form also UNDEF if Q 1 and Vd<0> 1....
target-arm: Handle UNDEF cases for Neon 3-regs-different-widths
Add missing UNDEF checks for instructions in the Neon "3 registers ofdifferent widths" data processing space.
target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms
Add missing checks for cases which must UNDEF in the Neon "2 registers anda scalar" data processing instruction space.
target-arm: Handle UNDEF cases for VEXT
VEXT must UNDEF if Q 1 && (Vd<0> 1 || Vr<0> 1 || Vm<0> 1)
target-arm: Simplify checking of size field in Neon 2reg-misc forms
Many of the Neon "2 register misc" instruction forms require invalidsize fields to cause the instruction to UNDEF. Pull this informationout into an array; this simplifies the code and also means we can do...
target-arm: Handle UNDEF cases for Neon 2 register misc forms
Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> 1 || Vm<0> 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q 1 || Vm<0> 1...
target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF
Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF itrather than allowing the helper function to index off the endof the register file.
target-arm: Handle UNDEF cases for VDUP (scalar)
Handle the UNDEF cases for VDUP: imm4 x000 Q 1 && Vd<0> == 1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Collapse VSRI case into VSHL, VSLI
Collapse some switch cases for VSRI into those for VSHL, VSLI,since the bodies are the same. (This is not completely obviousfor the size < 3 case, but since for VSRI we know U=1 theGEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded...
target-arm: Use lookup table for size check on Neon 3-reg-same insns
Simplify the checks for invalid size values for the Neon "three registersof the same size" instruction forms (and add them where they were missing)by using a lookup table.
This includes adding symbolic constants for the op values in this space,...
target-arm: Handle UNDEF cases for Neon 3-regs-same insns
Correct the handling of UNDEF cases for the NEON "3 registers samesize" forms, by adding missing checks and rationalising some othersso they are done early enough to avoid leaking TCG temporaries....
target-arm: Simplify three-register pairwise code
Since we know that the case of (pairwise && q) has been caughtearlier, we can simplify the register setup code for each passin the three-register-same-size Neon loop.
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>...
target-arm: Handle UNDEF cases for Neon "2 regs and shift" insns
Correctly handle all the UNDEF cases for Neon instructions of the"2 registers and shift" form, and make sure that we check for thesecases early enough not to leak TCG temporaries.
arm: basic support for ARMv4/ARMv4T emulation
Currently target-arm/ assumes at least ARMv5 core. Add support forhandling also ARMv4/ARMv4T. This changes the following instructions:
BX
BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-arm: Use global env in iwmmxt_helper.c helpers
Use the global 'env' variable in the helper functions in iwmmxt_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Use global env in neon_helper.c helpers
Use the global 'env' variable in the helper functions in neon_helper.c.This means we don't need to pass env as an argument to them any more.
target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handling
Implementing the floating-point versions of VCLE #0 and VCLT #0 bydoing a GT comparison and inverting the result gives the wrongresult if the input is a NaN. Implement as a GT comparison with theoperands swapped instead....
target-arm: Fix VLD of single element to all lanes
Fix several bugs in VLD of single element to all lanes:
The "single element to all lanes" form of VLD1 differs from those forVLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded elementshould be written to one or two Dregs (rather than being a register...
target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space
Move the allocation and freeing of the TCG temp used for the address forNeon load/store instructions so that we don't allocate the temporaryuntil we've done enough decoding to know that the instruction is not...
target-arm: Fix TCG temporary leaks for scalar VMULL
Fix a TCG temporary leak when translating 32-bit scalar VMULL.
target-arm: Set Q bit for overflow in SMUAD and SMLAD
SMUAD and SMLAD are supposed to set the Q bit if the addition ofthe two 16x16 multiply products and optional accumulator overflowsconsidered as a signed value. However we were only doing this checkfor the addition of the accumulator, not when adding the products,...
target-arm: Fix UNDEF cases in Thumb load/store
Decode of Thumb load/store was merging together the cases of 'bit 11==0'(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work forvalid instruction patterns but meant that we would not UNDEF for the...
target-arm: Implement a minimal set of cp14 debug registers
Newer ARM kernels try to probe for whether the CPU has hardware breakpointsupport. For this to work QEMU has to implement a minimal set of the cp14debug registers. The architecture requires v7 cores to implement debug...
target-arm: Use TCG temporary leak debugging facilities
Use the new TCG temporary leak debugging facilities tocheck that each ARM instruction does not leak temporaries.
target-arm: Remove ad-hoc leak checking code
This commit removes the ad-hoc resource leak checking code fromtarget-arm. This includes replacing all uses of new_tmp() withtcg_temp_new_i32() and all uses of dead_tmp() withtcg_temp_free_i32().
target-arm: Set carry flag correctly for Thumb2 ORNS
The code for Thumb2 ORNS (or negated and set flags) was trashinga TCG input register which was needed later for use in calculatingflags, with the effect that the carry flag was always set withthe wrong sense. Fix this by using the TCG orc op instead of...
target-arm: Handle VMOV between two core and VFP single regs
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry andVMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and apair of VFP single precision registers):
target-arm: Don't decode old cp15 WFI instructions on v7 cores
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-classinstruction, but in previous versions this functionality was providedvia a cp15 coprocessor register. Add correct feature checks to the...
target-arm: Fix shift by immediate and narrow where src, dest overlap
For Neon shifts by immediate and narrow, correctly handle the casewhere the source registers and the destination registers overlap(the second pass should use the original register contents, not the...
target-arm: Refactor to pull narrowing decode into separate function
Pull the code which decodes narrowing operations as being eithersigned/unsigned saturate or plain out into its own function.
target-arm: fix Neon VQSHRN and VSHRN.
Call the normal shift helpers instead of the rounding ones.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: fix decoding of Neon 64 bit shifts.
Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN,VQRSHRN, VQRSHRUN, taking into account whether inputs are unsignedor not.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Move Neon VZIP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsogive the correct answers where the inline implementation did not....
target-arm: Move Neon VUZP to helper functions
Move the implementation of the Neon VUZP unzip instruction from inlinecode to helper functions. (At 50+ TCG ops it was well over therecommended limit for coding inline.) The helper implementations alsofix the handling of the quadword version of the instruction....
target-arm: Correct conversion of Thumb Neon dp encodings into ARM
We handle Thumb Neon data processing instructions by converting theminto the equivalent ARM encoding, as the two are very close. Howeverthe ARM encoding should have bit 28 set, not clear. This wasn't causing...
target-arm: Fix Neon VQDMLSL instruction
For VQDMLSL, negation has to occur after saturation, not before.
target-arm: Refactor handling of VQDMULL
Refactor the handling of VQDMULL so that it is dealt with inits own if() case rather than together with the accumulatinginstructions.
target-arm: Implement VMULL.P8
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiplyinstruction).
target-arm: Use standard FPSCR for Neon half-precision operations
The Neon half-precision conversion operations (VCVT.F16.F32 andVCVT.F32.F16) use ARM standard floating-point arithmetic, unlikethe VFP versions (VCVTB and VCVTT).
target-arm: implement vsli.64, vsri.64
target-arm: fix VSHLL Neon instruction.
Fix bit mask used when widening the result of shift on narrow input.
target-arm: Fix VQMOVUN Neon instruction.
VQMOVUN does a signed-to-unsigned saturating conversion. This isdifferent from both the signed-to-signed and unsigned-to-unsignedconversions already implemented, so we need a new set of helperfunctions (neon_unarrow_sat*)....
target-arm: Fix decoding of preload and memory hint space
Correct the decoding of the ARM preload and memory hint space,by adding decoding of PLI, PLDW and the v7MP unallocated hintspace. This commit also corrects a slightly overexuberantdecoding of PLD which was not checking that bit 4...
target-arm: Fix decoding of Thumb preload and hint space
Refine the decoding of the Thumb preload and hint space, so weUNDEF on the patterns that are supposed to UNDEF rather than NOP.We also move the tests for this space earlier, so we don't emitharmless but unnecessary address generation code for preload...
Set the right overflow bit for neon 32 and 64 bit saturating add/sub.
target-arm: Fix Neon vsra instructions.
This patch fixes the errors reported by my tests in VSRA.
Support saturation with shift=0.
This patch fixes corner-case saturations, when the target range iszero. It merely removes the guard against (sh == 0), and makes:_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag_usat(0x87654321, 0) return 0 and set the saturation flag...
target-arm: Fix garbage collection of temporaries in Neon emulation.
Fix garbage collection of temporaries in Neon emulation.
target-arm: Fix loading of scalar value for Neon multiply-by-scalar
Fix the register and part of register we get the scalar from inthe various "multiply vector by scalar" ops (VMUL by scalarand friends).