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target-openrisc: Use new qemu_ld/st opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>Acked-by: Jia Liu <proljc@gmail.com>Signed-off-by: Jia Liu <proljc@gmail.com>
openrisc: Fix spelling in comment (transaltion -> translation)
I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Jia Liu <proljc@gmail.com>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
target-openrisc: Remove unnecessary code generated by jump instructions
The sr_f variable is only used for the l.bf and l.bnf instructions.For clarity the code is also rewritten using a switch statement insteadof if chaining.
Signed-off-by: Sebastian Macke <sebastian@macke.de>...
target-openrisc: Speed up move instruction
The OpenRISC architecture does not have its own move registerinstruction. Instead it uses either "l.addi rd, r0, x" or"l.ori rd, rs, 0" or "l.or rd, rx, r0"
The l.ori instruction is automatically optimized but not the l.addi instruction....
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
log: Change log_cpu_state[_mask]() argument to CPUState
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turncpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is nolonger needed.
Add documentation and make the functions available through qemu/log.h...
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
qemu-log: Remove qemu_log_try_set_file() and its users
Remove the function qemu_log_try_set_file() and its users (whichare all in TCG code generation functions for various targets).This function was added to abstract out code which was originallywritten as "if (!logfile) logfile = stderr;" in order that BUG:...
misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-or32: Add system instructions
Add OpenRISC system instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-or32: Add instruction translation
Add OpenRISC instruction tanslation routines.
target-or32: Add target stubs and QOM cpu
Add OpenRISC target stubs, QOM cpu and basic machine.