root / include / hw / pci / pci.h @ 22773d60
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1 | 87ecb68b | pbrook | #ifndef QEMU_PCI_H
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2 | 87ecb68b | pbrook | #define QEMU_PCI_H
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3 | 87ecb68b | pbrook | |
4 | 376253ec | aliguori | #include "qemu-common.h" |
5 | 376253ec | aliguori | |
6 | c759b24f | Michael S. Tsirkin | #include "hw/qdev.h" |
7 | 022c62cb | Paolo Bonzini | #include "exec/memory.h" |
8 | 9c17d615 | Paolo Bonzini | #include "sysemu/dma.h" |
9 | 6b1b92d3 | Paul Brook | |
10 | 87ecb68b | pbrook | /* PCI includes legacy ISA access. */
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11 | 0d09e41a | Paolo Bonzini | #include "hw/isa/isa.h" |
12 | 87ecb68b | pbrook | |
13 | c759b24f | Michael S. Tsirkin | #include "hw/pci/pcie.h" |
14 | 0428527c | Isaku Yamahata | |
15 | 87ecb68b | pbrook | /* PCI bus */
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16 | 87ecb68b | pbrook | |
17 | 3ae80618 | aliguori | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
18 | 3ae80618 | aliguori | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
19 | 3ae80618 | aliguori | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
20 | 90a20dbb | Isaku Yamahata | #define PCI_SLOT_MAX 32 |
21 | 6fa84913 | Isaku Yamahata | #define PCI_FUNC_MAX 8 |
22 | 3ae80618 | aliguori | |
23 | a770dc7e | aliguori | /* Class, Vendor and Device IDs from Linux's pci_ids.h */
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24 | c759b24f | Michael S. Tsirkin | #include "hw/pci/pci_ids.h" |
25 | 173a543b | blueswir1 | |
26 | a770dc7e | aliguori | /* QEMU-specific Vendor and Device ID definitions */
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27 | 6f338c34 | aliguori | |
28 | a770dc7e | aliguori | /* IBM (0x1014) */
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29 | a770dc7e | aliguori | #define PCI_DEVICE_ID_IBM_440GX 0x027f |
30 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff |
31 | deb54399 | aliguori | |
32 | a770dc7e | aliguori | /* Hitachi (0x1054) */
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33 | deb54399 | aliguori | #define PCI_VENDOR_ID_HITACHI 0x1054 |
34 | a770dc7e | aliguori | #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e |
35 | deb54399 | aliguori | |
36 | a770dc7e | aliguori | /* Apple (0x106b) */
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37 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_343S1201 0x0010 |
38 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e |
39 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f |
40 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022 |
41 | a770dc7e | aliguori | #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f |
42 | deb54399 | aliguori | |
43 | a770dc7e | aliguori | /* Realtek (0x10ec) */
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44 | a770dc7e | aliguori | #define PCI_DEVICE_ID_REALTEK_8029 0x8029 |
45 | deb54399 | aliguori | |
46 | a770dc7e | aliguori | /* Xilinx (0x10ee) */
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47 | a770dc7e | aliguori | #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300 |
48 | deb54399 | aliguori | |
49 | a770dc7e | aliguori | /* Marvell (0x11ab) */
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50 | a770dc7e | aliguori | #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620 |
51 | deb54399 | aliguori | |
52 | a770dc7e | aliguori | /* QEMU/Bochs VGA (0x1234) */
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53 | 4ebcf884 | blueswir1 | #define PCI_VENDOR_ID_QEMU 0x1234 |
54 | 4ebcf884 | blueswir1 | #define PCI_DEVICE_ID_QEMU_VGA 0x1111 |
55 | 4ebcf884 | blueswir1 | |
56 | a770dc7e | aliguori | /* VMWare (0x15ad) */
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57 | deb54399 | aliguori | #define PCI_VENDOR_ID_VMWARE 0x15ad |
58 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
59 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
60 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
61 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
62 | deb54399 | aliguori | #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
63 | 786fd2b0 | Dmitry Fleytman | #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 |
64 | deb54399 | aliguori | |
65 | cef3017c | aliguori | /* Intel (0x8086) */
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66 | a770dc7e | aliguori | #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 |
67 | d6fd1e66 | Stefan Weil | #define PCI_DEVICE_ID_INTEL_82557 0x1229 |
68 | 1a5a86fb | Alexander Graf | #define PCI_DEVICE_ID_INTEL_82801IR 0x2922 |
69 | 74c62ba8 | aurel32 | |
70 | deb54399 | aliguori | /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
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71 | d350d97d | aliguori | #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
72 | d350d97d | aliguori | #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
73 | d350d97d | aliguori | #define PCI_SUBDEVICE_ID_QEMU 0x1100 |
74 | d350d97d | aliguori | |
75 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_NET 0x1000 |
76 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 |
77 | d350d97d | aliguori | #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 |
78 | 14d50bef | aliguori | #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 |
79 | 973abc7f | Stefan Hajnoczi | #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 |
80 | 16c915ba | Amit Shah | #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 |
81 | 13744bd0 | Paolo Bonzini | #define PCI_DEVICE_ID_VIRTIO_9P 0x1009 |
82 | d350d97d | aliguori | |
83 | 5c03a254 | Paolo Bonzini | #define PCI_VENDOR_ID_REDHAT 0x1b36 |
84 | 5c03a254 | Paolo Bonzini | #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 |
85 | 5c03a254 | Paolo Bonzini | #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 |
86 | 5c03a254 | Paolo Bonzini | #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 |
87 | 5c03a254 | Paolo Bonzini | #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 |
88 | 22773d60 | Michael S. Tsirkin | #define PCI_DEVICE_ID_REDHAT_TEST 0x0005 |
89 | 5c03a254 | Paolo Bonzini | #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 |
90 | 5c03a254 | Paolo Bonzini | |
91 | 4f8589e1 | Isaku Yamahata | #define FMT_PCIBUS PRIx64
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92 | 6e355d90 | Isaku Yamahata | |
93 | 87ecb68b | pbrook | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
94 | 87ecb68b | pbrook | uint32_t address, uint32_t data, int len);
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95 | 87ecb68b | pbrook | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
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96 | 87ecb68b | pbrook | uint32_t address, int len);
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97 | 87ecb68b | pbrook | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
98 | 6e355d90 | Isaku Yamahata | pcibus_t addr, pcibus_t size, int type);
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99 | f90c2bcd | Alex Williamson | typedef void PCIUnregisterFunc(PCIDevice *pci_dev); |
100 | 87ecb68b | pbrook | |
101 | 87ecb68b | pbrook | typedef struct PCIIORegion { |
102 | 6e355d90 | Isaku Yamahata | pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
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103 | 6e355d90 | Isaku Yamahata | #define PCI_BAR_UNMAPPED (~(pcibus_t)0) |
104 | 6e355d90 | Isaku Yamahata | pcibus_t size; |
105 | 87ecb68b | pbrook | uint8_t type; |
106 | 79ff8cb0 | Avi Kivity | MemoryRegion *memory; |
107 | 5968eca3 | Avi Kivity | MemoryRegion *address_space; |
108 | 87ecb68b | pbrook | } PCIIORegion; |
109 | 87ecb68b | pbrook | |
110 | 87ecb68b | pbrook | #define PCI_ROM_SLOT 6 |
111 | 87ecb68b | pbrook | #define PCI_NUM_REGIONS 7 |
112 | 87ecb68b | pbrook | |
113 | e01fd687 | Alex Williamson | enum {
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114 | e01fd687 | Alex Williamson | QEMU_PCI_VGA_MEM, |
115 | e01fd687 | Alex Williamson | QEMU_PCI_VGA_IO_LO, |
116 | e01fd687 | Alex Williamson | QEMU_PCI_VGA_IO_HI, |
117 | e01fd687 | Alex Williamson | QEMU_PCI_VGA_NUM_REGIONS, |
118 | e01fd687 | Alex Williamson | }; |
119 | e01fd687 | Alex Williamson | |
120 | e01fd687 | Alex Williamson | #define QEMU_PCI_VGA_MEM_BASE 0xa0000 |
121 | e01fd687 | Alex Williamson | #define QEMU_PCI_VGA_MEM_SIZE 0x20000 |
122 | e01fd687 | Alex Williamson | #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0 |
123 | e01fd687 | Alex Williamson | #define QEMU_PCI_VGA_IO_LO_SIZE 0xc |
124 | e01fd687 | Alex Williamson | #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0 |
125 | e01fd687 | Alex Williamson | #define QEMU_PCI_VGA_IO_HI_SIZE 0x20 |
126 | e01fd687 | Alex Williamson | |
127 | c759b24f | Michael S. Tsirkin | #include "hw/pci/pci_regs.h" |
128 | fb58a897 | Isaku Yamahata | |
129 | fb58a897 | Isaku Yamahata | /* PCI HEADER_TYPE */
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130 | 6407f373 | Isaku Yamahata | #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80 |
131 | 8098ed41 | aurel32 | |
132 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config header */
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133 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_HEADER_SIZE 0x40 |
134 | b7ee1603 | Michael S. Tsirkin | /* Size of the standard PCI config space */
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135 | b7ee1603 | Michael S. Tsirkin | #define PCI_CONFIG_SPACE_SIZE 0x100 |
136 | a9f49946 | Isaku Yamahata | /* Size of the standart PCIe config space: 4KB */
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137 | a9f49946 | Isaku Yamahata | #define PCIE_CONFIG_SPACE_SIZE 0x1000 |
138 | b7ee1603 | Michael S. Tsirkin | |
139 | e369cad7 | Isaku Yamahata | #define PCI_NUM_PINS 4 /* A-D */ |
140 | e369cad7 | Isaku Yamahata | |
141 | 02eb84d0 | Michael S. Tsirkin | /* Bits in cap_present field. */
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142 | 02eb84d0 | Michael S. Tsirkin | enum {
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143 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_MSI = 0x1,
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144 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_MSIX = 0x2,
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145 | e4c7d2ae | Isaku Yamahata | QEMU_PCI_CAP_EXPRESS = 0x4,
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146 | 49823868 | Isaku Yamahata | |
147 | 49823868 | Isaku Yamahata | /* multifunction capable device */
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148 | e4c7d2ae | Isaku Yamahata | #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 |
149 | 49823868 | Isaku Yamahata | QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
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150 | b1aeb926 | Isaku Yamahata | |
151 | b1aeb926 | Isaku Yamahata | /* command register SERR bit enabled */
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152 | b1aeb926 | Isaku Yamahata | #define QEMU_PCI_CAP_SERR_BITNR 4 |
153 | b1aeb926 | Isaku Yamahata | QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
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154 | 1dc324d2 | Michael S. Tsirkin | /* Standard hot plug controller. */
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155 | 1dc324d2 | Michael S. Tsirkin | #define QEMU_PCI_SHPC_BITNR 5 |
156 | 1dc324d2 | Michael S. Tsirkin | QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
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157 | 762833b3 | Michael S. Tsirkin | #define QEMU_PCI_SLOTID_BITNR 6 |
158 | 762833b3 | Michael S. Tsirkin | QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
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159 | 02eb84d0 | Michael S. Tsirkin | }; |
160 | 02eb84d0 | Michael S. Tsirkin | |
161 | 40021f08 | Anthony Liguori | #define TYPE_PCI_DEVICE "pci-device" |
162 | 40021f08 | Anthony Liguori | #define PCI_DEVICE(obj) \
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163 | 40021f08 | Anthony Liguori | OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE) |
164 | 40021f08 | Anthony Liguori | #define PCI_DEVICE_CLASS(klass) \
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165 | 40021f08 | Anthony Liguori | OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE) |
166 | 40021f08 | Anthony Liguori | #define PCI_DEVICE_GET_CLASS(obj) \
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167 | 40021f08 | Anthony Liguori | OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE) |
168 | 40021f08 | Anthony Liguori | |
169 | 3afa9bb4 | Michael S. Tsirkin | typedef struct PCIINTxRoute { |
170 | 3afa9bb4 | Michael S. Tsirkin | enum {
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171 | 3afa9bb4 | Michael S. Tsirkin | PCI_INTX_ENABLED, |
172 | 3afa9bb4 | Michael S. Tsirkin | PCI_INTX_INVERTED, |
173 | 3afa9bb4 | Michael S. Tsirkin | PCI_INTX_DISABLED, |
174 | 3afa9bb4 | Michael S. Tsirkin | } mode; |
175 | 3afa9bb4 | Michael S. Tsirkin | int irq;
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176 | 3afa9bb4 | Michael S. Tsirkin | } PCIINTxRoute; |
177 | 3afa9bb4 | Michael S. Tsirkin | |
178 | 40021f08 | Anthony Liguori | typedef struct PCIDeviceClass { |
179 | 40021f08 | Anthony Liguori | DeviceClass parent_class; |
180 | 40021f08 | Anthony Liguori | |
181 | 40021f08 | Anthony Liguori | int (*init)(PCIDevice *dev);
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182 | 40021f08 | Anthony Liguori | PCIUnregisterFunc *exit; |
183 | 40021f08 | Anthony Liguori | PCIConfigReadFunc *config_read; |
184 | 40021f08 | Anthony Liguori | PCIConfigWriteFunc *config_write; |
185 | 40021f08 | Anthony Liguori | |
186 | 40021f08 | Anthony Liguori | uint16_t vendor_id; |
187 | 40021f08 | Anthony Liguori | uint16_t device_id; |
188 | 40021f08 | Anthony Liguori | uint8_t revision; |
189 | 40021f08 | Anthony Liguori | uint16_t class_id; |
190 | 40021f08 | Anthony Liguori | uint16_t subsystem_vendor_id; /* only for header type = 0 */
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191 | 40021f08 | Anthony Liguori | uint16_t subsystem_id; /* only for header type = 0 */
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192 | 40021f08 | Anthony Liguori | |
193 | 40021f08 | Anthony Liguori | /*
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194 | 40021f08 | Anthony Liguori | * pci-to-pci bridge or normal device.
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195 | 40021f08 | Anthony Liguori | * This doesn't mean pci host switch.
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196 | 40021f08 | Anthony Liguori | * When card bus bridge is supported, this would be enhanced.
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197 | 40021f08 | Anthony Liguori | */
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198 | 40021f08 | Anthony Liguori | int is_bridge;
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199 | 40021f08 | Anthony Liguori | |
200 | 40021f08 | Anthony Liguori | /* pcie stuff */
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201 | 40021f08 | Anthony Liguori | int is_express; /* is this device pci express? */ |
202 | 40021f08 | Anthony Liguori | |
203 | 40021f08 | Anthony Liguori | /* device isn't hot-pluggable */
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204 | 40021f08 | Anthony Liguori | int no_hotplug;
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205 | 40021f08 | Anthony Liguori | |
206 | 40021f08 | Anthony Liguori | /* rom bar */
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207 | 40021f08 | Anthony Liguori | const char *romfile; |
208 | 40021f08 | Anthony Liguori | } PCIDeviceClass; |
209 | 40021f08 | Anthony Liguori | |
210 | 0ae16251 | Jan Kiszka | typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev); |
211 | 2cdfe53c | Jan Kiszka | typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector, |
212 | 2cdfe53c | Jan Kiszka | MSIMessage msg); |
213 | 2cdfe53c | Jan Kiszka | typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector); |
214 | bbef882c | Michael S. Tsirkin | typedef void (*MSIVectorPollNotifier)(PCIDevice *dev, |
215 | bbef882c | Michael S. Tsirkin | unsigned int vector_start, |
216 | bbef882c | Michael S. Tsirkin | unsigned int vector_end); |
217 | 2cdfe53c | Jan Kiszka | |
218 | 87ecb68b | pbrook | struct PCIDevice {
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219 | 6b1b92d3 | Paul Brook | DeviceState qdev; |
220 | 5fa45de5 | David Gibson | |
221 | 87ecb68b | pbrook | /* PCI config space */
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222 | a9f49946 | Isaku Yamahata | uint8_t *config; |
223 | b7ee1603 | Michael S. Tsirkin | |
224 | ebabb67a | Stefan Weil | /* Used to enable config checks on load. Note that writable bits are
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225 | bd4b65ee | Michael S. Tsirkin | * never checked even if set in cmask. */
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226 | a9f49946 | Isaku Yamahata | uint8_t *cmask; |
227 | bd4b65ee | Michael S. Tsirkin | |
228 | b7ee1603 | Michael S. Tsirkin | /* Used to implement R/W bytes */
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229 | a9f49946 | Isaku Yamahata | uint8_t *wmask; |
230 | 87ecb68b | pbrook | |
231 | 92ba5f51 | Isaku Yamahata | /* Used to implement RW1C(Write 1 to Clear) bytes */
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232 | 92ba5f51 | Isaku Yamahata | uint8_t *w1cmask; |
233 | 92ba5f51 | Isaku Yamahata | |
234 | 6f4cbd39 | Michael S. Tsirkin | /* Used to allocate config space for capabilities. */
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235 | a9f49946 | Isaku Yamahata | uint8_t *used; |
236 | 6f4cbd39 | Michael S. Tsirkin | |
237 | 87ecb68b | pbrook | /* the following fields are read only */
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238 | 87ecb68b | pbrook | PCIBus *bus; |
239 | 09f1bbcd | Michael Roth | int32_t devfn; |
240 | 87ecb68b | pbrook | char name[64]; |
241 | 87ecb68b | pbrook | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
242 | 817dcc53 | Avi Kivity | AddressSpace bus_master_as; |
243 | 1c380f94 | Avi Kivity | MemoryRegion bus_master_enable_region; |
244 | 5fa45de5 | David Gibson | DMAContext *dma; |
245 | 87ecb68b | pbrook | |
246 | 87ecb68b | pbrook | /* do not access the following fields */
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247 | 87ecb68b | pbrook | PCIConfigReadFunc *config_read; |
248 | 87ecb68b | pbrook | PCIConfigWriteFunc *config_write; |
249 | 87ecb68b | pbrook | |
250 | 87ecb68b | pbrook | /* IRQ objects for the INTA-INTD pins. */
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251 | 87ecb68b | pbrook | qemu_irq *irq; |
252 | 87ecb68b | pbrook | |
253 | e01fd687 | Alex Williamson | /* Legacy PCI VGA regions */
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254 | e01fd687 | Alex Williamson | MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS]; |
255 | e01fd687 | Alex Williamson | bool has_vga;
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256 | e01fd687 | Alex Williamson | |
257 | 87ecb68b | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
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258 | d036bb21 | Michael S. Tsirkin | uint8_t irq_state; |
259 | 02eb84d0 | Michael S. Tsirkin | |
260 | 02eb84d0 | Michael S. Tsirkin | /* Capability bits */
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261 | 02eb84d0 | Michael S. Tsirkin | uint32_t cap_present; |
262 | 02eb84d0 | Michael S. Tsirkin | |
263 | 02eb84d0 | Michael S. Tsirkin | /* Offset of MSI-X capability in config space */
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264 | 02eb84d0 | Michael S. Tsirkin | uint8_t msix_cap; |
265 | 02eb84d0 | Michael S. Tsirkin | |
266 | 02eb84d0 | Michael S. Tsirkin | /* MSI-X entries */
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267 | 02eb84d0 | Michael S. Tsirkin | int msix_entries_nr;
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268 | 02eb84d0 | Michael S. Tsirkin | |
269 | d35e428c | Alex Williamson | /* Space to store MSIX table & pending bit array */
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270 | d35e428c | Alex Williamson | uint8_t *msix_table; |
271 | d35e428c | Alex Williamson | uint8_t *msix_pba; |
272 | 53f94925 | Alex Williamson | /* MemoryRegion container for msix exclusive BAR setup */
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273 | 53f94925 | Alex Williamson | MemoryRegion msix_exclusive_bar; |
274 | d35e428c | Alex Williamson | /* Memory Regions for MSIX table and pending bit entries. */
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275 | d35e428c | Alex Williamson | MemoryRegion msix_table_mmio; |
276 | d35e428c | Alex Williamson | MemoryRegion msix_pba_mmio; |
277 | 02eb84d0 | Michael S. Tsirkin | /* Reference-count for entries actually in use by driver. */
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278 | 02eb84d0 | Michael S. Tsirkin | unsigned *msix_entry_used;
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279 | 50322249 | Michael S. Tsirkin | /* MSIX function mask set or MSIX disabled */
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280 | 50322249 | Michael S. Tsirkin | bool msix_function_masked;
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281 | f16c4abf | Juan Quintela | /* Version id needed for VMState */
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282 | f16c4abf | Juan Quintela | int32_t version_id; |
283 | c2039bd0 | Anthony Liguori | |
284 | e4c7d2ae | Isaku Yamahata | /* Offset of MSI capability in config space */
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285 | e4c7d2ae | Isaku Yamahata | uint8_t msi_cap; |
286 | e4c7d2ae | Isaku Yamahata | |
287 | 0428527c | Isaku Yamahata | /* PCI Express */
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288 | 0428527c | Isaku Yamahata | PCIExpressDevice exp; |
289 | 0428527c | Isaku Yamahata | |
290 | 1dc324d2 | Michael S. Tsirkin | /* SHPC */
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291 | 1dc324d2 | Michael S. Tsirkin | SHPCDevice *shpc; |
292 | 1dc324d2 | Michael S. Tsirkin | |
293 | c2039bd0 | Anthony Liguori | /* Location of option rom */
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294 | 8c52c8f3 | Gerd Hoffmann | char *romfile;
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295 | 14caaf7f | Avi Kivity | bool has_rom;
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296 | 14caaf7f | Avi Kivity | MemoryRegion rom; |
297 | 88169ddf | Gerd Hoffmann | uint32_t rom_bar; |
298 | 2cdfe53c | Jan Kiszka | |
299 | 0ae16251 | Jan Kiszka | /* INTx routing notifier */
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300 | 0ae16251 | Jan Kiszka | PCIINTxRoutingNotifier intx_routing_notifier; |
301 | 0ae16251 | Jan Kiszka | |
302 | 2cdfe53c | Jan Kiszka | /* MSI-X notifiers */
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303 | 2cdfe53c | Jan Kiszka | MSIVectorUseNotifier msix_vector_use_notifier; |
304 | 2cdfe53c | Jan Kiszka | MSIVectorReleaseNotifier msix_vector_release_notifier; |
305 | bbef882c | Michael S. Tsirkin | MSIVectorPollNotifier msix_vector_poll_notifier; |
306 | 87ecb68b | pbrook | }; |
307 | 87ecb68b | pbrook | |
308 | e824b2cc | Avi Kivity | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
309 | e824b2cc | Avi Kivity | uint8_t attr, MemoryRegion *memory); |
310 | e01fd687 | Alex Williamson | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
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311 | e01fd687 | Alex Williamson | MemoryRegion *io_lo, MemoryRegion *io_hi); |
312 | e01fd687 | Alex Williamson | void pci_unregister_vga(PCIDevice *pci_dev);
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313 | 16a96f28 | Avi Kivity | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
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314 | 87ecb68b | pbrook | |
315 | ca77089d | Isaku Yamahata | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
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316 | ca77089d | Isaku Yamahata | uint8_t offset, uint8_t size); |
317 | 6f4cbd39 | Michael S. Tsirkin | |
318 | 6f4cbd39 | Michael S. Tsirkin | void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
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319 | 6f4cbd39 | Michael S. Tsirkin | |
320 | 6f4cbd39 | Michael S. Tsirkin | uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id); |
321 | 6f4cbd39 | Michael S. Tsirkin | |
322 | 6f4cbd39 | Michael S. Tsirkin | |
323 | 87ecb68b | pbrook | uint32_t pci_default_read_config(PCIDevice *d, |
324 | 87ecb68b | pbrook | uint32_t address, int len);
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325 | 87ecb68b | pbrook | void pci_default_write_config(PCIDevice *d,
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326 | 87ecb68b | pbrook | uint32_t address, uint32_t val, int len);
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327 | 87ecb68b | pbrook | void pci_device_save(PCIDevice *s, QEMUFile *f);
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328 | 87ecb68b | pbrook | int pci_device_load(PCIDevice *s, QEMUFile *f);
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329 | f5e6fed8 | Avi Kivity | MemoryRegion *pci_address_space(PCIDevice *dev); |
330 | e11d6439 | Richard Henderson | MemoryRegion *pci_address_space_io(PCIDevice *dev); |
331 | 87ecb68b | pbrook | |
332 | 5d4e84c8 | Juan Quintela | typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); |
333 | 87ecb68b | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
334 | 3afa9bb4 | Michael S. Tsirkin | typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); |
335 | e927d487 | Michael S. Tsirkin | |
336 | e927d487 | Michael S. Tsirkin | typedef enum { |
337 | e927d487 | Michael S. Tsirkin | PCI_HOTPLUG_DISABLED, |
338 | e927d487 | Michael S. Tsirkin | PCI_HOTPLUG_ENABLED, |
339 | e927d487 | Michael S. Tsirkin | PCI_COLDPLUG_ENABLED, |
340 | e927d487 | Michael S. Tsirkin | } PCIHotplugState; |
341 | e927d487 | Michael S. Tsirkin | |
342 | e927d487 | Michael S. Tsirkin | typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, |
343 | e927d487 | Michael S. Tsirkin | PCIHotplugState state); |
344 | cf09458d | Alex Williamson | |
345 | cf09458d | Alex Williamson | #define TYPE_PCI_BUS "PCI" |
346 | cf09458d | Alex Williamson | #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
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347 | cf09458d | Alex Williamson | #define TYPE_PCIE_BUS "PCIE" |
348 | cf09458d | Alex Williamson | |
349 | 8c0bf9e2 | Alex Williamson | bool pci_bus_is_express(PCIBus *bus);
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350 | 0889464a | Alex Williamson | bool pci_bus_is_root(PCIBus *bus);
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351 | 21eea4b3 | Gerd Hoffmann | void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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352 | 1e39101c | Avi Kivity | const char *name, |
353 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
354 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
355 | 60a0e443 | Alex Williamson | uint8_t devfn_min, const char *typename); |
356 | 1e39101c | Avi Kivity | PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
357 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
358 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
359 | 60a0e443 | Alex Williamson | uint8_t devfn_min, const char *typename); |
360 | 21eea4b3 | Gerd Hoffmann | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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361 | 21eea4b3 | Gerd Hoffmann | void *irq_opaque, int nirq); |
362 | 9ddf8437 | Isaku Yamahata | int pci_bus_get_irq_level(PCIBus *bus, int irq_num); |
363 | 87c30546 | Isaku Yamahata | void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
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364 | 91e56159 | Isaku Yamahata | /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
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365 | 91e56159 | Isaku Yamahata | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin); |
366 | 02e2da45 | Paul Brook | PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
367 | 02e2da45 | Paul Brook | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
368 | 1e39101c | Avi Kivity | void *irq_opaque,
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369 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem, |
370 | aee97b84 | Avi Kivity | MemoryRegion *address_space_io, |
371 | 60a0e443 | Alex Williamson | uint8_t devfn_min, int nirq, const char *typename); |
372 | 3afa9bb4 | Michael S. Tsirkin | void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
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373 | 3afa9bb4 | Michael S. Tsirkin | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
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374 | d6e65d54 | Alex Williamson | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
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375 | 0ae16251 | Jan Kiszka | void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
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376 | 0ae16251 | Jan Kiszka | void pci_device_set_intx_routing_notifier(PCIDevice *dev,
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377 | 0ae16251 | Jan Kiszka | PCIINTxRoutingNotifier notifier); |
378 | 0ead87c8 | Isaku Yamahata | void pci_device_reset(PCIDevice *dev);
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379 | 9bb33586 | Isaku Yamahata | void pci_bus_reset(PCIBus *bus);
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380 | 87ecb68b | pbrook | |
381 | 5607c388 | Markus Armbruster | PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
382 | 5607c388 | Markus Armbruster | const char *default_devaddr); |
383 | 07caea31 | Markus Armbruster | PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
384 | 07caea31 | Markus Armbruster | const char *default_devaddr); |
385 | 129d42fb | Aurelien Jarno | |
386 | 129d42fb | Aurelien Jarno | PCIDevice *pci_vga_init(PCIBus *bus); |
387 | 129d42fb | Aurelien Jarno | |
388 | 87ecb68b | pbrook | int pci_bus_num(PCIBus *s);
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389 | 7aa8cbb9 | Anthony PERARD | void pci_for_each_device(PCIBus *bus, int bus_num, |
390 | 7aa8cbb9 | Anthony PERARD | void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), |
391 | 7aa8cbb9 | Anthony PERARD | void *opaque);
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392 | c469e1dd | Isaku Yamahata | PCIBus *pci_find_root_bus(int domain);
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393 | e075e788 | Isaku Yamahata | int pci_find_domain(const PCIBus *bus); |
394 | 5256d8bf | Isaku Yamahata | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
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395 | f3006dd1 | Isaku Yamahata | int pci_qdev_find_device(const char *id, PCIDevice **pdev); |
396 | 49bd1458 | Markus Armbruster | PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr); |
397 | 87ecb68b | pbrook | |
398 | e9283f8b | Jan Kiszka | int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
399 | e9283f8b | Jan Kiszka | unsigned *slotp);
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400 | 880345c4 | aliguori | |
401 | 4c92325b | Isaku Yamahata | void pci_device_deassert_intx(PCIDevice *dev);
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402 | 4c92325b | Isaku Yamahata | |
403 | 5fa45de5 | David Gibson | typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int); |
404 | 5fa45de5 | David Gibson | |
405 | 5fa45de5 | David Gibson | void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque); |
406 | 5fa45de5 | David Gibson | |
407 | deb54399 | aliguori | static inline void |
408 | 64d50b8b | Michael S. Tsirkin | pci_set_byte(uint8_t *config, uint8_t val) |
409 | 64d50b8b | Michael S. Tsirkin | { |
410 | 64d50b8b | Michael S. Tsirkin | *config = val; |
411 | 64d50b8b | Michael S. Tsirkin | } |
412 | 64d50b8b | Michael S. Tsirkin | |
413 | 64d50b8b | Michael S. Tsirkin | static inline uint8_t |
414 | cb95c2e4 | Stefan Weil | pci_get_byte(const uint8_t *config)
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415 | 64d50b8b | Michael S. Tsirkin | { |
416 | 64d50b8b | Michael S. Tsirkin | return *config;
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417 | 64d50b8b | Michael S. Tsirkin | } |
418 | 64d50b8b | Michael S. Tsirkin | |
419 | 64d50b8b | Michael S. Tsirkin | static inline void |
420 | 14e12559 | Michael S. Tsirkin | pci_set_word(uint8_t *config, uint16_t val) |
421 | 14e12559 | Michael S. Tsirkin | { |
422 | 14e12559 | Michael S. Tsirkin | cpu_to_le16wu((uint16_t *)config, val); |
423 | 14e12559 | Michael S. Tsirkin | } |
424 | 14e12559 | Michael S. Tsirkin | |
425 | 14e12559 | Michael S. Tsirkin | static inline uint16_t |
426 | cb95c2e4 | Stefan Weil | pci_get_word(const uint8_t *config)
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427 | 14e12559 | Michael S. Tsirkin | { |
428 | cb95c2e4 | Stefan Weil | return le16_to_cpupu((const uint16_t *)config); |
429 | 14e12559 | Michael S. Tsirkin | } |
430 | 14e12559 | Michael S. Tsirkin | |
431 | 14e12559 | Michael S. Tsirkin | static inline void |
432 | 14e12559 | Michael S. Tsirkin | pci_set_long(uint8_t *config, uint32_t val) |
433 | 14e12559 | Michael S. Tsirkin | { |
434 | 14e12559 | Michael S. Tsirkin | cpu_to_le32wu((uint32_t *)config, val); |
435 | 14e12559 | Michael S. Tsirkin | } |
436 | 14e12559 | Michael S. Tsirkin | |
437 | 14e12559 | Michael S. Tsirkin | static inline uint32_t |
438 | cb95c2e4 | Stefan Weil | pci_get_long(const uint8_t *config)
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439 | 14e12559 | Michael S. Tsirkin | { |
440 | cb95c2e4 | Stefan Weil | return le32_to_cpupu((const uint32_t *)config); |
441 | 14e12559 | Michael S. Tsirkin | } |
442 | 14e12559 | Michael S. Tsirkin | |
443 | 14e12559 | Michael S. Tsirkin | static inline void |
444 | fb5ce7d2 | Isaku Yamahata | pci_set_quad(uint8_t *config, uint64_t val) |
445 | fb5ce7d2 | Isaku Yamahata | { |
446 | fb5ce7d2 | Isaku Yamahata | cpu_to_le64w((uint64_t *)config, val); |
447 | fb5ce7d2 | Isaku Yamahata | } |
448 | fb5ce7d2 | Isaku Yamahata | |
449 | fb5ce7d2 | Isaku Yamahata | static inline uint64_t |
450 | cb95c2e4 | Stefan Weil | pci_get_quad(const uint8_t *config)
|
451 | fb5ce7d2 | Isaku Yamahata | { |
452 | cb95c2e4 | Stefan Weil | return le64_to_cpup((const uint64_t *)config); |
453 | fb5ce7d2 | Isaku Yamahata | } |
454 | fb5ce7d2 | Isaku Yamahata | |
455 | fb5ce7d2 | Isaku Yamahata | static inline void |
456 | deb54399 | aliguori | pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
457 | deb54399 | aliguori | { |
458 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_VENDOR_ID], val); |
459 | deb54399 | aliguori | } |
460 | deb54399 | aliguori | |
461 | deb54399 | aliguori | static inline void |
462 | deb54399 | aliguori | pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
463 | deb54399 | aliguori | { |
464 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_DEVICE_ID], val); |
465 | deb54399 | aliguori | } |
466 | deb54399 | aliguori | |
467 | 173a543b | blueswir1 | static inline void |
468 | cf602c7b | Izik Eidus | pci_config_set_revision(uint8_t *pci_config, uint8_t val) |
469 | cf602c7b | Izik Eidus | { |
470 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_REVISION_ID], val); |
471 | cf602c7b | Izik Eidus | } |
472 | cf602c7b | Izik Eidus | |
473 | cf602c7b | Izik Eidus | static inline void |
474 | 173a543b | blueswir1 | pci_config_set_class(uint8_t *pci_config, uint16_t val) |
475 | 173a543b | blueswir1 | { |
476 | 14e12559 | Michael S. Tsirkin | pci_set_word(&pci_config[PCI_CLASS_DEVICE], val); |
477 | 173a543b | blueswir1 | } |
478 | 173a543b | blueswir1 | |
479 | cf602c7b | Izik Eidus | static inline void |
480 | cf602c7b | Izik Eidus | pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val) |
481 | cf602c7b | Izik Eidus | { |
482 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_CLASS_PROG], val); |
483 | cf602c7b | Izik Eidus | } |
484 | cf602c7b | Izik Eidus | |
485 | cf602c7b | Izik Eidus | static inline void |
486 | cf602c7b | Izik Eidus | pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) |
487 | cf602c7b | Izik Eidus | { |
488 | cf602c7b | Izik Eidus | pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); |
489 | cf602c7b | Izik Eidus | } |
490 | cf602c7b | Izik Eidus | |
491 | aabcf526 | Isaku Yamahata | /*
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492 | aabcf526 | Isaku Yamahata | * helper functions to do bit mask operation on configuration space.
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493 | aabcf526 | Isaku Yamahata | * Just to set bit, use test-and-set and discard returned value.
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494 | aabcf526 | Isaku Yamahata | * Just to clear bit, use test-and-clear and discard returned value.
|
495 | aabcf526 | Isaku Yamahata | * NOTE: They aren't atomic.
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496 | aabcf526 | Isaku Yamahata | */
|
497 | aabcf526 | Isaku Yamahata | static inline uint8_t |
498 | aabcf526 | Isaku Yamahata | pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) |
499 | aabcf526 | Isaku Yamahata | { |
500 | aabcf526 | Isaku Yamahata | uint8_t val = pci_get_byte(config); |
501 | aabcf526 | Isaku Yamahata | pci_set_byte(config, val & ~mask); |
502 | aabcf526 | Isaku Yamahata | return val & mask;
|
503 | aabcf526 | Isaku Yamahata | } |
504 | aabcf526 | Isaku Yamahata | |
505 | aabcf526 | Isaku Yamahata | static inline uint8_t |
506 | aabcf526 | Isaku Yamahata | pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) |
507 | aabcf526 | Isaku Yamahata | { |
508 | aabcf526 | Isaku Yamahata | uint8_t val = pci_get_byte(config); |
509 | aabcf526 | Isaku Yamahata | pci_set_byte(config, val | mask); |
510 | aabcf526 | Isaku Yamahata | return val & mask;
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511 | aabcf526 | Isaku Yamahata | } |
512 | aabcf526 | Isaku Yamahata | |
513 | aabcf526 | Isaku Yamahata | static inline uint16_t |
514 | aabcf526 | Isaku Yamahata | pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) |
515 | aabcf526 | Isaku Yamahata | { |
516 | aabcf526 | Isaku Yamahata | uint16_t val = pci_get_word(config); |
517 | aabcf526 | Isaku Yamahata | pci_set_word(config, val & ~mask); |
518 | aabcf526 | Isaku Yamahata | return val & mask;
|
519 | aabcf526 | Isaku Yamahata | } |
520 | aabcf526 | Isaku Yamahata | |
521 | aabcf526 | Isaku Yamahata | static inline uint16_t |
522 | aabcf526 | Isaku Yamahata | pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) |
523 | aabcf526 | Isaku Yamahata | { |
524 | aabcf526 | Isaku Yamahata | uint16_t val = pci_get_word(config); |
525 | aabcf526 | Isaku Yamahata | pci_set_word(config, val | mask); |
526 | aabcf526 | Isaku Yamahata | return val & mask;
|
527 | aabcf526 | Isaku Yamahata | } |
528 | aabcf526 | Isaku Yamahata | |
529 | aabcf526 | Isaku Yamahata | static inline uint32_t |
530 | aabcf526 | Isaku Yamahata | pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) |
531 | aabcf526 | Isaku Yamahata | { |
532 | aabcf526 | Isaku Yamahata | uint32_t val = pci_get_long(config); |
533 | aabcf526 | Isaku Yamahata | pci_set_long(config, val & ~mask); |
534 | aabcf526 | Isaku Yamahata | return val & mask;
|
535 | aabcf526 | Isaku Yamahata | } |
536 | aabcf526 | Isaku Yamahata | |
537 | aabcf526 | Isaku Yamahata | static inline uint32_t |
538 | aabcf526 | Isaku Yamahata | pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) |
539 | aabcf526 | Isaku Yamahata | { |
540 | aabcf526 | Isaku Yamahata | uint32_t val = pci_get_long(config); |
541 | aabcf526 | Isaku Yamahata | pci_set_long(config, val | mask); |
542 | aabcf526 | Isaku Yamahata | return val & mask;
|
543 | aabcf526 | Isaku Yamahata | } |
544 | aabcf526 | Isaku Yamahata | |
545 | aabcf526 | Isaku Yamahata | static inline uint64_t |
546 | aabcf526 | Isaku Yamahata | pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) |
547 | aabcf526 | Isaku Yamahata | { |
548 | aabcf526 | Isaku Yamahata | uint64_t val = pci_get_quad(config); |
549 | aabcf526 | Isaku Yamahata | pci_set_quad(config, val & ~mask); |
550 | aabcf526 | Isaku Yamahata | return val & mask;
|
551 | aabcf526 | Isaku Yamahata | } |
552 | aabcf526 | Isaku Yamahata | |
553 | aabcf526 | Isaku Yamahata | static inline uint64_t |
554 | aabcf526 | Isaku Yamahata | pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) |
555 | aabcf526 | Isaku Yamahata | { |
556 | aabcf526 | Isaku Yamahata | uint64_t val = pci_get_quad(config); |
557 | aabcf526 | Isaku Yamahata | pci_set_quad(config, val | mask); |
558 | aabcf526 | Isaku Yamahata | return val & mask;
|
559 | aabcf526 | Isaku Yamahata | } |
560 | aabcf526 | Isaku Yamahata | |
561 | c9f50cea | Michael S. Tsirkin | /* Access a register specified by a mask */
|
562 | c9f50cea | Michael S. Tsirkin | static inline void |
563 | c9f50cea | Michael S. Tsirkin | pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg) |
564 | c9f50cea | Michael S. Tsirkin | { |
565 | c9f50cea | Michael S. Tsirkin | uint8_t val = pci_get_byte(config); |
566 | c9f50cea | Michael S. Tsirkin | uint8_t rval = reg << (ffs(mask) - 1);
|
567 | c9f50cea | Michael S. Tsirkin | pci_set_byte(config, (~mask & val) | (mask & rval)); |
568 | c9f50cea | Michael S. Tsirkin | } |
569 | c9f50cea | Michael S. Tsirkin | |
570 | c9f50cea | Michael S. Tsirkin | static inline uint8_t |
571 | c9f50cea | Michael S. Tsirkin | pci_get_byte_by_mask(uint8_t *config, uint8_t mask) |
572 | c9f50cea | Michael S. Tsirkin | { |
573 | c9f50cea | Michael S. Tsirkin | uint8_t val = pci_get_byte(config); |
574 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
575 | c9f50cea | Michael S. Tsirkin | } |
576 | c9f50cea | Michael S. Tsirkin | |
577 | c9f50cea | Michael S. Tsirkin | static inline void |
578 | c9f50cea | Michael S. Tsirkin | pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg) |
579 | c9f50cea | Michael S. Tsirkin | { |
580 | c9f50cea | Michael S. Tsirkin | uint16_t val = pci_get_word(config); |
581 | c9f50cea | Michael S. Tsirkin | uint16_t rval = reg << (ffs(mask) - 1);
|
582 | c9f50cea | Michael S. Tsirkin | pci_set_word(config, (~mask & val) | (mask & rval)); |
583 | c9f50cea | Michael S. Tsirkin | } |
584 | c9f50cea | Michael S. Tsirkin | |
585 | c9f50cea | Michael S. Tsirkin | static inline uint16_t |
586 | c9f50cea | Michael S. Tsirkin | pci_get_word_by_mask(uint8_t *config, uint16_t mask) |
587 | c9f50cea | Michael S. Tsirkin | { |
588 | c9f50cea | Michael S. Tsirkin | uint16_t val = pci_get_word(config); |
589 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
590 | c9f50cea | Michael S. Tsirkin | } |
591 | c9f50cea | Michael S. Tsirkin | |
592 | c9f50cea | Michael S. Tsirkin | static inline void |
593 | c9f50cea | Michael S. Tsirkin | pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg) |
594 | c9f50cea | Michael S. Tsirkin | { |
595 | c9f50cea | Michael S. Tsirkin | uint32_t val = pci_get_long(config); |
596 | c9f50cea | Michael S. Tsirkin | uint32_t rval = reg << (ffs(mask) - 1);
|
597 | c9f50cea | Michael S. Tsirkin | pci_set_long(config, (~mask & val) | (mask & rval)); |
598 | c9f50cea | Michael S. Tsirkin | } |
599 | c9f50cea | Michael S. Tsirkin | |
600 | c9f50cea | Michael S. Tsirkin | static inline uint32_t |
601 | c9f50cea | Michael S. Tsirkin | pci_get_long_by_mask(uint8_t *config, uint32_t mask) |
602 | c9f50cea | Michael S. Tsirkin | { |
603 | c9f50cea | Michael S. Tsirkin | uint32_t val = pci_get_long(config); |
604 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
605 | c9f50cea | Michael S. Tsirkin | } |
606 | c9f50cea | Michael S. Tsirkin | |
607 | c9f50cea | Michael S. Tsirkin | static inline void |
608 | c9f50cea | Michael S. Tsirkin | pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg) |
609 | c9f50cea | Michael S. Tsirkin | { |
610 | c9f50cea | Michael S. Tsirkin | uint64_t val = pci_get_quad(config); |
611 | c9f50cea | Michael S. Tsirkin | uint64_t rval = reg << (ffs(mask) - 1);
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612 | c9f50cea | Michael S. Tsirkin | pci_set_quad(config, (~mask & val) | (mask & rval)); |
613 | c9f50cea | Michael S. Tsirkin | } |
614 | c9f50cea | Michael S. Tsirkin | |
615 | c9f50cea | Michael S. Tsirkin | static inline uint64_t |
616 | c9f50cea | Michael S. Tsirkin | pci_get_quad_by_mask(uint8_t *config, uint64_t mask) |
617 | c9f50cea | Michael S. Tsirkin | { |
618 | c9f50cea | Michael S. Tsirkin | uint64_t val = pci_get_quad(config); |
619 | c9f50cea | Michael S. Tsirkin | return (val & mask) >> (ffs(mask) - 1); |
620 | c9f50cea | Michael S. Tsirkin | } |
621 | c9f50cea | Michael S. Tsirkin | |
622 | 49823868 | Isaku Yamahata | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
623 | 49823868 | Isaku Yamahata | const char *name); |
624 | 49823868 | Isaku Yamahata | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
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625 | 49823868 | Isaku Yamahata | bool multifunction,
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626 | 49823868 | Isaku Yamahata | const char *name); |
627 | 499cf102 | Markus Armbruster | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name); |
628 | 6b1b92d3 | Paul Brook | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); |
629 | 6b1b92d3 | Paul Brook | |
630 | 3c18685f | Isaku Yamahata | static inline int pci_is_express(const PCIDevice *d) |
631 | a9f49946 | Isaku Yamahata | { |
632 | a9f49946 | Isaku Yamahata | return d->cap_present & QEMU_PCI_CAP_EXPRESS;
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633 | a9f49946 | Isaku Yamahata | } |
634 | a9f49946 | Isaku Yamahata | |
635 | 3c18685f | Isaku Yamahata | static inline uint32_t pci_config_size(const PCIDevice *d) |
636 | a9f49946 | Isaku Yamahata | { |
637 | a9f49946 | Isaku Yamahata | return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
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638 | a9f49946 | Isaku Yamahata | } |
639 | a9f49946 | Isaku Yamahata | |
640 | ec174575 | David Gibson | /* DMA access functions */
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641 | d86a77f8 | David Gibson | static inline DMAContext *pci_dma_context(PCIDevice *dev) |
642 | d86a77f8 | David Gibson | { |
643 | 5fa45de5 | David Gibson | return dev->dma;
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644 | d86a77f8 | David Gibson | } |
645 | d86a77f8 | David Gibson | |
646 | ec174575 | David Gibson | static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr, |
647 | ec174575 | David Gibson | void *buf, dma_addr_t len, DMADirection dir)
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648 | ec174575 | David Gibson | { |
649 | d86a77f8 | David Gibson | dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir); |
650 | ec174575 | David Gibson | return 0; |
651 | ec174575 | David Gibson | } |
652 | ec174575 | David Gibson | |
653 | ec174575 | David Gibson | static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr, |
654 | ec174575 | David Gibson | void *buf, dma_addr_t len)
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655 | ec174575 | David Gibson | { |
656 | ec174575 | David Gibson | return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
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657 | ec174575 | David Gibson | } |
658 | ec174575 | David Gibson | |
659 | ec174575 | David Gibson | static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr, |
660 | ec174575 | David Gibson | const void *buf, dma_addr_t len) |
661 | ec174575 | David Gibson | { |
662 | ec174575 | David Gibson | return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE); |
663 | ec174575 | David Gibson | } |
664 | ec174575 | David Gibson | |
665 | ec174575 | David Gibson | #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
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666 | ec174575 | David Gibson | static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \ |
667 | ec174575 | David Gibson | dma_addr_t addr) \ |
668 | ec174575 | David Gibson | { \ |
669 | d86a77f8 | David Gibson | return ld##_l##_dma(pci_dma_context(dev), addr); \ |
670 | ec174575 | David Gibson | } \ |
671 | ec174575 | David Gibson | static inline void st##_s##_pci_dma(PCIDevice *dev, \ |
672 | d86a77f8 | David Gibson | dma_addr_t addr, uint##_bits##_t val) \ |
673 | ec174575 | David Gibson | { \ |
674 | d86a77f8 | David Gibson | st##_s##_dma(pci_dma_context(dev), addr, val); \ |
675 | ec174575 | David Gibson | } |
676 | ec174575 | David Gibson | |
677 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(ub, b, 8);
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678 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
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679 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
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680 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
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681 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
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682 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
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683 | ec174575 | David Gibson | PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
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684 | ec174575 | David Gibson | |
685 | ec174575 | David Gibson | #undef PCI_DMA_DEFINE_LDST
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686 | ec174575 | David Gibson | |
687 | ec174575 | David Gibson | static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr, |
688 | ec174575 | David Gibson | dma_addr_t *plen, DMADirection dir) |
689 | ec174575 | David Gibson | { |
690 | ec174575 | David Gibson | void *buf;
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691 | ec174575 | David Gibson | |
692 | d86a77f8 | David Gibson | buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir); |
693 | ec174575 | David Gibson | return buf;
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694 | ec174575 | David Gibson | } |
695 | ec174575 | David Gibson | |
696 | ec174575 | David Gibson | static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len, |
697 | ec174575 | David Gibson | DMADirection dir, dma_addr_t access_len) |
698 | ec174575 | David Gibson | { |
699 | d86a77f8 | David Gibson | dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len); |
700 | ec174575 | David Gibson | } |
701 | ec174575 | David Gibson | |
702 | ec174575 | David Gibson | static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev, |
703 | ec174575 | David Gibson | int alloc_hint)
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704 | ec174575 | David Gibson | { |
705 | c65bcef3 | David Gibson | qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev)); |
706 | ec174575 | David Gibson | } |
707 | ec174575 | David Gibson | |
708 | 701a8f76 | Paolo Bonzini | extern const VMStateDescription vmstate_pci_device; |
709 | 701a8f76 | Paolo Bonzini | |
710 | 701a8f76 | Paolo Bonzini | #define VMSTATE_PCI_DEVICE(_field, _state) { \
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711 | 701a8f76 | Paolo Bonzini | .name = (stringify(_field)), \ |
712 | 701a8f76 | Paolo Bonzini | .size = sizeof(PCIDevice), \
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713 | 701a8f76 | Paolo Bonzini | .vmsd = &vmstate_pci_device, \ |
714 | 701a8f76 | Paolo Bonzini | .flags = VMS_STRUCT, \ |
715 | 701a8f76 | Paolo Bonzini | .offset = vmstate_offset_value(_state, _field, PCIDevice), \ |
716 | 701a8f76 | Paolo Bonzini | } |
717 | 701a8f76 | Paolo Bonzini | |
718 | 701a8f76 | Paolo Bonzini | #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
|
719 | 701a8f76 | Paolo Bonzini | .name = (stringify(_field)), \ |
720 | 701a8f76 | Paolo Bonzini | .size = sizeof(PCIDevice), \
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721 | 701a8f76 | Paolo Bonzini | .vmsd = &vmstate_pci_device, \ |
722 | 701a8f76 | Paolo Bonzini | .flags = VMS_STRUCT|VMS_POINTER, \ |
723 | 701a8f76 | Paolo Bonzini | .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \ |
724 | 701a8f76 | Paolo Bonzini | } |
725 | 701a8f76 | Paolo Bonzini | |
726 | 87ecb68b | pbrook | #endif |