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target-arm: Implement qmp query-cpu-definitions
Libvirt uses this to introspect available CPU models.
Signed-off-by: Cole Robinson <crobinso@redhat.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Message-id: c0bdcd6c7ea6a085a6902ccaa73180fd771c8267.1378303555.git.crobinso@redhat.com...
target-arm: Avoid "1 << 31" undefined behaviour
Avoid the undefined behaviour of "1 << 31" by using 1U to makethe shift be of an unsigned value rather than shifting into thesign bit of a signed integer. For consistency, we make all theCPSR_* constants unsigned, though the only one which triggers...
aio / timers: Switch entire codebase to the new timer API
This is an autogenerated patch using scripts/switch-timer-api.
Switch the entire code base to using the new timer API.
Note this patch may introduce some line length issues.
Signed-off-by: Alex Bligh <alex@alex.org.uk>...
target-arm: Allow raw_read() and raw_write() to handle 64 bit regs
Extend the raw_read() and raw_write() helper accessors so thatthey can be used for 64 bit registers as well as 32 bit registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
target-arm: Implement the generic timer
The ARMv7 architecture specifies a 'generic timer' which is implementedvia cp15 registers. Newer kernels will prefer to use this rather thana devboard-level timer. Implement the generic timer for TCG; for KVMwe will already use the hardware's virtualized timer for this....
target-arm: Implement 'int' loglevel
The 'int' loglevel for recording interrupts and exceptionsrequires support in the target-specific code. Implementit for ARM. This improves debug logging in some situationsthat were otherwise pretty opaque, such as when we fault...
misc: Use g_assert_not_reached for code which is expected to be unreachable
The macro g_assert_not_reached is a better self documenting replacementfor assert(0) or assert(false).
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helperscpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd()....
gdbstub: Change gdb_register_coprocessor() argument to CPUState
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup
The if block detecting OMAP/StrongARM modifies the id_cp_reginfo.access fields in place. So there is no need to replicate the callto define_arm_cp_reg(). Dropped, and let the OMAP case fall through...
target-arm/helper.c: Implement MIDR aliases
Unimplemented registers in the cp15, CRn=0, opc1=0, CRm=0 space defaultto aliasing the MIDR register. Set all registers in the space to accessMIDR by default.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
target-arm/helper.c: Allow const opaques in arm CP
Allow for defining const opaque data in ARM CP register definitions bysetting .opaque = foo. If non null opaque is passed intodefine_one_arm_cp_reg_with_opaque then that opaque will takeprecedence, otherwise if null opaque is passed, the original opaque...
target-arm: avoid undefined behaviour when writing TTBCR
LPAE CPUs have more potentially valid bits in the TTBCR, and so thesimple masking out of invalid bits is no longer sufficient to obtainthe base address width field of the register, which is what we use to...
target-arm: Avoid g_hash_table_get_keys()
g_hash_table_get_keys() was only introduced in glib 2.14, and we'restill targeting a minimum version of 2.12. Rewrite the offendingcode (introduced in commit 721fae1) to use g_hash_table_foreach()to build the list of keys....
target-arm: Convert TCG to using (index,value) list for cp migration
Convert the TCG ARM target to using an (index,value) list for migratingcoprocessors. The primary benefit of the (index,value) list is forpassing state between KVM and QEMU, but it works for TCG-to-TCG...
target-arm: Add raw_readfn and raw_writefn to ARMCPRegInfo
For reading and writing register values from the kernel for KVM,we need to provide accessor functions which are guaranteed to succeedand don't impose access checks, mask out unwritable bits, etc....
target-arm: mark up cpregs for no-migrate or raw access
Mark up coprocessor register definitions to add raw accessfunctions or mark the register as non-migratable where necessary.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
cpu: Pass CPUState to cpu_interrupt()
Move it to qom/cpu.h to avoid issues with include order.
Change pc_acpi_smi_interrupt() opaque to X86CPU.
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
target-arm: Override do_interrupt for ARMv7-M profile
Enable ARMCPUInfo to specify a custom class_init functions.Introduce arm_v7m_class_init() and use it for "cortex-m3" model.
Instead of forwarding from arm_cpu_do_interrupt() to do_interrupt_v7m(),override CPUClass::do_interrupt with arm_v7m_cpu_do_interrupt()...
ARM: KVM: Add support for KVM on ARM architecture
Add basic support for KVM on ARM architecture.
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>[PMM: Minor tweaks and code cleanup, switch to ONE_REG]Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Drop CPUARMState* argument from bank_number()
Drop the CPUARMState* argument from bank_number(), since we onlyuse it for passing to cpu_abort(). Use hw_error() instead.This avoids propagating further interfaces using env pointers.
In the long term this function's callers need auditing to fix...
target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-arm: Move TCG initialization to ARMCPU initfn
Ensures that a QOM-created ARMCPU is usable.
target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer calledvia cpu.h prototype. To maintain the semantics of cpu_init(), setrealized = true explicitly in cpu_arm_init().
Move GDB coprocessor registration, CPU reset and vCPU initialization...
target-arm: Rename CPU types
In the initial conversion of CPU models to QOM types, model names weremapped 1:1 to type names. As a side effect this gained us a type "any",which is now a device.
To avoid "-device any" silliness and to pave the way for compiling...
target-arm: Detect attempt to instantiate non-CPU type in cpu_init()
Consolidate model checking into a new arm_cpu_class_by_name().
If the name matches an existing type, also check whether that type isactually (a sub-type of) TYPE_ARM_CPU.
This fixes, e.g., -cpu tmp105 asserting....
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using anegative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset()....
target-arm: Fix SWI (SVC) instruction in M profile.
When do_interrupt_v7m is called with EXCP_SWI, the PC alreadypoints to the next instruction. Don't modify it here.
Signed-off-by: Alex Rozenman <Alex_Rozenman@mentor.com>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Merge branch 'master' of git://git.qemu.org/qemu into qom-cpu
Adapt header include paths.
cpu: Introduce CPUListState struct
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it foreach target. Place it in cpu-common.h to avoid circular dependencies.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Igor Mammedov <imammedo@redhat.com>...
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
exec: move include files to include/exec/
target-arm: Implement abs_i32 inline rather than as a helper
Implement abs_i32 inline (with movcond) rather than using a helperfunction.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-arm: final conversion to AREG0 free mode
Convert code load functions and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Fix potential buffer overflow
Report from smatch:
target-arm/helper.c:651 arm946_prbs_read(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8target-arm/helper.c:661 arm946_prbs_write(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8...
target-arm: Fix typos in comments
Fix a variety of typos in comments in target-arm files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
target-arm: Implement privileged-execute-never (PXN)
Implement the privileged-execute-never (PXN) translation table bit.It is implementation-defined whether this is implemented, so we giveit its own ARM_FEATURE_ flag. LPAE requires PXN, so add also anLPAE feature flag and the implication logic, as a placeholder...
target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
Add implementations of the AMAIR0 and AMAIR1 LPAEAuxiliary Memory Attribute Indirection Registers.These are implementation defined and we choose toimplement them as RAZ/WI, matching the Cortex-A7and Cortex-A15....
target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; weonly implement these as dummy RAZ versions; provide dummies forthe 64 bit accesses as well.
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extendedto 64 bits, with a 64 bit (MRRC/MCRR) access path to read thefull width of the register. Add the state fields for the tophalf and the 64 bit access path. Actual use of the top half of...
target-arm: Use target_phys_addr_t in get_phys_addr()
In the implementation of get_phys_addr(), consistently usetarget_phys_addr_t to hold the physical address rather thanuint32_t.
target-arm: Implement long-descriptor PAR format
Implement the different format of the PAR when long descriptortranslation tables are in use. Note that we assume thatget_phys_addr() returns a long-descriptor format DFSR value onfailure if long descriptors are in use; this added subtlety tips...
target-arm: Implement TTBCR changes for LPAE
Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it
target-arm: Add support for long format translation table walks
Implement the actual table walk code for LPAE's long formattranslation tables.
target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
Fix a copy-and-paste error in the register description for TTBR1that meant it was a duplicate of TTBR0 rather than affecting thecorrect bit of CPU state.
target-arm: Fix some copy-and-paste errors in cp register names
Fix a couple of cases where cp register names were copy-and-pasted.These are harmless since we don't use the name for anything (exceptdebugging convenience) but could be confusing.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,so it can be deleted.
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.This includes only providing them on the CPUs which implementedthem, rather than the previous blunderbuss approach of makingall MCRR instructions on all CPUs act as NOPs....
target-arm: Convert final ID registers
Convert the final ID registers to the new cp15 scheme.
target-arm: Convert MPIDR
Convert the MPIDR to the new cp15 register scheme.This includes giving it its own feature bit ratherthan doing a CPUID value check.
target-arm: Convert cp15 cache ID registers
Convert the cp15 cache ID registers to the new scheme.
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Convert the cp15 crn=0 crm={1,2} features registers tothe new cp reg framework.
target-arm: Convert cp15 crn=1 registers
Convert the cp15 crn=1 registers to the new scheme.
target-arm: Convert cp15 crn=9 registers
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.
Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This isa change from previous behaviour, but a return to the behaviour of commit...
target-arm: Convert cp15 crn=6 registers
Convert the cp15 crn=6 registers to the new scheme.Note that this includes some minor tidyup: drop an unnecessaryunderdecoding of op2 on OMAPCP cores, and only implement thepre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5...
target-arm: convert cp15 crn=7 registers
Convert the cp15 crn=7 registers to the new scheme.Note that to do this we have to distinguish some registersused on the ARM9 and ARM10 from some which are ARM1176only. This is because the old code returned a value of 0...
target-arm: Convert cp15 VA-PA translation registers
Convert the cp15 VA-PA translation registers (a subset ofthe crn=7 regs) to the new scheme.
target-arm: Convert cp15 MMU TLB control
Convert cp15 MMU TLB control (crn=8) to new scheme.
target-arm: Convert cp15 crn=15 registers
Convert the cp15 crn=15 (implementation specific) registersto the new scheme.
target-arm: Convert cp15 crn=10 registers
We RAZ/WI the entire block of crn=10 registers. Note that thisactually covers not just the implementation-defined TLBlockdown registers but also a number of v7 VMSA memoryattribute registers which we would need to implement to...
target-arm: Convert cp15 crn=13 registers
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR,and the ARM946 Trace Process Identifier Register).
target-arm: Convert cp15 crn=2 registers
Convert the cp15 crn=2 registers (MMU page table control,MPU cache control) to the new scheme.
target-arm: Convert MMU fault status cp15 registers
Convert the MMU fault status and MPU access permission cp15registers to the new scheme.
target-arm: Convert cp15 c3 register
Convert the cp15 c3 register (MMU domain access controlor MPU write buffer control). NB that this is horriblyunderdecoded for modern cores (should be crn=3,crm=0,opc1=0,opc2=0) but this change preserves the existing...
target-arm: Convert generic timer cp15 regs
Convert the (dummy) generic timer cp15 implementation.
target-arm: Convert performance monitor registers
Convert the v7 performance monitor cp15 registers tothe new scheme.
target-arm: Convert TLS registers
Convert TLS registers to the new cp15 framework
target-arm: Convert WFI/barriers special cases to cp_reginfo
Convert the various WFI and barrier instruction special cases to usecp_reginfo infrastructure.
target-arm: Convert TEECR, TEEHBR to new scheme
Convert the THUMB2EE cp14 registers TEECR and TEEHBR touse arm_cp_reginfo.
target-arm: Convert debug registers to cp_reginfo
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to thecp_reginfo scheme.
target-arm: Add register_cp_regs_for_features()
Add new function register_cp_regs_for_features() as a place toregister coprocessor registers dependent on feature flags.
target-arm: Remove old cpu_arm_set_cp_io infrastructure
All the users of cpu_arm_set_cp_io have been converted, so wecan remove it and the infrastructure it used.
target-arm: initial coprocessor register framework
Initial infrastructure for data-driven registration ofcoprocessor register implementations.
We still fall back to the old-style switch statements pendingcomplete conversion of all existing registers....
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-arm: Use cpu_reset() in cpu_arm_init()
Commit 3c30dd5a68e9fee6af67cfd0d14ed7520820f36a (target-arm: Move resethandling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacingcpu_state_reset() with cpu_reset().
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-arm: Change cpu_arm_init() return type to ARMCPU
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need toobtain an ARMCPU through arm_env_get_cpu() in machine init code.This requires to adjust the inclusion site of cpu-qom.h and in turn,...
target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move thereset code over to the class reset function and have cpu_state_resetsimply do a reset on the CPU QOM object.
target-arm: Drop cpu_reset_model_id()
cpu_reset_model_id() is now empty and we can remove it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Acked-by: Andreas Färber <afaerber@suse.de>
target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() bycreating a field for the reset value in ARMCPU and setting itup in the cpu specific init functions.
target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;since these registers are only accessible on CPUs with theOMAPCP feature set there's no need to guard this reset witheither a CPUID or feature bit check....
target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.
target-arm: Move iWMMXT wCID reset to cpu_state_reset
Move the iWMMXT wCID reset to cpu_state_reset(). Sincewe use the same value for all CPUs with this feature(with the major/minor revision fields set to the QEMUspecific 'Q' value) there's no need to create an ARMCPU...
target-arm: Drop JTAG_ID documentation
None of the machines in QEMU offer a JTAG debug interface, so this infowas unused. Further, the PXA250 ID contradicts the February 2002Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.
target-arm: Move SCTLR reset value setup to per cpu init fns
Move the reset value of SCTLR to ARMCPU, initialised inthe per-cpu init functions. It can then be reset by asimple copy, and we can drop the code from cpu_reset_model_id().
target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU fieldset up by per-cpu init fns.
target-arm: Move MVFR* setup to per cpu init fns
Move the MVFR* VFP feature register values to ARMCPU,so they are set up by the implementation-specific instanceinit functions rather than in cpu_reset_model_id().
target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in theper-implementation instance init function. At reset we thenjust copy the reset value into the CPUARMState field.
target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id()to each CPU's instance init function. This requires us to movethe features field in CPUARMState so that it is not clearedon reset.
target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation.
Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,except for special value "any".
Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the...
Userspace ARM BE8 support
Add support for ARM BE8 userspace binaries.i.e. big-endian data and little-endian code.In principle LE8 mode is also possible, but AFAIK has never actuallybeen implemented/used.
System emulation doesn't have any useable big-endian board models,...
ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registerswith a test for a new feature flag ARM_FEATURE_MVFR, and sets this featurefor all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu...
target-arm: Minimalistic CPU QOM'ification
Introduce only one non-abstract type TYPE_ARM_CPU and do not touchcp15 registers to not interfere with Peter's ongoing remodelling.Embed CPUARMState as first (additional) field of ARMCPU.
Let CPUClass::reset() call cpu_state_reset() for now....
target-arm: Drop cpu_arm_close()
It's unused, so no need to QOM'ify it later.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-arm: Clear IT bits when taking exceptions in v7M
When taking an exception for an M profile core, we must clearthe IT bits. Since the IT bits are cached in env->condexec_bitswe must clear them there: writing the bits in env->uncached_cpsrhas no effect. (Reported as LP:944645.)...
target-arm: Fix typo in ARM946 cp15 c5 handling
Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling(instruction access permission bits) that meant it wouldreturn the data access permission bits by mistake.
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>...