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target-arm: Log bad system register accesses with LOG_UNIMP
Log guest attempts to access unimplemented system registers viathe LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bitinstruction sets). This is particularly useful for debuggingproblems where the guest is trying to use a system register that...
target-arm: A64: Implement floating point pairwise insns
Add support for the floating-point pairwise operationsFADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use thecode which was previously handling only integer pairwise operations,and push the integer-specific decode and handling of unallocated...
target-arm: A64: Implement remaining 3-same instructions
Implement the remaining instructions in the SIMD 3-reg-sameand scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,FACGT, FMLA and FMLS.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Implement long vector x indexed insns
Implement the 'long' operations in the vector x indexedelement category.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Implement SIMD scalar indexed instructions
Implement the SIMD scalar indexed instructions. The encodinghere is nearly identical to the vector indexed grouping, sowe combine the two.
target-arm: A64: Implement scalar three different instructions
Implement the scalar three different instruction group:it only has three instructions in it.
target-arm: A64: Implement SIMD FP compare and set insns
This adds all forms of the SIMD floating point and set instructions:
FCM(GT|GE|EQ|LE|LT)
Most of the heavy lifting is done by either the existing neon helpers orsome new helpers for the 64bit double cases. Most of the code paths are...
target-arm: A64: Implement plain vector SIMD indexed element insns
Implement all the SIMD vector x indexed element instructionsin the subcategory which are not 'long' ops.
disas: Implement disassembly output for A64
Use libvixl to implement disassembly output in debuglogs for A64, for use with both AArch64 hosts and targets.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>[PMM: * added support for target disassembly...
target-arm: A64: Implement 2-register misc compares, ABS, NEG
Implement the simple 2-register-misc operations we can sharewith the scalar-two-register-misc code. (SUQADD, USQADD, SQABS,SQNEG also fall into this category, but aren't implemented inthe scalar-2-register case yet either.)...
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
Implement the 2-reg-misc CNT, NOT and RBIT instructions.
target-arm: A64: Add narrowing 2-reg-misc instructions
Add the narrowing integer instructions in the 2-reg-misc class.
target-arm: A64: Add 2-reg-misc REV* instructions
Add the byte-reverse operations REV64, REV32 and REV16 from thetwo-reg-misc group.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
Add the SIMD FNEG and FABS instructions in the SIMD 2-reg-misc group.
target-arm: A64: Implement scalar pairwise ops
Implement the instructions in the scalar pairwise group (C3.6.8).
target-arm: A64: Implement remaining integer scalar-3-same insns
Implement the remaining integer instructions in the scalar-three-reg-samegroup: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,SQDMULH, SQRDMULH.
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
Implement the simple 64 bit integer operations from the SIMDscalar 2-register misc group (C3.6.12): the comparisons againstzero, plus ABS and NEG.
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
Add a skeleton decode for the SIMD 2-reg misc group.
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
Implement the SIMD 3-reg-same instructions SQADD, UQADD,SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,SQRSHL, UQRSHL; these are all simple calls to existingNeon helpers. We also enable SSHL, USHL, SRSHL and URSHL...
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
Implement the SIMD 3-reg-same instructions where the size == 3 caseis reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,...
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
Implement the pairwise integer operations in the 3-reg-same SIMD group:ADDP, SMAXP, SMINP, UMAXP and UMINP.
target-arm: A64: Add top level decode for SIMD 3-same group
Add top level decode for the A64 SIMD three regs same group(C3.6.16), splitting it into the pairwise, logical, float andinteger subgroups.
target-arm: A64: Add logic ops from SIMD 3 same group
Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,BIT and BIF) from the SIMD 3 register same group (C3.6.16).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: Add integer ops from SIMD 3-same group
Add some of the integer operations in the SIMD 3-same group:specifically, the comparisons, addition and subtraction.
target-arm: A64: Add simple SIMD 3-same floating point ops
Implement a simple subset of the SIMD 3-same floating pointoperations. This includes a common helper function used for bothscalar and vector ops; FABD is the only currently implementedshared op....
target-arm: A64: Add SIMD shift by immediate
This implements a subset of the AdvSIMD shift operations (namely all thenone saturating or narrowing ones). The actual shift generation codeitself is common for both the scalar and vector cases but wrapped with...
target-arm: A64: Add SIMD three-different multiply accumulate insns
Add support for the multiply-accumulate instructions from theSIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of the group into its three sub-parts...
target-arm: A64: Add SIMD three-different ABDL instructions
Implement the absolute-difference instructions in the SIMDthree-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,SABDL2, UABDL, UABDL2.
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Implement the add, sub and compare ops from the SIMD "scalar three same" group.
target-arm: Move arm_rmode_to_sf to a shared location.
This function will be needed for AArch32 ARMv8 support, so move it tohelper.c where it can be used by both targets. Also moves the code outof line, but as it is quite a large function I don't believe this...
target-arm: A64: Add SIMD modified immediate group
This patch adds support for the AdvSIMD modified immediate group(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf <agraf@suse.de>[AJB: new decode struct, minor bug fixes, optimisation]...
target-arm: A64: Add SIMD scalar copy instructions
Add support for the SIMD scalar copy instruction group (C3.6.7),which consists of the single instruction DUP (element, scalar).
target-arm: A64: Add SIMD TBL/TBLX
Add support for the SIMD TBL/TBLX instructions (group C3.6.2).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: rewritten to do more of the decode in translate-a64.c, and to do only one 64 bit pass at a time in the helper]...
target-arm: A64: Add SIMD ZIP/UZP/TRN
Add support for the SIMD ZIP/UZIP/TRN instruction group(C3.6.3).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: use new do_vec_get/set etc functions and generally update to new codebase standards; refactor to pull per-element loop outside switch]...
target-arm: A64: Add SIMD across-lanes instructions
Add support for the SIMD "across lanes" instruction group (C3.6.4).
Signed-off-by: Michael Matz <matz@suse.de>[PMM: Updated to current codebase, added fp min/max ops, added unallocated encoding checks]...
target-arm: A64: Add SIMD copy operations
This adds support for the all the AdvSIMD vector copy operations(ARM ARM 3.6.5).
target-arm: A64: Add SIMD ld/st multiple
This adds support support for the SIMD load/storemultiple category of instructions.
This also brings in a couple of helper functions for manipulatingsections of the SIMD registers:
target-arm: A64: Add SIMD ld/st single
Implement the SIMD ld/st single structure instructions.
target-arm: A64: Add decode skeleton for SIMD data processing insns
Add decode skeleton and function placeholders for all the SIMD dataprocessing instructions. Due to the complexity of this part of thetable the normal extract and switch approach gets very messy very...
target-arm: A64: Add SIMD EXT
Add support for the SIMD EXT instruction (the only one in itsgroup, C3.6.1).
target-arm: A64: Add floating-point<->fixed-point instructions
This patch adds emulation for the instruction group labeled"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU(scalar, fixed-point)....
target-arm: A64: Add floating-point<->integer conversion instructions
Add support for the AArch64 floating-point <-> integer conversioninstructions to disas_fpintconv. In the process we can rearrangeand simplify the detection of unallocated encodings a little....
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
This patch adds support for those instructions in the "Floating-pointdata-processing (1 source)" group which are simple 32-bit-to-32-bitor 64-bit-to-64-bit operations (ie everything except FCVT between...
target-arm: A64: Add support for FCVT between half, single and double
Add support for FCVT between half, single and double precision.
target-arm: A64: Add support for dumping AArch64 VFP register state
When dumping the current CPU state, we can also get a requestto dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so thatwe can properly debug code that modifies floating point registers....
target-arm: A64: Fix vector register access on bigendian hosts
The A64 128 bit vector registers are stored as a pair ofuint64_t values in the register array. This means that ifwe're directly loading or storing a value of size less than64 bits we must adjust the offset appropriately to account...
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
This patch adds emulation for the "Floating-point data-processing (2 source)" group of instructions.
Signed-off-by: Alexander Graf <agraf@suse.de>[WN: Commit message tweak, merge single and double precision patches. Rebase...
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
This patch adds emulation for the "Floating-point data-processing (3 source)" group of instructions.
Signed-off-by: Alexander Graf <agraf@suse.de>[WN: Commit message tweak, merged single and double precision patches....
target-arm: A64: Add fmov (scalar, immediate) instruction
This patch adds emulation for the fmov instruction working on scalarswith an immediate payload.
Signed-off-by: Alexander Graf <agraf@suse.de>[WN: Commit message tweak, rebase and use new infrastructure.]...
target-arm: A64: Add support for floating point compare
Add decoding support for C3.6.22 Floating-point compare.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm: A64: Add support for floating point conditional compare
This adds decoding support for C3.6.23 FP Conditional Compare.
target-arm: A64: Add support for floating point cond select
This adds decoding support for C3.6.24 FP conditional select.
target-arm: A64: add support for add/sub with carry
This patch adds support for C3.5.3 Add/subtract (with carry):instructions ADC, ADCS, SBC, SBCS.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: add support for conditional compare insns
this patch adds support for C3.5.4 - C3.5.5Conditional compare (both immediate and register)
target-arm: aarch64: add support for ld lit
Adds support for Load Register (literal), both normaland SIMD/FP forms.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Alex Bennée <alex.bennee@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: support for ld/st/cl exclusive
This implement exclusive loads/stores for aarch64 along the lines ofarm32 and ppc implementations. The exclusive load remembers the addressand loaded value. The exclusive store throws an an exception which uses...
target-arm: A64: Implement minimal set of EL0-visible sysregs
Implement an initial minimal set of EL0-visible system registers: * NZCV * FPCR * FPSR * CTR_EL0 * DCZID_EL0
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
The cpregs APIs used by the decoder (get_arm_cp_reginfo() andcp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.This is problematic for the A64 decoder, which doesn't pass the...
target-arm: A64: Implement MRS/MSR/SYS/SYSL
The AArch64 equivalent of the traditional AArch32cp15 coprocessor registers is the set of instructionsMRS/MSR/SYS/SYSL, which cover between them both truesystem registers and the "operations with side effects"...
target-arm: A64: implement FMOV
Implement FMOV, ie non-converting moves between general purposeregisters and floating point registers. This is a subtype ofthe floating point <-> integer instruction class.
target-arm: A64: add support for 3 src data proc insns
This patch adds emulation for the "Data-processing (3 source)" family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,UMADDL, UMSUBL, UMULH.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Alex Bennée <alex.bennee@linaro.org>...
target-arm: A64: implement SVC, BRK
Add decoding for the exception generating instructions, and implementSVC (syscalls) and BRK (software breakpoint).
target-arm: A64: Add decoder skeleton for FP instructions
Add a top level decoder skeleton for FP instructions.
target-arm: A64: add support for ld/st with reg offset
This adds support for the load/store forms using a register offset.
target-arm: A64: add support for ld/st with index
This adds support for the pre/post-index ld/st forms with immediateoffsets as well as the un-scaled immediate form (which are allvariations on the same 9-bit immediate instruction form).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>...
target-arm: A64: add support for add, addi, sub, subi
Implement the non-carry forms of addition and subtraction(immediate, extended register and shifted register).This includes the code to calculate NZCV if the instructioncalls for setting the flags....
target-arm: A64: add support for move wide instructions
This patch adds emulation for the mov wide instructions(MOVN, MOVZ, MOVK).
target-arm: A64: add support for ld/st pair
This patch support the basic load and store pair instructions andincludes the generic helper functions:
target-arm: A64: add support for ld/st unsigned imm
This adds support for the forms of ld/st with a 12 bitunsigned immediate offset.
target-arm: A64: add support for EXTR
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more...
target-arm: A64: add support for 2-src data processing and DIV
This patch adds support for decoding 2-src data processing insns,and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder adding the 2-src decoding level,...
target-arm: A64: add support for 2-src shift reg insns
This adds 2-src variable shift register instructions:C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, use enums for shift types]...
target-arm: A64: add support for 1-src data processing and CLZ
This patch adds support for decoding 1-src data processing insns,and the first user, C5.6.40 CLZ (count leading zeroes).
target-arm: A64: add support for 1-src RBIT insn
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch,...
target-arm: A64: add support for 1-src REV insns
This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
target-arm: A64: add support for bitfield insns
This patch implements the C3.4.2 Bitfield instructions:SBFM, BFM, UBFM.
target-arm: A64: add support for 1-src CLS insn
this patch adds support for the CLS instruction.
target-arm: A64: add support for logical (immediate) insns
This patch adds support for C3.4.4 Logical (immediate),which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, function renaming, removed a TCG temp variable]...
target-arm: A64: add support for logical (shifted register)
Add support for the instructions described in "C3.5.10 Logical(shifted register)".
We store the flags in the same locations as the 32 bit decoder.This is slightly awkward when calculating 64 bit results, but seems...
target-arm: A64: add support for ADR and ADRP
Add support for the instructions described in"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder structure]Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>...
target-arm: A64: add support for BR, BLR and RET insns
Implement BR, BLR and RET. This is all of the 'unconditionalbranch (register)' instruction category except for ERETand DPRS (which are system mode only).
Signed-off-by: Alexander Graf <agraf@suse.de>...
target-arm: A64: add support for conditional branches
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags]...
target-arm: A64: add support for 'test and branch' imm
This patch adds emulation for the test and branch insns,TBZ and TBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted for new decoder always compare with 0 remove a TCG temporary...
target-arm: A64: add support for compare and branch imm
This patch adds emulation for the compare and branch insns,CBZ and CBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)]...
target-arm: A64: add support for conditional select
This patch adds support for the instruction group "C3.5.6Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>[PMM: Improved code generated in the nomatch case as per RTH suggestions]...
target-arm: A64: provide skeleton for a64 insn decoding
Provide a skeleton for a64 instruction decoding in translate-a64.c,by dividing instructions into the classes defined by theARM Architecture Reference Manual(DDI0487A_a) section C3.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>...
target-arm: A64: expand decoding skeleton for system instructions
Decode the various kinds of system instructions: hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL sync instructions, which include CLREX, DSB, DMB, ISB msr_i, which move immediate to processor state field...
target-arm: A64: add support for B and BL insns
Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries which might be generatedif a source register is the zero-register XZR, we provide a simple...
target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
The A32/T32 gen_intermediate_code_internal() is complicated because ithas to deal with: * conditionally executed instructions * Thumb IT blocks * kernel helper page * M profile exception-exit special casing...
target-arm: Clean up handling of AArch64 PSTATE
The env->pstate field is a little odd since it doesn't strictlyspeaking represent an architectural register. However it's convenientfor QEMU to use it to hold the various PSTATE architectural bitsin the same format the architecture specifies for SPSR registers...
target-arm: Add AArch64 translation stub
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,registers look vastly different, instruction encoding is completely different,basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the...