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fpu: move public header file to include/fpu
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
exec: move include files to include/exec/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Remove t0, t1 from CPUSPARCState
These fields are no longer used.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
target-sparc: make do_unaligned_access static
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-sparc: Move sdivx and udivx out of line
The branches around the exception are maintaining an otherwiseunnecessary use of local temps for the cpu destination.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Let cpu_sparc_init() return SPARCCPU
Make include paths for cpu-qom.h consistent, so that SPARCCPU can beused in cpu.h.
Turn cpu_init macro into a static inline function returningCPUSPARCState for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: QOM'ify CPU
Embed CPUSPARCState as first member of SPARCCPU.Drop cpu_sparc_close() in favor of object_delete() and a finalizer.Let cpu_state_reset() call cpu_reset().
Make TYPE_SPARC_CPU non-abstract for now.Distinguish between "sparc-cpu" and "sparc64-cpu"....
target-sparc: Add compiler attribute to some functions which don't return
helper_raise_exception does not return, nor does do_unaligned_access.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 wrappers for memory access helpers
Adjust generation of load and store templates so that the functionstake a parameter for CPUState instead of relying on global env.
Remove wrappers. Move remaining memory helpers to ldst_helper.c.
Sparc: avoid AREG0 for memory access helpers
Make memory access helpers take a parameter for CPUState insteadof relying on global env. Introduce wrappers for load and store ops.
sparc64: implement PCI and ISA irqs
Generate correct trap for external interrupts. Map PCI and ISA IRQs toRIC/UltraSPARC-IIi interrupt vectors.
sparc: reset CPU state on reset
Not strictly accurate for Sparc64 but avoid confusing Valgrind.
Reported-by: Michael S. Tsirkin <mst@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-sparc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc] sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
target-sparc: Typedef struct CPUSPARCState early
Will be needed for qemu_irq_ack callback.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
target-sparc: Change fpr representation to doubles.
This allows a more efficient representation for 64-bit hosts.It should be about the same for 32-bit hosts, as we can stillaccess the individual pieces of the double.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
Sparc: split MMU helpers
Move MMU helpers to mmu_helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameterfor CPUState instead of relying on global env. Move the functionsto int{32,64}_helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
Sparc: split CWP and PSTATE op helpers
Move CWP and PSTATE op helpers to win_helper.c.
Sparc: split helper.c
Move CPU init to cpu_init.c and interrupt handling to int32_helper.cfor Sparc32 and int64_helper.c for Sparc64.
Gdbstub: Fix back-trace on SPARC32
Gdb expects all registers windows to be flushed in ram, which is not the casein Qemu. Therefore the back-trace generation doesn't work. This patch adds afunction to handle reads (and only read) in stack frames as if windows were...
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
SPARC64: implement addtional MMU faults related to nonfaulting load
This patch implements MMU faults caused by TTE.NFO and TTE.E:- access other than nonfaulting load to a page marked NFO should raise data_access_exception- nonfaulting load to a page marked with E bit should raise...
SPARC64: split cpu_get_phys_page_debug() from cpu_get_phys_page_nofault()
This patch makes cpu_get_phys_page_debug() independent fromcpu_get_phys_page_nofault() in advance of implementing nonfaulting load.This also modifies cpu_get_phys_page_nofault() to be compiled only on...
SPARC64: SFSR cleanup and fix
Add macros for SFSR fields and use macros instead of magic numbers.Also fix the update of the register fields on MMU faults.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: TTE bits cleanup
Add macros for TTE bits and modify to use macros instead ofmagic numbers.
Fix unassigned memory access handling
cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memoryaccess handling. Fix them by always passing CPUState to the handlers.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: fix FPU and AM enable checks for translation
Translation used incorrectly CPUState fields directly to checkfor FPU enable state and 32 bit address masking on Sparc64.
Fix by using TB flags instead.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
sparc: move do_interrupt to helper.c
do_interrupt() was mixing CPUState pointer passed from callerand global env (AREG0).
Fix by moving the function to helper.c. Introduce a helper for callingchange_pstate() safely from outside of execution context.
Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, saveand load all MXCC registers.
SPARC: Fix Leon3 cache control
The "leon3_cache_control_int" (op_helper.c) function is called within leon3.cwhich leads to segfault error with the global "env".
Now cache control is a CPU feature and everything is handled in op_helper.c.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>...
SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (moreinformation on http://www.gaisler.com).
Leon3 is made of multiple components available in the GrLib VHDL library.Three devices are implemented: uart, timers and IRQ manager....
SPARC: Add asr17 register support
This register is activated by CPU_FEATURE_ASR17 in the feature field.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: implement monitor command 'info tlb'
Use existing dump_mmu() to implement monitor command 'info tlb'.
target-sparc: Use fprintf_function (format checking)
This change was missing in commit9a78eead0c74333a394c0f7bbfc4423ac746fcd5.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: remove unused functions cpu_lock(), cpu_unlock()
remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
move cpu_pc_from_tb to target-*/exec.h
sparc64: fix mmu context at trap levels above zero
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero- cpu_get_tb_cpu_state: store trap level and primary context in flags this allows to restart code translation when address translation is changed...
sparc64: fix pstate privilege bits
- refactor code to handle hpstate only if available for current cpu- conditionally set hypervisor bit in hpstate register- reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well...
sparc64: fix TT_WOTHER value
- fix off by one error in spill trap number bit for other window (must be bit 5)- fixes invalid instruction issue with HelenOS
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc: Fix lazy flag calculation on interrupts, refactor
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlierflags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actualfunctions to op_helper.c.
Thanks to Igor Kovalenko for reporting....
sparc64: handle asi referencing nucleus and secondary MMU contexts
- increase max supported MMU modes to 6- handle nucleus context asi- handle secondary context asi- handle non-faulting loads from secondary context
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>...
sparc64: implement global translation table entries v1
- match global tte against any context- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb- should fix gcc warning about uninitialized context variable
target-sparc: Fix TARGET_{PHYS,VIRT}_ADDR_SPACE_BITS.
The 32 and 64-bit definitions were swapped in the ifdef.
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
sparc64: reimplement tick timers v4
sparc64 timer has tick counter which can be set and read,and tick compare value used as deadline to fire timer interrupt.The timer is not used as periodic timer, instead deadlineis set each time new timer interrupt is needed....
sparc64: correct write extra bits to cwp
- correctly fit to cwp if provided window number is out of range
sparc64: interrupt trap handling
cpu_check_irqs- handle SOFTINT register TICK and STICK timer bits- only check interrupt levels greater than PIL value- handle preemption by higher level traps
cpu_exec- handle CPU_INTERRUPT_HARD only if interrupts are enabled...
sparc64: move cpu_interrupts_enabled to cpu.h
- to be used by cpu_check_irqs
sparc64: add macros to deal with softint and timer interrupt
Sparc64: handle MMU global bit and nucleus context
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
sparc32 remove an unnecessary cpu irq set
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc64: replace tsptr with helper routine
tl and tsptr of members sparc64 cpu state must be changedsimultaneously to keep trap state window in sync with currenttrap level. Currently translation of store to tl does not changetsptr, which leads to corrupt trap state on corresponding...
sparc64 really implement itlb/dtlb automatic replacement writes
- implement "used" bit in tlb translation entry- mark tlb entry used if qemu code/data translation succeeds- fold i/d mmu replacement writes code into replace_tlb_1bit_lru whichadds 1bit lru replacement algorithm; previously code tried to replace...
sparc64 name mmu registers and general cleanup
- add names to mmu registers, this helps understanding the code whichuses/modifies them.- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries- extract demap_tlb routine (code duplication)...
sparc64: trap handling corrections
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: Good trap handling is required to process interrupts. This patch fixes the following:...
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
Good trap handling is required to process interrupts. This patch fixes the following:...
Hardware convenience library
The only target dependency for most hardware is sizeof(target_phys_addr_t).Build these files into a convenience library, and use that instead ofbuilding for every target.
Remove and poison various target specific macros to avoid bogus target...
Use dynamical computation for condition codes
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
Add SuperSPARC MMU breakpoint registers (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6125 c046a42c-6fe2-441c-8c8c-71466251a162
Better SuperSPARC emulation (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6123 c046a42c-6fe2-441c-8c8c-71466251a162
Implement tick interrupt disable bits
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6122 c046a42c-6fe2-441c-8c8c-71466251a162
Refactor translation block CPU state handling (Jan Kiszka)
This patch refactors the way the CPU state is handled that is associatedwith a TB. The basic motivation is to move more arch specific code outof generic files. Specifically the long #ifdef clutter in tb_find_fast()...
Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)
as macros should be avoided when possible.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
Show size for unassigned accesses (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5436 c046a42c-6fe2-441c-8c8c-71466251a162
Rearrange tick functions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5408 c046a42c-6fe2-441c-8c8c-71466251a162
Fix missing prototype warnings by moving declarations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5407 c046a42c-6fe2-441c-8c8c-71466251a162
Add software and timer interrupt support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
Move signal handler prototype back to cpu.h
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5276 c046a42c-6fe2-441c-8c8c-71466251a162
Convert rest of ops using float32 to TCG, remove FT0 and FT1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
Silence gcc warning about constant overflow
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5175 c046a42c-6fe2-441c-8c8c-71466251a162
Fix FCC handling for Sparc64 target, initial patch by Vince Weaver
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5110 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 boot on i386 host: - move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions...
Use initial CPU definition structure for some CPU fields instead of copyingthem around, based on patch by Luis Pureza.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
Make MAXTL dynamic, bounds check tl when indexing
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc32: save/load all MMU registers, Sparc64: add CPU save/load
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4938 c046a42c-6fe2-441c-8c8c-71466251a162
Use MMU globals for some MMU traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4918 c046a42c-6fe2-441c-8c8c-71466251a162
Make UA200x features selectable, add MMU types
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4911 c046a42c-6fe2-441c-8c8c-71466251a162
Fix MMU miss traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4880 c046a42c-6fe2-441c-8c8c-71466251a162
Move interrupt_request and user_mode_only to common cpu state.Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU save/load registration to common code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compiler warning (Jan Kiszka)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4781 c046a42c-6fe2-441c-8c8c-71466251a162
Allow NWINDOWS selection (CPU feature with model specific defaults)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4690 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162