target-sh4: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-sh4: ignore ocbp and ocbwb instructions
ocbp and ocbwb controls the writeback of a cache line to memory. Theyare supposed to do nothing in case of a cache miss. Given QEMU onlypartially emulate caches, it is safe to ignore these instructions.
This fixes a kernel oops when trying to access an rtl8139 NIC with...
target-sh4: Fix operands for fipr, ftrv instructions
Coverity complained about right shifts of opcode (16, 18) which werelarger than the size of opcode (16 bit).
Using the correct shift values fixes this.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Alexander Graf <agraf@suse.de>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Blue Swirl <blauwirbel@gmail.com>...
sh_intc: convert interrupt controller to memory API
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>Signed-off-by: Avi Kivity <avi@redhat.com>
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
target-sh4: get rid of CPU_{Float,Double}U
SH4 is always using softfloat, so it's possible to have helpers directlytaking float32 or float64 value. This allow to get rid of conversionsthrough CPU_{Float,Double}U.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sh4: move intr_at_halt out of cpu_halted()
All targets except SH4 have the same cpu_halted() routine, and it hasonly one caller. It is therefore a good candidate for inlining.
The difference is the handling of the intr_at_halt, which is necessary...
target-sh4: fix negc
sh4: implement missing mmaped TLB write functions
sh4: implement missing mmaped TLB read functions
target-sh4: update PTEH upon MMU exception
Update the PTEH register to contain the VPN at which an MMUexception occured as specified by the SH4 reference.
Signed-off-by: Alexandre Courbot <gnurou@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: fix index of address read error exception
Exception index of address read error should be 0x0e0.
target-sh4: fix TLB invalidation code
In cpu_sh4_invalidate_tlb, the UTLB was invalidated twice and theITLB left unchaged, probably because of some unfortunate copy/paste.
target-sh4: use rotl/rotr when possible
target-sh4: implement negc using TCG
Using setcond it's now possible to generate a relatively short negcinstruction in TCG.
target-sh4: correct use of ! and &
Fix wrong usage of ! and & in MMU related functions. Thanks to BlueSwirl for reporting the issue.
Reported-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-sh4: define FPSCR constants
Define FPSCR constants for all field and use them instead of hardcodedvalues.
target-sh4: implement flush-to-zero
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers aszero. Enable the corresponding softfloat option when this bit is set.
target-sh4: implement FPU exceptions
FPU exception support where not implemented on SH4. Implement them byclearing the softfloat exceptions flags before an FP instruction (theSH4 FPU also clear them before an instruction), and calling a functionto update the FPSCR register after an FP instruction. This function...
target-sh4: add fipr instruction
Add the fipr FVm,FVn instruction, which computes the inner products ofa 4-dimensional single precision floating-point vector.
target-sh4: add ftrv instruction
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-columnmatrix XMTRX by the 4-dimensional vector FVn.
target-sh4: optimize exceptions
As exception is not the normal path, don't bother saving PC, beforeraising one, instead rely on code retranslation to get the CPU state.
target-sh4: fix reset on r2d
target-sh4: simplify comparisons after a 'and' op
When a TCG variable is anded with a value and the compared with the samevalue, we can simply invert the comparison and compare it with 0. Thegenerated code is smaller.
target-sh4: log instructions start in TCG code
target-sh4: use setcond when possible
target-sh4: use default-NaN mode
SH4 FPU doesn't propagate NaN, and instead always regenerate new ones.Enable the default-NaN mode by default.
target-sh4: fix fpu disabled/illegal exception
Illegal instructions in a slot delay should generate a slot illegalinstruction exception instead of an illegal instruction exception.
The current PC should be saved before generating such an exception,but should not be corrected if in a delay slot, given it's already...
target-sh4: improve TLB
SH4 is using 16-bit instructions which means most of the constants areloaded through a constant pool at the end of the subroutine. The samememory page is therefore accessed in exec and read mode.
With the current implementation, a QEMU TLB entry is set to read or...
target-sh4: implement writes to mmaped ITLB
Some Linux kernels seems to implement ITLB/UTLB flushing through bywriting all TLB entries through the memory mapped interface insteadof writing one to MMUCR.TI.
Implement memory mapped ITLB write interface so that such kernels can...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-sh4: Add support for ldc & stc with sgr
Add support for the following missing priviledged intructions:
For SH4:- stc sgr, Rn- stc.l sgr, @-Rn
For SH4A:- ldc Rm, sgr- ldc.l @Rm+, sgr
target-sh4: Split the LDST macro into 2 sub-macros
The LDST macro is used to generate ldc and stc instructions that work with aspecific register. However, the SGR register only supports stc up to SH4A,which supports both stc and ldc. This patch creates two sub-macros named LD...
remove exec-all.h inclusion from cpu.h
move cpu_pc_from_tb to target-*/exec.h
target-sh4: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Replace assert(0) with abort() or cpu_abort()
When building with -DNDEBUG, assert(0) will not stop executionso it must not be used for abnormal termination.
Use cpu_abort() when in CPU context, abort() otherwise.
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
Fix incorrect exception_index use
env->exception_index should be cleared with -1, not 0.
See also 821b19fe923ac49a24cdb4af902584fdd019cee6.
Spotted by Igor Kovalenko.
target-sh4: MMU: separate execute and read/write permissions
On SH4, the ITLB and UTLB configurations are memory mapped, so loadingITLB entries from UTLB has to be simulated correctly. For that the QEMUTLB has to be handle the execute (ITLB) and read/write permissions...
target-sh4: MMU: fix mem_idx computation
The mem_idx is wrongly computed. As written in target-sh4/cpu.h, mode 0corresponds to kernel mode (SR_MD = 1), while mode 1 corresponds to usermode (SR_MD = 0).
target-sh4: MMU: simplify call to tlb_set_page()
tlb_set_page() doesn't need addresses with offset, but simply thepage aligned addresses.
target-sh4: MMU: fix ITLB priviledge check
There is an ITLB access violation if SR_MD=0 (user mode) whilethe high bit of the protection key is 0 (priviledge mode).
target-sh4: MMU: optimize UTLB accesses
With the current code, the QEMU TLB is setup to match the read/writemode of the MMU fault. This means when read access is done, the pageis setup in read-only mode. When the page is later accessed in writemode, an MMU fault happened, and the page is switch in write-only...
target-sh4: MMU: reduce the size of a TLB entry
Reduce the size of the TLB entry from 32 to 16 bytes, reorganisingmembers and using a bit field.
target-sh4: MMU: remove dead code
target-sh4: MMU: fix store queue addresses
The store queues are located from 0xe0000000 to 0xe3ffffff.
sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should beflushed.
target-sh4: minor optimisations
kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Fix Sparse warnings about using plain integer as NULL pointer
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with afew minor variations. This patch sets up appropriate defaults for ageneric handle_cpu_signal and provides overrides for particular targets...
Update to a hopefully more future proof FSF address
Convert machine registration to use module init functions
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
qemu: per-arch cpu_has_work (Marcelo Tosatti)
Blue Swirl: fix Sparc32 breakage
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
SH: Fix linux-user _is_cached typo.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6970 c046a42c-6fe2-441c-8c8c-71466251a162
SH: Add cpu_sh4_is_cached for linux-user.
The entire U0 area is assumed to be cacheable.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6969 c046a42c-6fe2-441c-8c8c-71466251a162
SH: Improve movca.l/ocbi emulation.
Author: Vladimir Prus <vladimir@codesourcery.com>
Fix movcal.l/ocbi emulation.
The _exit syscall is used for both thread termination in NPTL applications,and process termination in legacy applications. Try to guess which we wantbased on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>...
SH4: Fixed last UTLB unused and URB/URC management
Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6675 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Fixed last UTLB unused
Version 2 of the patch.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6672 c046a42c-6fe2-441c-8c8c-71466251a162
With my previous patch (the one monitoring tlb), I found that the lastTLB entry was never use. Here a little fix.
Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
clean build: Fix remaining sh4 warnings
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6668 c046a42c-6fe2-441c-8c8c-71466251a162
SH: Implement MOVCO.L and MOVLI.L
(Vladimir Prus)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6666 c046a42c-6fe2-441c-8c8c-71466251a162
SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 and fix BCR2 support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
sh4: Add FMAC instruction support
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: make the initial value of SR easier to read
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6016 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: don't disable FPU instructions in user mode
Based on a patch from Lionel Landwerlin.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6015 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: disable debug code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6014 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4: add prefi, icbi, synco
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162