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gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-xtensa: Use mul*2 for mul*hi
Cc: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: Use add2/sub2 for mac
target-xtensa: fix search_pc for the last TB opcode
Zero out tcg_ctx.gen_opc_instr_start for instructions representing thelast guest opcode in the TB.
Cc: qemu-stable@nongnu.orgSigned-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memorytype. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and thecorresponding TLB management instructions are not available. Instead,functionality similar to the Region Protection Option is availablethrough the cache attribute register. See ISA, A.2.14 for details....
target-xtensa: restrict available SRs by enabled options
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,xsr) are associated with their corresponding SR and raise illegal opcodeexception in case the register is not configured for the core....
target-xtensa: better control rsr/wsr/xsr access to SRs
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagalopcode exception on illegal access to these SRs.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: implement MISC SR
The Miscellaneous Special Registers Option provides zero to four scratchregisters within the processor readable and writable by RSR, WSR, andXSR. These registers are privileged. They may be useful for someapplication-specific exception and interrupt processing tasks in the...
target-xtensa: use movcond where possible
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAXopcodes.
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
target-xtensa: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Andreas Färber <afaerber@suse.de>
target-xtensa: de-optimize EXTUI
Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shiftare optimized in tcg/tcg-op.h there is no need to do it intarget-xtensa/translate.c.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement coprocessor context option
In case Coprocessor Context option is enabled CPENABLE SR bits controlwhether access to coprocessors is allowed or would rise one ofCoprocessorXDisabled exceptions.
See ISA, 4.4.5 for more details.
FP is coprocessor 0....
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status userregisters (fcr, fsr).
See ISA, 4.3.10 for more details.
target-xtensa: implement LSCX and LSCI groups
These are load/store instructions for FP registers with immediate orregister index and optional base post-update.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes.See ISA, 4.3.10 for more details.
Note that ISA description for utrunc.s is currently incorrect and willbe fixed in future revisions.
target-xtensa: fix extui shift amount
extui opcode only uses lowermost op1 bit for sa4.
Reported-by: malc <av1474@comtv.ru>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Cc: qemu-stable <qemu-stable@nongnu.org>Signed-off-by: malc <av1474@comtv.ru>
target-xtensa: don't emit extra tcg_gen_goto_tb
Unconditional gen_check_loop_end at the end of disas_xtensa_insncan emit tcg_gen_goto_tb with slot id already used in the TB (e.g. whenTB ends at LEND with a branch).
target-xtensa: fix big-endian BBS/BBC implementation
Quote from ISA, 2.1:
For most Xtensa instructions, bit numbering is irrelevant; only the BBCand BBS instructions assign bit numbers to values on which the processoroperates. The BBC/BBS instructions use big-endian bit ordering (0 is the...
target-xtensa: switch to AREG0-free mode
Add env parameter to every helper function that needs it, update'configure' script.
target-xtensa: fix CCOUNT for conditional branches
Taken conditional branches fail to update CCOUNT register becauseaccumulated ccount_delta is reset during translation of non-takenbranch. To fix it only update CCOUNT once per conditional branchinstruction translation....
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Translation of LOOP instructions used to call LEND SR write handler toupdate LEND and invalidate relevant TBs. Now that LEND SR write handlerends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple...
target-xtensa: fix tb invalidation for IBREAK and LOOP
Instruction breakpoint/zero overhead loop handling code is built intoTBs pointed to by IBREAKA/LEND SRs. When these or related SRs getchanged TBs at virtual addresses corresponding to their old and their...
target-xtensa: Move helpers.h to helper.h
Provides a file naming scheme consistent with other targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
target-xtensa: add DBREAK data breakpoints
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debugwatchpoints.
This implementation is not fully compliant to ISA: when a breakpoint isset to an unmapped/inaccessible memory address it generates TLB/memory...
target-xtensa: add ICOUNT SR and debug exception
ICOUNT SR gets incremented on every instruction completion provided thatCINTLEVEL at the beginning of the instruction execution is lower thanICOUNTLEVEL.
When ICOUNT would increment to 0 a debug exception is raised if...
target-xtensa: add DEBUGCAUSE SR and configuration
DEBUGCAUSE SR holds information about the most recent debug exception.See ISA, 4.7.7 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK andBREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
target-xtensa: fetch 3rd opcode byte only when needed
According to ISA, 3.5.4, third opcode byte should not be fetched for2-byte instructions.
target-xtensa: raise an exception for invalid and reserved opcodes
This includes opcodes from disabled features and those marked reserved in the ISA.Also end TB on opcodes that definitely generate an exception: illegalinstructions, syscall and privileged instructions....
target-xtensa: mask out undefined bits of WINDOWSTART SR
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SRmust be zero.
target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP;- add an option for MULSH/MULUH;- put S32C1I under conditional store option.
target-xtensa: implement MAC16 option
See ISA, 4.3.7 for the details.
- add ACC and MR special registers;- implement MAC16 and all inner MAC* opcode groups.
target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values thatcorrespond to default VECBASE value.
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
target-xtensa: implement boolean option
See ISA, 4.3.9
target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields inCPUEnv. Only current window is accessible to TCG. On operations thatchange window base helpers copy current window to and from physical...
target-xtensa: implement loop option
See ISA, 4.3.2 for details.
Operations that change LEND SR value invalidate TBs at the old and atthe new LEND. LEND value at TB compilation time is considered constantand loop instruction is generated based on this value....
target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
target-xtensa: implement unaligned exception option
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generatedin case this option is not enabled.
target-xtensa: implement SIMCALL
Tensilica iss provides support for applications running in freestandingenvironment through SIMCALL command. It is used by Tensilica libc toaccess argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses....
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: implement accurate window check
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used registerwatermark" beyond its current level. Used register watermark is reset oninstructions that change WINDOW_BASE/WINDOW_START SRs....
target-xtensa: implement CPENABLE and PRID SRs
target-xtensa: implement RST3 group
- access to Special Registers (wsr, rsr);- access to User Registers (wur, rur);- misc. operations option (value clamp, sign extension, min, max);- conditional moves.
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA;- RST1: shifts, 16-bit multiplication.
target-xtensa: implement LSAI group
- base + offset load/store operations for 1/2/4 byte values;- cache operations (not implemented);- multiprocessor synchronization operations.
target-xtensa: mark reserved and TBD opcodes
Reserved opcodes must generate illegal instruction exception. Usuallythey signal emulation quality problems.Not implemented opcodes are good to see.
target-xtensa: implement SYNC group
All operations in this group are no-ops, because there are no delayedside effects.
target-xtensa: implement CACHE group
All operations in this group are no-ops, because cache ought to betransparent to applications. However cache may be abused, then we'llneed to actually implement these opcodes.
target-xtensa: add PS register and access control
target-xtensa: implement exceptions
- mark privileged opcodes with ring check;- make debug exception on exception handler entry.
target-xtensa: implement RST2 group (32 bit mul/div/rem)
target-xtensa: implement conditional jumps
- BZ (comparison to zero);- BI0 (comparison to signed immediate);- BI1 (comparison to unsigned immediate);- B (two registers comparison, bit sets comparison);- BEQZ.N/BNEZ.N (narrow comparison to zero).
target-xtensa: implement JX/RET0/CALLX
Group SNM0 (indirect jumps and calls).
target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processorby the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in somecases of options that Tensilica provides. See ISA, 5.4 for details....
target-xtensa: add target stubs
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
target-xtensa: implement narrow instructions
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
target-xtensa: implement RT0 group
NEG and ABS are the only members of RT0 group.