MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of codethat figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1Xnot being set where applicable that causes floating-point MADD family...
target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs. So theirbehavior is well defined when RD equals BASE. The MIPS ArchitectureVerification Programs (AVPs) check that they work as expected. This...
target-mips: add privilege level check to several Cop0 instructions
The MIPS Architecture Verification Programs (AVPs) check privilegedinstructions for the required privilege level. These changes are neededto pass the AVP suite.
Signed-off-by: Eric Johnson <ericj@mips.com>...
mips-linux-user: Always support rdhwr.
The kernel will emulate this instruction if it's not supportednatively. This insn is used for TLS, among other things, andso is required by modern glibc.
Signed-off-by: Richard Henderson <rth@twiddle.net>Cc: Riku Voipio <riku.voipio@iki.fi>...
target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix order of CVT.PS.S operands
The FS input to CVT.PS.S is the high half and FT is the low half.tcg_gen_concat_i32_i64 takes the low half first, so the operandswere in the wrong order.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix operands of RECIP2.S and RECIP2.PS
Read the second input operand of RECIP2.S and RECIP2.PS from FT ratherthan FD. RECIP2.D is already correct.
target-mips: Fix some helper functions (VR54xx multiplication)
Commits b5dc7732e1cc2fb549e48b7b5d664f2c79628e2e andbe24bb4f3007c3e07cbf1934f7e781493d876ab7 optimized the codeand removed the correct setting of t0. Fix this.
gcc-4.7 detected this bug because parameter arg1 was unused...
target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required*MIPS32r2 RDHWR hardware registers should be accessible (theLinux kernel enables access to these same registers). Notethat these registers are still enabled when the MIPS ISA is...
MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps onfloating-point MADD group instructions with SIGILL, at least whileemulating MIPS32r2 processors. These instructions use the COP1X majoropcode and include ones like:...
build: move other target-*/ objects to nested Makefile.objs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-mips: Use cpu_reset() in cpu_mips_init()
Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ifyCPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping theintroduction of subclasses for 1.1, due to mips_def_t the reset code...
target-mips: Use cpu_reset() in do_interrupt()
Signed-off-by: Andreas Färber <afaerber@suse.de>
target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSStatefor backwards compatibility.
mips: Fix BC1ANY24F instructions
There's some dodgy application of De Morgan's law in the emulationof the MIPS BC1ANY24F instructions: they end up branching onlyif all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests....
target-mips: Remove commented-out function declaration
There is no function cpu_mips_get_clock(), so drop it.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Stefan Weil <sw@weilnetz.de>
target-mips: Remove unused inline function
Function set_HILO is not needed anywhere.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu
target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-mips: Start QOM'ifying CPU init
Move code not dependent on mips_def_t from cpu_mips_init() into aQOM initfn, as a start.
target-mips: Move definition of uint_fast{8, 16}_t to osdep.h
osdep.h is included via qemu-common.h.
Prepares for use of [u]int_fast*_t types in softfloat code.
Signed-off-by: Andreas Färber <afaerber@suse.de>Cc: Ben Taylor <bentaylor.solx86@gmail.com>...
target-mips: Fix type cast for w64 (uintptr_t)
This changes nothing for other hosts.
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace Qemu by QEMU in internal documentation
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: Add compiler attribute to some functions which don't return
helper_raise_exception_err does not return, nor do helper_raise_exceptionand do_unaligned_access.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-mips: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
Spelling fixes in comments (it's -> its)
Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
target-mips: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
Fix spelling in comments, documentation and messages
accidently->accidentallyannother->anotherchoosen->chosenconsideres->considersdecriptor->descriptordevelopement->developmentparamter->parameterpreceed->precedepreceeding->precedingpriviledge->privilege...
fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Alexander Graf <agraf@suse.de>Cc: Aurelien Jarno <aurelien@aurel32.net>Cc: Blue Swirl <blauwirbel@gmail.com>...
softmmu_header: pass CPUState to tlb_fill
Pass CPUState pointer to tlb_fill() instead of architecture localcpu_single_env hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
mips: Default to using one VPE and one TC.
Boards can override the setup if needed.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs andTCs start in sleep.
mips: Add MT halting and waking of VPEs
+ some partial support for TC's.
mips: Support the MT TCStatus IXMT irq disable flag
mips: Handle TC indexing of other VPEs
Introduce mips_cpu_map_tc() to map a global TC index into a VPE nrand local tc index.
mips: Synchronize CP0 TCSTatus, Status and EntryHi
These registers share some of their fields. Writes to these fieldsshould be visible through the corresponding mirror fields.
mips: Hook in more reg accesses via mttr/mftr
mips: Correct IntCtl write mask for VInt
mips: Correct VInt vector generation
1. The pending need to pass the Status IM gating.2. The priority is from seven (highest prio) down to zero. QEMU was doing the opposite.
mips: Enable VInt interrupt mode for the 34Kf
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h totarget-*/op_helper.c. Move also various other stuff only used inop_helper.c there.
Define global env in dyngen-exec.h.
For i386, move wrappers for segment and FPU helpers from user-exec.c...
Fix unassigned memory access handling
cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memoryaccess handling. Fix them by always passing CPUState to the handlers.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This isneeded by later patches.
exec.h: fix coding style and change cpu_has_work to return bool
Before the next patch, fix coding style of the areas affected.
Change the type of the return value from cpu_has_work() andqemu_cpu_has_work() to bool.
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
target-mips: Fix warning caused by unused local variable
Fix compilation with gcc-4.6, based on a patch from StefanWeil <weil@mail.berlios.de>.
Merge remote-tracking branch 'stefanha/trivial-patches' into staging
Conflicts: cpu-all.h
target-mips: Do not check CPU_INTERRUPT_TIMER.
This bit is never set, therefore we should not read it either.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix typos in comments (interupt -> interrupt)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix typo in code and comments
Replace writeable -> writable
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
target-mips: simplify FP comparisons
As the softfloat comparison functions already test for NaN, there is noneed to always call the float*_unordered*() functions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: don't hardcode softfloat exception bits
target-mips: fix c.ps.* instructions
Contrary to cabs.ps.* instructions, c.ps.* should not compare the absolutevalue of the operand, but directly the operands.
target-mips: clear softfpu exception state for comparison instructions
MIPS FPU instructions should start with a clean softfpu status. Thisis done for the most instructions, but not for comparison ones.
target-mips: use new float*_unordered*() functions
Use the new float*_unordered*() functions from softfloat instead ofredefining a private version.
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
Fix trivial "endianness bugs"
Replace endianess -> endianness.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
[PATCH] [MIPS] Clear softfpu exception state for round, trunc, ceil and floor
MIPS FPU instructions should start with a clean softfpu status. Thisis done for the arithmetic operations and cvt instructions, but notfor round, trunc, ceil and floor.
Signed-off-by: Chris Dearman <chris@mips.com>...
target-mips: fix save_cpu_state() calls
The rule is:- don't save PC if the exception is only triggered by softmmu.- save PC if the exception can be triggered by an helper.
Fix a 64-bit kernel crash when loading modules.
mips: Break TBs after mfc0_count
Break the TB after reading the count register. This makes itpossible to take timer interrupts immediately after a read ofa possibly expired timer.
softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,because they return true only for quiet NaNs, not for all NaNs.Rename them to float*_is_quiet_nan() to more accurately reflect...
target-mips: fix host CPU consumption when guest is idle
When the CPU is in wait state, do not wake-up if an interrupt can't betaken. This avoid host CPU running at 100% if a device (e.g. timer) hasan interrupt line left enabled.
Also factorize code to check if interrupts are enabled in...
target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:
int x; ... /* no initialization of x */ x = f (x);
which confused later bits of TCG rather badly, leading to crashes.
Fix the helpers to only return results (those instructions have no...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
mips: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:/src/qemu/target-mips/translate.c: In function 'gen_ld':/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]...
MIPS: fix yield handling
The parameter for yield should be handled as a signed integerfor the comparisons to have any effect.
This also avoids a gcc warning with -Wtype-limits.
mips: Add support for VInt and VEIC irq modes
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Remove unused constant
Remove unused constant MIPS_FCR0
mips: more fixes to the MIPS interrupt glue logic
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of theinterrupt logic to cpu-exec.c. Remove the remaining useless codeand fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU shouldsee the hw interrupt line as active. The CPU may or may not take theinterrupt based on internal state (global irq mask etc) but the glue...
target-mips: fix xtlb exception for loongson
Loongson 2E and 2F use the same entry for xtlb and tlb exception, atoffset 0x000.
target-mips: add loongson 2E & 2F integer instructions
This patch adds support for loongson 2E & 2F instructions. They are thesame instructions, but differ by the opcode encoding.
remove exec-all.h inclusion from cpu.h
move cpu_pc_from_tb to target-*/exec.h
remove unused stuff from */exec.h
target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.Emulate it as a NOP.
target-mips: split load and store
target-mips: fix DINSU instruction
target-mips: enable movn/movz on loongson 2E & 2F
MIPS: Initial support of fulong mini pc (CPU definition)
Signed-off-by: Huacai Chen <zltjiangshi@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.
Cc: Nathan Froyd <froydnj@codesourcery.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exceptionhandlers. The ISA mode is selectable via a user-writable CP0.Config3flag.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numberinginto the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral specialopcodes. Since there are several places where the delay slotrequirements for microMIPS branches differ from mips16 branches, usingopcodes is easier than checking hflags, then checking mips16...
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.