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Makefile.objs 136 Bytes
TODO 1.9 kB
cpu-qom.h 1.8 kB
cpu.c 1.8 kB
cpu.h 23.2 kB
helper.c 22.1 kB
helper.h 8.8 kB
machine.c 10.6 kB
mips-defs.h 2.1 kB
op_helper.c 103.9 kB
translate.c 365.1 kB
translate_init.c 22.3 kB

Latest revisions

# Date Author Comment
03e6e501 09/08/2012 02:37 am Maciej W. Rozycki

MIPS/user: Fix reset CPU state initialization

This change updates the CPU reset sequence to use a common piece of code
that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
not being set where applicable that causes floating-point MADD family...
36c6711b 08/27/2012 11:18 pm Eric Johnson

target-mips: allow microMIPS SWP and SDP to have RD equal to BASE

The microMIPS SWP and SDP instructions do not modify GPRs. So their
behavior is well defined when RD equals BASE. The MIPS Architecture
Verification Programs (AVPs) check that they work as expected. This...
2e15497c 08/27/2012 11:17 pm Eric Johnson

target-mips: add privilege level check to several Cop0 instructions

The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level. These changes are needed
to pass the AVP suite.

Signed-off-by: Eric Johnson <>...
b3167288 08/27/2012 01:17 pm Richard Henderson

mips-linux-user: Always support rdhwr.

The kernel will emulate this instruction if it's not supported
natively. This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <>
Cc: Riku Voipio <>...
05168674 08/27/2012 01:17 pm Richard Henderson

target-mips: Streamline indexed cp1 memory addressing.

We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <>
13d24f49 08/27/2012 01:03 pm Richard Sandiford

Fix order of CVT.PS.S operands

The FS input to CVT.PS.S is the high half and FT is the low half.
tcg_gen_concat_i32_i64 takes the low half first, so the operands
were in the wrong order.

Signed-off-by: Richard Sandiford <>
Signed-off-by: Aurelien Jarno <>
d22d7289 08/27/2012 01:03 pm Richard Sandiford

Fix operands of RECIP2.S and RECIP2.PS

Read the second input operand of RECIP2.S and RECIP2.PS from FT rather
than FD. RECIP2.D is already correct.

Signed-off-by: Richard Sandiford <>
Signed-off-by: Aurelien Jarno <>
6fc97faf 08/24/2012 02:03 am Stefan Weil

target-mips: Fix some helper functions (VR54xx multiplication)

Commits b5dc7732e1cc2fb549e48b7b5d664f2c79628e2e and
be24bb4f3007c3e07cbf1934f7e781493d876ab7 optimized the code
and removed the correct setting of t0. Fix this.

gcc-4.7 detected this bug because parameter arg1 was unused...
94159135 08/23/2012 06:21 pm Meador Inge

target-mips: Enable access to required RDHWR hardware registers

While running in the usermode emulator all of the required*
MIPS32r2 RDHWR hardware registers should be accessible (the
Linux kernel enables access to these same registers). Note
that these registers are still enabled when the MIPS ISA is...
f1cb0951 08/09/2012 09:36 pm Nathan Froyd

MIPS: Correct FCR0 initialization

This change addresses a problem where QEMU incorrectly traps on
floating-point MADD group instructions with SIGILL, at least while
emulating MIPS32r2 processors.  These instructions use the COP1X major
opcode and include ones like:...

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