cpu: Change qemu_init_vcpu() argument to CPUState
This allows to move the call into CPUState's realizefn.Therefore move the stub into libqemustub.a.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Make cpustats monitor command available unconditionally.
Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec()arguments to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
cpu: Move halted and interrupt_request fields to CPUState
Both fields are used in VMState, thus need to be moved together.Explicitly zero them on reset since they were located beforebreakpoints.
Pass PowerPCCPU to kvmppc_handle_halt().
cpu: Replace do_interrupt() by CPUClass::do_interrupt method
This removes a global per-target function and thus takes us one stepcloser to compiling multiple targets into one executable.
It will also allow to override the interrupt handling for certain CPU...
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
cpu: Introduce ENV_OFFSET macros
Introduce ENV_OFFSET macros which can be used in non-target-specificcode that needs to generate TCG instructions which reference CPUStatefields given the cpu_env register that TCG targets set up with apointer to the CPUArchState struct....
target-xtensa: Use mul*2 for mul*hi
Cc: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: Use add2/sub2 for mac
cpu: Add CPUArchState pointer to CPUState
The target-specific ENV_GET_CPU() macros have allowed us to navigatefrom CPUArchState to CPUState. The reverse direction was not supported.Avoid introducing CPU_GET_ENV() macros by initializing an untypedpointer that is initialized in derived instance_init functions....
target-xtensa: Move TCG initialization to XtensaCPU initfn
Combine this with breakpoint handler registration, guarding both withtcg_enabled() to suppress also TCG init for qtest. Rename the handler toxtensa_breakpoint_handler() since it needs to become global....
target-xtensa: Introduce QOM realizefn for XtensaCPU
Introduce realizefn and set realized = true in cpu_xtensa_init().
target-xtensa: Mark as unmigratable
There was no CPU_SAVE_VERSION defined, so neither "cpu_common" VMStatenor cpu_{save,load}() were registered. Their implementation was no-op.Therefore there is no backwards compatibility to keep, so mark XtensaCPUas unmigratable at device level....
target-xtensa: fix search_pc for the last TB opcode
Zero out tcg_ctx.gen_opc_instr_start for instructions representing thelast guest opcode in the TB.
Cc: qemu-stable@nongnu.orgSigned-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
softmmu: move include files to include/sysemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
misc: move include files to include/qemu/
qom: move include files to include/qom/
exec: move include files to include/exec/
build: kill libdis, move disassemblers to disas/
exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: fix ITLB/DTLB page protection flags
With MMU option xtensa architecture has two TLBs: ITLB and DTLB. ITLB isonly used for code access, DTLB is only for data. However TLB entries inboth TLBs have attribute field controlling write and exec access. These...
target-xtensa: implement ATOMCTL SR
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memorytype. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement CACHEATTR SR
In XEA1, the Options for Memory Protection and Translation and thecorresponding TLB management instructions are not available. Instead,functionality similar to the Region Protection Option is availablethrough the cache attribute register. See ISA, A.2.14 for details....
target-xtensa: restrict available SRs by enabled options
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,xsr) are associated with their corresponding SR and raise illegal opcodeexception in case the register is not configured for the core....
target-xtensa: better control rsr/wsr/xsr access to SRs
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagalopcode exception on illegal access to these SRs.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: implement MISC SR
The Miscellaneous Special Registers Option provides zero to four scratchregisters within the processor readable and writable by RSR, WSR, andXSR. These registers are privileged. They may be useful for someapplication-specific exception and interrupt processing tasks in the...
target-xtensa: use movcond where possible
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAXopcodes.
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
target-xtensa: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Andreas Färber <afaerber@suse.de>
cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.
Make include paths for cpu-qom.h consistent for alpha and unicore32.
Signed-off-by: Andreas Färber <afaerber@suse.de>[AF: Updated new target-openrisc function accordingly]...
target-xtensa: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Cc: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>...
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes arereserved) and its purpose doesn't match the name (most target_phys_addr_taddresses are not target specific). Replace it with a finger-friendly,...
target-xtensa: de-optimize EXTUI
Now that "and" with 0xff, 0xffff and 0xffffffff and "shr" with 0 shiftare optimized in tcg/tcg-op.h there is no need to do it intarget-xtensa/translate.c.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
target-xtensa: implement FP1 group
These are comparison and conditional move opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement coprocessor context option
In case Coprocessor Context option is enabled CPENABLE SR bits controlwhether access to coprocessors is allowed or would rise one ofCoprocessorXDisabled exceptions.
See ISA, 4.4.5 for more details.
FP is coprocessor 0....
target-xtensa: handle boolean option in overlays
target-xtensa: add FP registers
There are 16 32-bit FP registers (f0 - f15), control and status userregisters (fcr, fsr).
See ISA, 4.3.10 for more details.
target-xtensa: implement LSCX and LSCI groups
These are load/store instructions for FP registers with immediate orregister index and optional base post-update.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 arithmetic
These are FP arithmetic opcodes.See ISA, 4.3.10 for more details.
target-xtensa: implement FP0 conversions
These are FP to integer and integer to FP conversion opcodes.See ISA, 4.3.10 for more details.
Note that ISA description for utrunc.s is currently incorrect and willbe fixed in future revisions.
target-xtensa: fix extui shift amount
extui opcode only uses lowermost op1 bit for sa4.
Reported-by: malc <av1474@comtv.ru>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Cc: qemu-stable <qemu-stable@nongnu.org>Signed-off-by: malc <av1474@comtv.ru>
target-xtensa: don't emit extra tcg_gen_goto_tb
Unconditional gen_check_loop_end at the end of disas_xtensa_insncan emit tcg_gen_goto_tb with slot id already used in the TB (e.g. whenTB ends at LEND with a branch).
target-xtensa: fix missing errno codes for mingw32
Put the following errno value mappings under #ifdef:
xtensa-semi.c: In function 'errno_h2g':xtensa-semi.c:113: error: 'ENOTBLK' undeclared (first use in this function)xtensa-semi.c:113: error: (Each undeclared identifier is reported only once...
target-xtensa: convert host errno values to guest
Guest errno values are taken from the newlib. Convert only those errnovalues that can be returned from used system calls.
target-xtensa: return ENOSYS for unimplemented simcalls
This prevents guest from proceeding with uninitialised garbage returnedfrom unimplemented simcalls.
Merge branch 'x86cpu_qom_tcg_v2' of git://github.com/imammedo/qemu
target-xtensa: make default CPU depend on target endianness
This makes usable default for -cpu option both for qemu-system-xtensaand qemu-system-xtensaeb fixing the following error:
$ qemu-system-xtensaeb -M sim Unable to find CPU definition
target-xtensa: fix big-endian BBS/BBC implementation
Quote from ISA, 2.1:
For most Xtensa instructions, bit numbering is irrelevant; only the BBCand BBS instructions assign bit numbers to values on which the processoroperates. The BBC/BBS instructions use big-endian bit ordering (0 is the...
target-xtensa: drop usage of prev_debug_excp_handler
Chains of exception handlers are currently unused feature. Dropping itto be consistent with target-i386 but it may simplify qom-ifying CPUin future like for target-i386.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
target-xtensa: switch to AREG0-free mode
Add env parameter to every helper function that needs it, update'configure' script.
target-xtensa: add attributes to helper functions
Mark exception generating functions 'noreturn' and pure constantfunctions as such.
target-xtensa: remove unnecessary include of dyngen-exec.h
Signed-off-by: Peter Portante <peter.portante@redhat.com>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: fix CCOUNT for conditional branches
Taken conditional branches fail to update CCOUNT register becauseaccumulated ccount_delta is reset during translation of non-takenbranch. To fix it only update CCOUNT once per conditional branchinstruction translation....
target-xtensa: flush TLB page for new MMU mapping
Both old and new mappings need flushing because their VPN may bedifferent in MMU case.
target-xtensa: update EXCVADDR in case of page table lookup
According to ISA, 4.4.2.6, EXCVADDR may be changed by any TLB miss, evenif the miss is handled entirely by processor hardware.
target-xtensa: extract TLB entry setting method
target-xtensa: update autorefill TLB entries conditionally
This is to avoid interference of internal QEMU helpers(cpu_get_phys_page_debug, tb_invalidate_virtual_addr) with guest-visibleTLB state.
target-xtensa: control page table lookup explicitly
Hardware pagetable walking may not be nested. Stop guessing and passexplicit flag to the get_physical_addr_mmu function that controls pagetable lookup.
build: move other target-*/ objects to nested Makefile.objs
build: move libobj-y variable to nested Makefile.objs
build: move obj-TARGET-y variables to nested Makefile.objs
Also drop duplicate occurrence of device-hotplug.o.
Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-xtensa: Let cpu_xtensa_init() return XtensaCPU
Make the include paths for cpu-qom.h consistent to allow using XtensaCPUin cpu.h.
Turn cpu_init macro into a static inline function returningCPUXtensaState for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Translation of LOOP instructions used to call LEND SR write handler toupdate LEND and invalidate relevant TBs. Now that LEND SR write handlerends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple...
target-xtensa: add license to core-fsf.c
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: add license to core-dc232b.c
target-xtensa: add dc233c core
This is Diamond 233L Standard Core Rev.C (LE), implemented throughlinux/gdb overlay.
target-xtensa: fix tb invalidation for IBREAK and LOOP
Instruction breakpoint/zero overhead loop handling code is built intoTBs pointed to by IBREAKA/LEND SRs. When these or related SRs getchanged TBs at virtual addresses corresponding to their old and their...
Use uintptr_t for various op related functions
Use uintptr_t instead of void * or unsigned long inseveral op related functions, env->mem_io_pc andGETPC macro.
Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: Move helpers.h to helper.h
Provides a file naming scheme consistent with other targets.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU
Embed CPUXtensaState as first member of XtensaCPU.Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU reset
Move code from cpu_state_reset() into QOM xtensa_cpu_reset().To avoid moving reset_mmu() and dependencies, make it non-static.
target-xtensa: Start QOM'ifying CPU init
Move XtensaConfig-independent code from cpu_xtensa_init() into aQOM initfn, as a start.
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-xtensa: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
target-xtensa: Clean includes
Remove some include statements which are not needed.
Acked-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Stefan Weil <sw@weilnetz.de>
target-xtensa: add DBREAK data breakpoints
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debugwatchpoints.
This implementation is not fully compliant to ISA: when a breakpoint isset to an unmapped/inaccessible memory address it generates TLB/memory...
target-xtensa: add DEBUG_SECTION to overlay tool
Fill debug configuration from overlay definitions in the DEBUG_SECTION.Add DEBUG_SECTION to DC232B and FSF cores.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: add ICOUNT SR and debug exception
ICOUNT SR gets incremented on every instruction completion provided thatCINTLEVEL at the beginning of the instruction execution is lower thanICOUNTLEVEL.
When ICOUNT would increment to 0 a debug exception is raised if...
target-xtensa: add DEBUGCAUSE SR and configuration
DEBUGCAUSE SR holds information about the most recent debug exception.See ISA, 4.7.7 for more details.
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK andBREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
target-xtensa: implement info tlb monitor command
Command dumps valid ITLB and DTLB entries.
target-xtensa: fetch 3rd opcode byte only when needed
According to ISA, 3.5.4, third opcode byte should not be fetched for2-byte instructions.
target-xtensa: define TLB_TEMPLATE for MMU-less cores
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.Make TLB_TEMPLATE available for region protection core variants,defining 1 way ITLB and DTLB with 8 entries each.
target-xtensa: fix MMUv3 initialization
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively;- ITLB/DTLB way 6 attr field is set to 3 on reset.
target-xtensa: handle cache options in the overlay tool
Cache options must be enabled for the cores that have cache to avoidillegal instruction exceptions.
target-xtensa: raise an exception for invalid and reserved opcodes
This includes opcodes from disabled features and those marked reserved in the ISA.Also end TB on opcodes that definitely generate an exception: illegalinstructions, syscall and privileged instructions....
target-xtensa: mask out undefined bits of WINDOWSTART SR
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SRmust be zero.
target-xtensa: add fsf core
This is FSF big endian core implemented through linux overlay.
target-xtensa: add dc232b core
This is Diamond 232L Standard Core Rev.B (LE), implemented throughlinux/gdb overlay.
target-xtensa: extract core configuration from overlay
Introduce overlay_tool.h that defines core configuration blocks fromdata available in the linux architecture variant overlay.
Overlay data is automatically generated in the core configurationprocess by Tensilica tools and can be directly converted to qemu xtensa...
target-xtensa: implement external interrupt mapping
Xtensa cores may have different mapping of external interrupt pins tointernal IRQ numers. Implement API to acquire core IRQ by its externalinterrupt number.
target-xtensa: remove hand-written xtensa cores implementations
target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP;- add an option for MULSH/MULUH;- put S32C1I under conditional store option.