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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | fdf9b3e8 | bellard | */
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19 | fdf9b3e8 | bellard | #include <stdarg.h> |
20 | fdf9b3e8 | bellard | #include <stdlib.h> |
21 | fdf9b3e8 | bellard | #include <stdio.h> |
22 | fdf9b3e8 | bellard | #include <string.h> |
23 | fdf9b3e8 | bellard | #include <inttypes.h> |
24 | fdf9b3e8 | bellard | #include <signal.h> |
25 | fdf9b3e8 | bellard | |
26 | fdf9b3e8 | bellard | #include "cpu.h" |
27 | b279e5ef | Benoît Canet | |
28 | b279e5ef | Benoît Canet | #if !defined(CONFIG_USER_ONLY)
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29 | 0d09e41a | Paolo Bonzini | #include "hw/sh4/sh_intc.h" |
30 | b279e5ef | Benoît Canet | #endif
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31 | fdf9b3e8 | bellard | |
32 | 355fb23d | pbrook | #if defined(CONFIG_USER_ONLY)
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33 | 355fb23d | pbrook | |
34 | 97a8ea5a | Andreas Färber | void superh_cpu_do_interrupt(CPUState *cs)
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35 | 355fb23d | pbrook | { |
36 | 97a8ea5a | Andreas Färber | SuperHCPU *cpu = SUPERH_CPU(cs); |
37 | 97a8ea5a | Andreas Färber | CPUSH4State *env = &cpu->env; |
38 | 97a8ea5a | Andreas Färber | |
39 | 97a8ea5a | Andreas Färber | env->exception_index = -1;
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40 | 355fb23d | pbrook | } |
41 | 355fb23d | pbrook | |
42 | 73e5716c | Andreas Färber | int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, |
43 | 97b348e7 | Blue Swirl | int mmu_idx)
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44 | 355fb23d | pbrook | { |
45 | 355fb23d | pbrook | env->tea = address; |
46 | ee0dc6d3 | Blue Swirl | env->exception_index = -1;
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47 | 355fb23d | pbrook | switch (rw) {
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48 | 355fb23d | pbrook | case 0: |
49 | 355fb23d | pbrook | env->exception_index = 0x0a0;
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50 | 355fb23d | pbrook | break;
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51 | 355fb23d | pbrook | case 1: |
52 | 355fb23d | pbrook | env->exception_index = 0x0c0;
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53 | 355fb23d | pbrook | break;
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54 | cf7055bd | aurel32 | case 2: |
55 | cf7055bd | aurel32 | env->exception_index = 0x0a0;
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56 | cf7055bd | aurel32 | break;
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57 | 355fb23d | pbrook | } |
58 | 355fb23d | pbrook | return 1; |
59 | 355fb23d | pbrook | } |
60 | 355fb23d | pbrook | |
61 | 3c1adf12 | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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62 | 3c1adf12 | edgar_igl | { |
63 | 3c1adf12 | edgar_igl | /* For user mode, only U0 area is cachable. */
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64 | 679dee3c | edgar_igl | return !(addr & 0x80000000); |
65 | 3c1adf12 | edgar_igl | } |
66 | 3c1adf12 | edgar_igl | |
67 | 355fb23d | pbrook | #else /* !CONFIG_USER_ONLY */ |
68 | 355fb23d | pbrook | |
69 | fdf9b3e8 | bellard | #define MMU_OK 0 |
70 | fdf9b3e8 | bellard | #define MMU_ITLB_MISS (-1) |
71 | fdf9b3e8 | bellard | #define MMU_ITLB_MULTIPLE (-2) |
72 | fdf9b3e8 | bellard | #define MMU_ITLB_VIOLATION (-3) |
73 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_READ (-4) |
74 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_WRITE (-5) |
75 | fdf9b3e8 | bellard | #define MMU_DTLB_INITIAL_WRITE (-6) |
76 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_READ (-7) |
77 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_WRITE (-8) |
78 | fdf9b3e8 | bellard | #define MMU_DTLB_MULTIPLE (-9) |
79 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS (-10) |
80 | cf7055bd | aurel32 | #define MMU_IADDR_ERROR (-11) |
81 | cf7055bd | aurel32 | #define MMU_DADDR_ERROR_READ (-12) |
82 | cf7055bd | aurel32 | #define MMU_DADDR_ERROR_WRITE (-13) |
83 | fdf9b3e8 | bellard | |
84 | 97a8ea5a | Andreas Färber | void superh_cpu_do_interrupt(CPUState *cs)
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85 | fdf9b3e8 | bellard | { |
86 | 97a8ea5a | Andreas Färber | SuperHCPU *cpu = SUPERH_CPU(cs); |
87 | 97a8ea5a | Andreas Färber | CPUSH4State *env = &cpu->env; |
88 | 259186a7 | Andreas Färber | int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
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89 | e96e2044 | ths | int do_exp, irq_vector = env->exception_index;
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90 | e96e2044 | ths | |
91 | e96e2044 | ths | /* prioritize exceptions over interrupts */
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92 | e96e2044 | ths | |
93 | e96e2044 | ths | do_exp = env->exception_index != -1;
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94 | e96e2044 | ths | do_irq = do_irq && (env->exception_index == -1);
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95 | e96e2044 | ths | |
96 | e96e2044 | ths | if (env->sr & SR_BL) {
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97 | e96e2044 | ths | if (do_exp && env->exception_index != 0x1e0) { |
98 | e96e2044 | ths | env->exception_index = 0x000; /* masked exception -> reset */ |
99 | e96e2044 | ths | } |
100 | efac4154 | Aurelien Jarno | if (do_irq && !env->in_sleep) {
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101 | e96e2044 | ths | return; /* masked */ |
102 | e96e2044 | ths | } |
103 | e96e2044 | ths | } |
104 | efac4154 | Aurelien Jarno | env->in_sleep = 0;
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105 | e96e2044 | ths | |
106 | e96e2044 | ths | if (do_irq) {
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107 | e96e2044 | ths | irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
108 | e96e2044 | ths | (env->sr >> 4) & 0xf); |
109 | e96e2044 | ths | if (irq_vector == -1) { |
110 | e96e2044 | ths | return; /* masked */ |
111 | e96e2044 | ths | } |
112 | e96e2044 | ths | } |
113 | e96e2044 | ths | |
114 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_INT)) {
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115 | fdf9b3e8 | bellard | const char *expname; |
116 | fdf9b3e8 | bellard | switch (env->exception_index) {
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117 | fdf9b3e8 | bellard | case 0x0e0: |
118 | fdf9b3e8 | bellard | expname = "addr_error";
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119 | fdf9b3e8 | bellard | break;
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120 | fdf9b3e8 | bellard | case 0x040: |
121 | fdf9b3e8 | bellard | expname = "tlb_miss";
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122 | fdf9b3e8 | bellard | break;
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123 | fdf9b3e8 | bellard | case 0x0a0: |
124 | fdf9b3e8 | bellard | expname = "tlb_violation";
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125 | fdf9b3e8 | bellard | break;
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126 | fdf9b3e8 | bellard | case 0x180: |
127 | fdf9b3e8 | bellard | expname = "illegal_instruction";
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128 | fdf9b3e8 | bellard | break;
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129 | fdf9b3e8 | bellard | case 0x1a0: |
130 | fdf9b3e8 | bellard | expname = "slot_illegal_instruction";
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131 | fdf9b3e8 | bellard | break;
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132 | fdf9b3e8 | bellard | case 0x800: |
133 | fdf9b3e8 | bellard | expname = "fpu_disable";
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134 | fdf9b3e8 | bellard | break;
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135 | fdf9b3e8 | bellard | case 0x820: |
136 | fdf9b3e8 | bellard | expname = "slot_fpu";
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137 | fdf9b3e8 | bellard | break;
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138 | fdf9b3e8 | bellard | case 0x100: |
139 | fdf9b3e8 | bellard | expname = "data_write";
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140 | fdf9b3e8 | bellard | break;
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141 | fdf9b3e8 | bellard | case 0x060: |
142 | fdf9b3e8 | bellard | expname = "dtlb_miss_write";
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143 | fdf9b3e8 | bellard | break;
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144 | fdf9b3e8 | bellard | case 0x0c0: |
145 | fdf9b3e8 | bellard | expname = "dtlb_violation_write";
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146 | fdf9b3e8 | bellard | break;
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147 | fdf9b3e8 | bellard | case 0x120: |
148 | fdf9b3e8 | bellard | expname = "fpu_exception";
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149 | fdf9b3e8 | bellard | break;
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150 | fdf9b3e8 | bellard | case 0x080: |
151 | fdf9b3e8 | bellard | expname = "initial_page_write";
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152 | fdf9b3e8 | bellard | break;
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153 | fdf9b3e8 | bellard | case 0x160: |
154 | fdf9b3e8 | bellard | expname = "trapa";
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155 | fdf9b3e8 | bellard | break;
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156 | fdf9b3e8 | bellard | default:
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157 | e96e2044 | ths | expname = do_irq ? "interrupt" : "???"; |
158 | e96e2044 | ths | break;
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159 | fdf9b3e8 | bellard | } |
160 | 93fcfe39 | aliguori | qemu_log("exception 0x%03x [%s] raised\n",
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161 | 93fcfe39 | aliguori | irq_vector, expname); |
162 | a0762859 | Andreas Färber | log_cpu_state(cs, 0);
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163 | fdf9b3e8 | bellard | } |
164 | fdf9b3e8 | bellard | |
165 | fdf9b3e8 | bellard | env->ssr = env->sr; |
166 | e96e2044 | ths | env->spc = env->pc; |
167 | fdf9b3e8 | bellard | env->sgr = env->gregs[15];
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168 | fdf9b3e8 | bellard | env->sr |= SR_BL | SR_MD | SR_RB; |
169 | fdf9b3e8 | bellard | |
170 | 274a9e70 | aurel32 | if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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171 | 274a9e70 | aurel32 | /* Branch instruction should be executed again before delay slot. */
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172 | 274a9e70 | aurel32 | env->spc -= 2;
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173 | 274a9e70 | aurel32 | /* Clear flags for exception/interrupt routine. */
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174 | 274a9e70 | aurel32 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE); |
175 | 274a9e70 | aurel32 | } |
176 | 274a9e70 | aurel32 | if (env->flags & DELAY_SLOT_CLEARME)
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177 | 274a9e70 | aurel32 | env->flags = 0;
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178 | 274a9e70 | aurel32 | |
179 | e96e2044 | ths | if (do_exp) {
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180 | e96e2044 | ths | env->expevt = env->exception_index; |
181 | e96e2044 | ths | switch (env->exception_index) {
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182 | e96e2044 | ths | case 0x000: |
183 | e96e2044 | ths | case 0x020: |
184 | e96e2044 | ths | case 0x140: |
185 | e96e2044 | ths | env->sr &= ~SR_FD; |
186 | e96e2044 | ths | env->sr |= 0xf << 4; /* IMASK */ |
187 | e96e2044 | ths | env->pc = 0xa0000000;
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188 | e96e2044 | ths | break;
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189 | e96e2044 | ths | case 0x040: |
190 | e96e2044 | ths | case 0x060: |
191 | e96e2044 | ths | env->pc = env->vbr + 0x400;
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192 | e96e2044 | ths | break;
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193 | e96e2044 | ths | case 0x160: |
194 | e96e2044 | ths | env->spc += 2; /* special case for TRAPA */ |
195 | e96e2044 | ths | /* fall through */
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196 | e96e2044 | ths | default:
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197 | e96e2044 | ths | env->pc = env->vbr + 0x100;
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198 | e96e2044 | ths | break;
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199 | e96e2044 | ths | } |
200 | e96e2044 | ths | return;
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201 | e96e2044 | ths | } |
202 | e96e2044 | ths | |
203 | e96e2044 | ths | if (do_irq) {
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204 | e96e2044 | ths | env->intevt = irq_vector; |
205 | e96e2044 | ths | env->pc = env->vbr + 0x600;
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206 | e96e2044 | ths | return;
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207 | fdf9b3e8 | bellard | } |
208 | fdf9b3e8 | bellard | } |
209 | fdf9b3e8 | bellard | |
210 | 73e5716c | Andreas Färber | static void update_itlb_use(CPUSH4State * env, int itlbnb) |
211 | fdf9b3e8 | bellard | { |
212 | fdf9b3e8 | bellard | uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
213 | fdf9b3e8 | bellard | |
214 | fdf9b3e8 | bellard | switch (itlbnb) {
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215 | fdf9b3e8 | bellard | case 0: |
216 | ea2b542a | aurel32 | and_mask = 0x1f;
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217 | fdf9b3e8 | bellard | break;
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218 | fdf9b3e8 | bellard | case 1: |
219 | fdf9b3e8 | bellard | and_mask = 0xe7;
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220 | fdf9b3e8 | bellard | or_mask = 0x80;
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221 | fdf9b3e8 | bellard | break;
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222 | fdf9b3e8 | bellard | case 2: |
223 | fdf9b3e8 | bellard | and_mask = 0xfb;
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224 | fdf9b3e8 | bellard | or_mask = 0x50;
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225 | fdf9b3e8 | bellard | break;
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226 | fdf9b3e8 | bellard | case 3: |
227 | fdf9b3e8 | bellard | or_mask = 0x2c;
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228 | fdf9b3e8 | bellard | break;
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229 | fdf9b3e8 | bellard | } |
230 | fdf9b3e8 | bellard | |
231 | ea2b542a | aurel32 | env->mmucr &= (and_mask << 24) | 0x00ffffff; |
232 | fdf9b3e8 | bellard | env->mmucr |= (or_mask << 24);
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233 | fdf9b3e8 | bellard | } |
234 | fdf9b3e8 | bellard | |
235 | 73e5716c | Andreas Färber | static int itlb_replacement(CPUSH4State * env) |
236 | fdf9b3e8 | bellard | { |
237 | fdf9b3e8 | bellard | if ((env->mmucr & 0xe0000000) == 0xe0000000) |
238 | fdf9b3e8 | bellard | return 0; |
239 | ea2b542a | aurel32 | if ((env->mmucr & 0x98000000) == 0x18000000) |
240 | fdf9b3e8 | bellard | return 1; |
241 | fdf9b3e8 | bellard | if ((env->mmucr & 0x54000000) == 0x04000000) |
242 | fdf9b3e8 | bellard | return 2; |
243 | fdf9b3e8 | bellard | if ((env->mmucr & 0x2c000000) == 0x00000000) |
244 | fdf9b3e8 | bellard | return 3; |
245 | 43dc2a64 | Blue Swirl | cpu_abort(env, "Unhandled itlb_replacement");
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246 | fdf9b3e8 | bellard | } |
247 | fdf9b3e8 | bellard | |
248 | fdf9b3e8 | bellard | /* Find the corresponding entry in the right TLB
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249 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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250 | fdf9b3e8 | bellard | */
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251 | 73e5716c | Andreas Färber | static int find_tlb_entry(CPUSH4State * env, target_ulong address, |
252 | fdf9b3e8 | bellard | tlb_t * entries, uint8_t nbtlb, int use_asid)
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253 | fdf9b3e8 | bellard | { |
254 | fdf9b3e8 | bellard | int match = MMU_DTLB_MISS;
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255 | fdf9b3e8 | bellard | uint32_t start, end; |
256 | fdf9b3e8 | bellard | uint8_t asid; |
257 | fdf9b3e8 | bellard | int i;
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258 | fdf9b3e8 | bellard | |
259 | fdf9b3e8 | bellard | asid = env->pteh & 0xff;
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260 | fdf9b3e8 | bellard | |
261 | fdf9b3e8 | bellard | for (i = 0; i < nbtlb; i++) { |
262 | fdf9b3e8 | bellard | if (!entries[i].v)
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263 | fdf9b3e8 | bellard | continue; /* Invalid entry */ |
264 | eeda6778 | aurel32 | if (!entries[i].sh && use_asid && entries[i].asid != asid)
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265 | fdf9b3e8 | bellard | continue; /* Bad ASID */ |
266 | fdf9b3e8 | bellard | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
267 | fdf9b3e8 | bellard | end = start + entries[i].size - 1;
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268 | fdf9b3e8 | bellard | if (address >= start && address <= end) { /* Match */ |
269 | ea2b542a | aurel32 | if (match != MMU_DTLB_MISS)
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270 | fdf9b3e8 | bellard | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
271 | fdf9b3e8 | bellard | match = i; |
272 | fdf9b3e8 | bellard | } |
273 | fdf9b3e8 | bellard | } |
274 | fdf9b3e8 | bellard | return match;
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275 | fdf9b3e8 | bellard | } |
276 | fdf9b3e8 | bellard | |
277 | 73e5716c | Andreas Färber | static void increment_urc(CPUSH4State * env) |
278 | 29e179bc | aurel32 | { |
279 | 29e179bc | aurel32 | uint8_t urb, urc; |
280 | 29e179bc | aurel32 | |
281 | 29e179bc | aurel32 | /* Increment URC */
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282 | 29e179bc | aurel32 | urb = ((env->mmucr) >> 18) & 0x3f; |
283 | 29e179bc | aurel32 | urc = ((env->mmucr) >> 10) & 0x3f; |
284 | 29e179bc | aurel32 | urc++; |
285 | 927e3a4e | aurel32 | if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
286 | 29e179bc | aurel32 | urc = 0;
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287 | 29e179bc | aurel32 | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
288 | 29e179bc | aurel32 | } |
289 | 29e179bc | aurel32 | |
290 | 829a4927 | Aurelien Jarno | /* Copy and utlb entry into itlb
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291 | 829a4927 | Aurelien Jarno | Return entry
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292 | 829a4927 | Aurelien Jarno | */
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293 | 73e5716c | Andreas Färber | static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) |
294 | 829a4927 | Aurelien Jarno | { |
295 | 829a4927 | Aurelien Jarno | int itlb;
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296 | 829a4927 | Aurelien Jarno | |
297 | 829a4927 | Aurelien Jarno | tlb_t * ientry; |
298 | 829a4927 | Aurelien Jarno | itlb = itlb_replacement(env); |
299 | 829a4927 | Aurelien Jarno | ientry = &env->itlb[itlb]; |
300 | 829a4927 | Aurelien Jarno | if (ientry->v) {
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301 | 829a4927 | Aurelien Jarno | tlb_flush_page(env, ientry->vpn << 10);
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302 | 829a4927 | Aurelien Jarno | } |
303 | 829a4927 | Aurelien Jarno | *ientry = env->utlb[utlb]; |
304 | 829a4927 | Aurelien Jarno | update_itlb_use(env, itlb); |
305 | 829a4927 | Aurelien Jarno | return itlb;
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306 | 829a4927 | Aurelien Jarno | } |
307 | 829a4927 | Aurelien Jarno | |
308 | 829a4927 | Aurelien Jarno | /* Find itlb entry
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309 | fdf9b3e8 | bellard | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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310 | fdf9b3e8 | bellard | */
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311 | 73e5716c | Andreas Färber | static int find_itlb_entry(CPUSH4State * env, target_ulong address, |
312 | 829a4927 | Aurelien Jarno | int use_asid)
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313 | fdf9b3e8 | bellard | { |
314 | 829a4927 | Aurelien Jarno | int e;
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315 | fdf9b3e8 | bellard | |
316 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
317 | 829a4927 | Aurelien Jarno | if (e == MMU_DTLB_MULTIPLE) {
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318 | fdf9b3e8 | bellard | e = MMU_ITLB_MULTIPLE; |
319 | 829a4927 | Aurelien Jarno | } else if (e == MMU_DTLB_MISS) { |
320 | ea2b542a | aurel32 | e = MMU_ITLB_MISS; |
321 | 829a4927 | Aurelien Jarno | } else if (e >= 0) { |
322 | fdf9b3e8 | bellard | update_itlb_use(env, e); |
323 | 829a4927 | Aurelien Jarno | } |
324 | fdf9b3e8 | bellard | return e;
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325 | fdf9b3e8 | bellard | } |
326 | fdf9b3e8 | bellard | |
327 | fdf9b3e8 | bellard | /* Find utlb entry
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328 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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329 | 73e5716c | Andreas Färber | static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid) |
330 | fdf9b3e8 | bellard | { |
331 | 29e179bc | aurel32 | /* per utlb access */
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332 | 29e179bc | aurel32 | increment_urc(env); |
333 | fdf9b3e8 | bellard | |
334 | fdf9b3e8 | bellard | /* Return entry */
|
335 | fdf9b3e8 | bellard | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
|
336 | fdf9b3e8 | bellard | } |
337 | fdf9b3e8 | bellard | |
338 | fdf9b3e8 | bellard | /* Match address against MMU
|
339 | fdf9b3e8 | bellard | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
|
340 | fdf9b3e8 | bellard | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
|
341 | fdf9b3e8 | bellard | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
|
342 | cf7055bd | aurel32 | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
|
343 | cf7055bd | aurel32 | MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
|
344 | fdf9b3e8 | bellard | */
|
345 | 73e5716c | Andreas Färber | static int get_mmu_address(CPUSH4State * env, target_ulong * physical, |
346 | fdf9b3e8 | bellard | int *prot, target_ulong address,
|
347 | fdf9b3e8 | bellard | int rw, int access_type) |
348 | fdf9b3e8 | bellard | { |
349 | cf7055bd | aurel32 | int use_asid, n;
|
350 | fdf9b3e8 | bellard | tlb_t *matching = NULL;
|
351 | fdf9b3e8 | bellard | |
352 | 06afe2c8 | aurel32 | use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
353 | fdf9b3e8 | bellard | |
354 | cf7055bd | aurel32 | if (rw == 2) { |
355 | 829a4927 | Aurelien Jarno | n = find_itlb_entry(env, address, use_asid); |
356 | fdf9b3e8 | bellard | if (n >= 0) { |
357 | fdf9b3e8 | bellard | matching = &env->itlb[n]; |
358 | 4d1e4ff6 | Aurelien Jarno | if (!(env->sr & SR_MD) && !(matching->pr & 2)) |
359 | fdf9b3e8 | bellard | n = MMU_ITLB_VIOLATION; |
360 | fdf9b3e8 | bellard | else
|
361 | 5a25cc2b | Aurelien Jarno | *prot = PAGE_EXEC; |
362 | 829a4927 | Aurelien Jarno | } else {
|
363 | 829a4927 | Aurelien Jarno | n = find_utlb_entry(env, address, use_asid); |
364 | 829a4927 | Aurelien Jarno | if (n >= 0) { |
365 | 829a4927 | Aurelien Jarno | n = copy_utlb_entry_itlb(env, n); |
366 | 829a4927 | Aurelien Jarno | matching = &env->itlb[n]; |
367 | 829a4927 | Aurelien Jarno | if (!(env->sr & SR_MD) && !(matching->pr & 2)) { |
368 | 829a4927 | Aurelien Jarno | n = MMU_ITLB_VIOLATION; |
369 | 829a4927 | Aurelien Jarno | } else {
|
370 | 829a4927 | Aurelien Jarno | *prot = PAGE_READ | PAGE_EXEC; |
371 | 829a4927 | Aurelien Jarno | if ((matching->pr & 1) && matching->d) { |
372 | 829a4927 | Aurelien Jarno | *prot |= PAGE_WRITE; |
373 | 829a4927 | Aurelien Jarno | } |
374 | 829a4927 | Aurelien Jarno | } |
375 | 829a4927 | Aurelien Jarno | } else if (n == MMU_DTLB_MULTIPLE) { |
376 | 829a4927 | Aurelien Jarno | n = MMU_ITLB_MULTIPLE; |
377 | 829a4927 | Aurelien Jarno | } else if (n == MMU_DTLB_MISS) { |
378 | 829a4927 | Aurelien Jarno | n = MMU_ITLB_MISS; |
379 | 829a4927 | Aurelien Jarno | } |
380 | fdf9b3e8 | bellard | } |
381 | fdf9b3e8 | bellard | } else {
|
382 | fdf9b3e8 | bellard | n = find_utlb_entry(env, address, use_asid); |
383 | fdf9b3e8 | bellard | if (n >= 0) { |
384 | fdf9b3e8 | bellard | matching = &env->utlb[n]; |
385 | 628b61a0 | Aurelien Jarno | if (!(env->sr & SR_MD) && !(matching->pr & 2)) { |
386 | 628b61a0 | Aurelien Jarno | n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
387 | 628b61a0 | Aurelien Jarno | MMU_DTLB_VIOLATION_READ; |
388 | 628b61a0 | Aurelien Jarno | } else if ((rw == 1) && !(matching->pr & 1)) { |
389 | 628b61a0 | Aurelien Jarno | n = MMU_DTLB_VIOLATION_WRITE; |
390 | 0c16e71e | Aurelien Jarno | } else if ((rw == 1) && !matching->d) { |
391 | 628b61a0 | Aurelien Jarno | n = MMU_DTLB_INITIAL_WRITE; |
392 | 628b61a0 | Aurelien Jarno | } else {
|
393 | 628b61a0 | Aurelien Jarno | *prot = PAGE_READ; |
394 | 628b61a0 | Aurelien Jarno | if ((matching->pr & 1) && matching->d) { |
395 | 628b61a0 | Aurelien Jarno | *prot |= PAGE_WRITE; |
396 | 628b61a0 | Aurelien Jarno | } |
397 | 628b61a0 | Aurelien Jarno | } |
398 | fdf9b3e8 | bellard | } else if (n == MMU_DTLB_MISS) { |
399 | cf7055bd | aurel32 | n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
|
400 | fdf9b3e8 | bellard | MMU_DTLB_MISS_READ; |
401 | fdf9b3e8 | bellard | } |
402 | fdf9b3e8 | bellard | } |
403 | fdf9b3e8 | bellard | if (n >= 0) { |
404 | 628b61a0 | Aurelien Jarno | n = MMU_OK; |
405 | fdf9b3e8 | bellard | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
406 | fdf9b3e8 | bellard | (address & (matching->size - 1));
|
407 | fdf9b3e8 | bellard | } |
408 | fdf9b3e8 | bellard | return n;
|
409 | fdf9b3e8 | bellard | } |
410 | fdf9b3e8 | bellard | |
411 | 73e5716c | Andreas Färber | static int get_physical_address(CPUSH4State * env, target_ulong * physical, |
412 | ef7ec1c1 | aurel32 | int *prot, target_ulong address,
|
413 | ef7ec1c1 | aurel32 | int rw, int access_type) |
414 | fdf9b3e8 | bellard | { |
415 | fdf9b3e8 | bellard | /* P1, P2 and P4 areas do not use translation */
|
416 | fdf9b3e8 | bellard | if ((address >= 0x80000000 && address < 0xc0000000) || |
417 | fdf9b3e8 | bellard | address >= 0xe0000000) {
|
418 | fdf9b3e8 | bellard | if (!(env->sr & SR_MD)
|
419 | 03e3b61e | Aurelien Jarno | && (address < 0xe0000000 || address >= 0xe4000000)) { |
420 | fdf9b3e8 | bellard | /* Unauthorized access in user mode (only store queues are available) */
|
421 | fdf9b3e8 | bellard | fprintf(stderr, "Unauthorized access\n");
|
422 | cf7055bd | aurel32 | if (rw == 0) |
423 | cf7055bd | aurel32 | return MMU_DADDR_ERROR_READ;
|
424 | cf7055bd | aurel32 | else if (rw == 1) |
425 | cf7055bd | aurel32 | return MMU_DADDR_ERROR_WRITE;
|
426 | cf7055bd | aurel32 | else
|
427 | cf7055bd | aurel32 | return MMU_IADDR_ERROR;
|
428 | fdf9b3e8 | bellard | } |
429 | 29e179bc | aurel32 | if (address >= 0x80000000 && address < 0xc0000000) { |
430 | 29e179bc | aurel32 | /* Mask upper 3 bits for P1 and P2 areas */
|
431 | 29e179bc | aurel32 | *physical = address & 0x1fffffff;
|
432 | 29e179bc | aurel32 | } else {
|
433 | 29e179bc | aurel32 | *physical = address; |
434 | 29e179bc | aurel32 | } |
435 | 5a25cc2b | Aurelien Jarno | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
436 | fdf9b3e8 | bellard | return MMU_OK;
|
437 | fdf9b3e8 | bellard | } |
438 | fdf9b3e8 | bellard | |
439 | fdf9b3e8 | bellard | /* If MMU is disabled, return the corresponding physical page */
|
440 | 0c16e71e | Aurelien Jarno | if (!(env->mmucr & MMUCR_AT)) {
|
441 | fdf9b3e8 | bellard | *physical = address & 0x1FFFFFFF;
|
442 | 5a25cc2b | Aurelien Jarno | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
443 | fdf9b3e8 | bellard | return MMU_OK;
|
444 | fdf9b3e8 | bellard | } |
445 | fdf9b3e8 | bellard | |
446 | fdf9b3e8 | bellard | /* We need to resort to the MMU */
|
447 | fdf9b3e8 | bellard | return get_mmu_address(env, physical, prot, address, rw, access_type);
|
448 | fdf9b3e8 | bellard | } |
449 | fdf9b3e8 | bellard | |
450 | 73e5716c | Andreas Färber | int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, |
451 | 97b348e7 | Blue Swirl | int mmu_idx)
|
452 | fdf9b3e8 | bellard | { |
453 | 0f3f1ec7 | Aurelien Jarno | target_ulong physical; |
454 | fdf9b3e8 | bellard | int prot, ret, access_type;
|
455 | fdf9b3e8 | bellard | |
456 | fdf9b3e8 | bellard | access_type = ACCESS_INT; |
457 | fdf9b3e8 | bellard | ret = |
458 | fdf9b3e8 | bellard | get_physical_address(env, &physical, &prot, address, rw, |
459 | fdf9b3e8 | bellard | access_type); |
460 | fdf9b3e8 | bellard | |
461 | fdf9b3e8 | bellard | if (ret != MMU_OK) {
|
462 | fdf9b3e8 | bellard | env->tea = address; |
463 | e3f114f7 | Alexandre Courbot | if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
|
464 | e3f114f7 | Alexandre Courbot | env->pteh = (env->pteh & PTEH_ASID_MASK) | |
465 | e3f114f7 | Alexandre Courbot | (address & PTEH_VPN_MASK); |
466 | e3f114f7 | Alexandre Courbot | } |
467 | fdf9b3e8 | bellard | switch (ret) {
|
468 | fdf9b3e8 | bellard | case MMU_ITLB_MISS:
|
469 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_READ:
|
470 | fdf9b3e8 | bellard | env->exception_index = 0x040;
|
471 | fdf9b3e8 | bellard | break;
|
472 | fdf9b3e8 | bellard | case MMU_DTLB_MULTIPLE:
|
473 | fdf9b3e8 | bellard | case MMU_ITLB_MULTIPLE:
|
474 | fdf9b3e8 | bellard | env->exception_index = 0x140;
|
475 | fdf9b3e8 | bellard | break;
|
476 | fdf9b3e8 | bellard | case MMU_ITLB_VIOLATION:
|
477 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
478 | fdf9b3e8 | bellard | break;
|
479 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_WRITE:
|
480 | fdf9b3e8 | bellard | env->exception_index = 0x060;
|
481 | fdf9b3e8 | bellard | break;
|
482 | fdf9b3e8 | bellard | case MMU_DTLB_INITIAL_WRITE:
|
483 | fdf9b3e8 | bellard | env->exception_index = 0x080;
|
484 | fdf9b3e8 | bellard | break;
|
485 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_READ:
|
486 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
487 | fdf9b3e8 | bellard | break;
|
488 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_WRITE:
|
489 | fdf9b3e8 | bellard | env->exception_index = 0x0c0;
|
490 | fdf9b3e8 | bellard | break;
|
491 | cf7055bd | aurel32 | case MMU_IADDR_ERROR:
|
492 | cf7055bd | aurel32 | case MMU_DADDR_ERROR_READ:
|
493 | bec43cc3 | Alexandre Courbot | env->exception_index = 0x0e0;
|
494 | cf7055bd | aurel32 | break;
|
495 | cf7055bd | aurel32 | case MMU_DADDR_ERROR_WRITE:
|
496 | cf7055bd | aurel32 | env->exception_index = 0x100;
|
497 | cf7055bd | aurel32 | break;
|
498 | fdf9b3e8 | bellard | default:
|
499 | 43dc2a64 | Blue Swirl | cpu_abort(env, "Unhandled MMU fault");
|
500 | fdf9b3e8 | bellard | } |
501 | fdf9b3e8 | bellard | return 1; |
502 | fdf9b3e8 | bellard | } |
503 | fdf9b3e8 | bellard | |
504 | 0f3f1ec7 | Aurelien Jarno | address &= TARGET_PAGE_MASK; |
505 | 0f3f1ec7 | Aurelien Jarno | physical &= TARGET_PAGE_MASK; |
506 | fdf9b3e8 | bellard | |
507 | d4c430a8 | Paul Brook | tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); |
508 | d4c430a8 | Paul Brook | return 0; |
509 | fdf9b3e8 | bellard | } |
510 | 355fb23d | pbrook | |
511 | 00b941e5 | Andreas Färber | hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
512 | 355fb23d | pbrook | { |
513 | 00b941e5 | Andreas Färber | SuperHCPU *cpu = SUPERH_CPU(cs); |
514 | 355fb23d | pbrook | target_ulong physical; |
515 | 355fb23d | pbrook | int prot;
|
516 | 355fb23d | pbrook | |
517 | 00b941e5 | Andreas Färber | get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0); |
518 | 355fb23d | pbrook | return physical;
|
519 | 355fb23d | pbrook | } |
520 | 355fb23d | pbrook | |
521 | ef7ec1c1 | aurel32 | void cpu_load_tlb(CPUSH4State * env)
|
522 | ea2b542a | aurel32 | { |
523 | ea2b542a | aurel32 | int n = cpu_mmucr_urc(env->mmucr);
|
524 | ea2b542a | aurel32 | tlb_t * entry = &env->utlb[n]; |
525 | ea2b542a | aurel32 | |
526 | 06afe2c8 | aurel32 | if (entry->v) {
|
527 | 06afe2c8 | aurel32 | /* Overwriting valid entry in utlb. */
|
528 | 06afe2c8 | aurel32 | target_ulong address = entry->vpn << 10;
|
529 | 5a25cc2b | Aurelien Jarno | tlb_flush_page(env, address); |
530 | 06afe2c8 | aurel32 | } |
531 | 06afe2c8 | aurel32 | |
532 | ea2b542a | aurel32 | /* Take values into cpu status from registers. */
|
533 | ea2b542a | aurel32 | entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
534 | ea2b542a | aurel32 | entry->vpn = cpu_pteh_vpn(env->pteh); |
535 | ea2b542a | aurel32 | entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
536 | ea2b542a | aurel32 | entry->ppn = cpu_ptel_ppn(env->ptel); |
537 | ea2b542a | aurel32 | entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
538 | ea2b542a | aurel32 | switch (entry->sz) {
|
539 | ea2b542a | aurel32 | case 0: /* 00 */ |
540 | ea2b542a | aurel32 | entry->size = 1024; /* 1K */ |
541 | ea2b542a | aurel32 | break;
|
542 | ea2b542a | aurel32 | case 1: /* 01 */ |
543 | ea2b542a | aurel32 | entry->size = 1024 * 4; /* 4K */ |
544 | ea2b542a | aurel32 | break;
|
545 | ea2b542a | aurel32 | case 2: /* 10 */ |
546 | ea2b542a | aurel32 | entry->size = 1024 * 64; /* 64K */ |
547 | ea2b542a | aurel32 | break;
|
548 | ea2b542a | aurel32 | case 3: /* 11 */ |
549 | ea2b542a | aurel32 | entry->size = 1024 * 1024; /* 1M */ |
550 | ea2b542a | aurel32 | break;
|
551 | ea2b542a | aurel32 | default:
|
552 | 43dc2a64 | Blue Swirl | cpu_abort(env, "Unhandled load_tlb");
|
553 | ea2b542a | aurel32 | break;
|
554 | ea2b542a | aurel32 | } |
555 | ea2b542a | aurel32 | entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
556 | ea2b542a | aurel32 | entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
557 | ea2b542a | aurel32 | entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
558 | ea2b542a | aurel32 | entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
559 | ea2b542a | aurel32 | entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
560 | ea2b542a | aurel32 | entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
561 | ea2b542a | aurel32 | entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
562 | ea2b542a | aurel32 | } |
563 | ea2b542a | aurel32 | |
564 | e0bcb9ca | Aurelien Jarno | void cpu_sh4_invalidate_tlb(CPUSH4State *s)
|
565 | e0bcb9ca | Aurelien Jarno | { |
566 | e0bcb9ca | Aurelien Jarno | int i;
|
567 | e0bcb9ca | Aurelien Jarno | |
568 | e0bcb9ca | Aurelien Jarno | /* UTLB */
|
569 | e0bcb9ca | Aurelien Jarno | for (i = 0; i < UTLB_SIZE; i++) { |
570 | e0bcb9ca | Aurelien Jarno | tlb_t * entry = &s->utlb[i]; |
571 | e0bcb9ca | Aurelien Jarno | entry->v = 0;
|
572 | e0bcb9ca | Aurelien Jarno | } |
573 | e0bcb9ca | Aurelien Jarno | /* ITLB */
|
574 | e40a67be | Alexandre Courbot | for (i = 0; i < ITLB_SIZE; i++) { |
575 | e40a67be | Alexandre Courbot | tlb_t * entry = &s->itlb[i]; |
576 | e0bcb9ca | Aurelien Jarno | entry->v = 0;
|
577 | e0bcb9ca | Aurelien Jarno | } |
578 | e0bcb9ca | Aurelien Jarno | |
579 | e0bcb9ca | Aurelien Jarno | tlb_flush(s, 1);
|
580 | e0bcb9ca | Aurelien Jarno | } |
581 | e0bcb9ca | Aurelien Jarno | |
582 | bc656a29 | Aurelien Jarno | uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, |
583 | a8170e5e | Avi Kivity | hwaddr addr) |
584 | bc656a29 | Aurelien Jarno | { |
585 | bc656a29 | Aurelien Jarno | int index = (addr & 0x00000300) >> 8; |
586 | bc656a29 | Aurelien Jarno | tlb_t * entry = &s->itlb[index]; |
587 | bc656a29 | Aurelien Jarno | |
588 | bc656a29 | Aurelien Jarno | return (entry->vpn << 10) | |
589 | bc656a29 | Aurelien Jarno | (entry->v << 8) |
|
590 | bc656a29 | Aurelien Jarno | (entry->asid); |
591 | bc656a29 | Aurelien Jarno | } |
592 | bc656a29 | Aurelien Jarno | |
593 | a8170e5e | Avi Kivity | void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
|
594 | c0f809c4 | Aurelien Jarno | uint32_t mem_value) |
595 | c0f809c4 | Aurelien Jarno | { |
596 | c0f809c4 | Aurelien Jarno | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
597 | c0f809c4 | Aurelien Jarno | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
598 | c0f809c4 | Aurelien Jarno | uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
599 | c0f809c4 | Aurelien Jarno | |
600 | 9f97309a | Aurelien Jarno | int index = (addr & 0x00000300) >> 8; |
601 | c0f809c4 | Aurelien Jarno | tlb_t * entry = &s->itlb[index]; |
602 | c0f809c4 | Aurelien Jarno | if (entry->v) {
|
603 | c0f809c4 | Aurelien Jarno | /* Overwriting valid entry in itlb. */
|
604 | c0f809c4 | Aurelien Jarno | target_ulong address = entry->vpn << 10;
|
605 | c0f809c4 | Aurelien Jarno | tlb_flush_page(s, address); |
606 | c0f809c4 | Aurelien Jarno | } |
607 | c0f809c4 | Aurelien Jarno | entry->asid = asid; |
608 | c0f809c4 | Aurelien Jarno | entry->vpn = vpn; |
609 | c0f809c4 | Aurelien Jarno | entry->v = v; |
610 | c0f809c4 | Aurelien Jarno | } |
611 | c0f809c4 | Aurelien Jarno | |
612 | bc656a29 | Aurelien Jarno | uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s, |
613 | a8170e5e | Avi Kivity | hwaddr addr) |
614 | bc656a29 | Aurelien Jarno | { |
615 | bc656a29 | Aurelien Jarno | int array = (addr & 0x00800000) >> 23; |
616 | bc656a29 | Aurelien Jarno | int index = (addr & 0x00000300) >> 8; |
617 | bc656a29 | Aurelien Jarno | tlb_t * entry = &s->itlb[index]; |
618 | bc656a29 | Aurelien Jarno | |
619 | bc656a29 | Aurelien Jarno | if (array == 0) { |
620 | bc656a29 | Aurelien Jarno | /* ITLB Data Array 1 */
|
621 | bc656a29 | Aurelien Jarno | return (entry->ppn << 10) | |
622 | bc656a29 | Aurelien Jarno | (entry->v << 8) |
|
623 | bc656a29 | Aurelien Jarno | (entry->pr << 5) |
|
624 | bc656a29 | Aurelien Jarno | ((entry->sz & 1) << 6) | |
625 | bc656a29 | Aurelien Jarno | ((entry->sz & 2) << 4) | |
626 | bc656a29 | Aurelien Jarno | (entry->c << 3) |
|
627 | bc656a29 | Aurelien Jarno | (entry->sh << 1);
|
628 | bc656a29 | Aurelien Jarno | } else {
|
629 | bc656a29 | Aurelien Jarno | /* ITLB Data Array 2 */
|
630 | bc656a29 | Aurelien Jarno | return (entry->tc << 1) | |
631 | bc656a29 | Aurelien Jarno | (entry->sa); |
632 | bc656a29 | Aurelien Jarno | } |
633 | bc656a29 | Aurelien Jarno | } |
634 | bc656a29 | Aurelien Jarno | |
635 | a8170e5e | Avi Kivity | void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
|
636 | 9f97309a | Aurelien Jarno | uint32_t mem_value) |
637 | 9f97309a | Aurelien Jarno | { |
638 | 9f97309a | Aurelien Jarno | int array = (addr & 0x00800000) >> 23; |
639 | 9f97309a | Aurelien Jarno | int index = (addr & 0x00000300) >> 8; |
640 | 9f97309a | Aurelien Jarno | tlb_t * entry = &s->itlb[index]; |
641 | 9f97309a | Aurelien Jarno | |
642 | 9f97309a | Aurelien Jarno | if (array == 0) { |
643 | 9f97309a | Aurelien Jarno | /* ITLB Data Array 1 */
|
644 | 9f97309a | Aurelien Jarno | if (entry->v) {
|
645 | 9f97309a | Aurelien Jarno | /* Overwriting valid entry in utlb. */
|
646 | 9f97309a | Aurelien Jarno | target_ulong address = entry->vpn << 10;
|
647 | 9f97309a | Aurelien Jarno | tlb_flush_page(s, address); |
648 | 9f97309a | Aurelien Jarno | } |
649 | 9f97309a | Aurelien Jarno | entry->ppn = (mem_value & 0x1ffffc00) >> 10; |
650 | 9f97309a | Aurelien Jarno | entry->v = (mem_value & 0x00000100) >> 8; |
651 | 9f97309a | Aurelien Jarno | entry->sz = (mem_value & 0x00000080) >> 6 | |
652 | 9f97309a | Aurelien Jarno | (mem_value & 0x00000010) >> 4; |
653 | 9f97309a | Aurelien Jarno | entry->pr = (mem_value & 0x00000040) >> 5; |
654 | 9f97309a | Aurelien Jarno | entry->c = (mem_value & 0x00000008) >> 3; |
655 | 9f97309a | Aurelien Jarno | entry->sh = (mem_value & 0x00000002) >> 1; |
656 | 9f97309a | Aurelien Jarno | } else {
|
657 | 9f97309a | Aurelien Jarno | /* ITLB Data Array 2 */
|
658 | 9f97309a | Aurelien Jarno | entry->tc = (mem_value & 0x00000008) >> 3; |
659 | 9f97309a | Aurelien Jarno | entry->sa = (mem_value & 0x00000007);
|
660 | 9f97309a | Aurelien Jarno | } |
661 | 9f97309a | Aurelien Jarno | } |
662 | 9f97309a | Aurelien Jarno | |
663 | bc656a29 | Aurelien Jarno | uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s, |
664 | a8170e5e | Avi Kivity | hwaddr addr) |
665 | bc656a29 | Aurelien Jarno | { |
666 | bc656a29 | Aurelien Jarno | int index = (addr & 0x00003f00) >> 8; |
667 | bc656a29 | Aurelien Jarno | tlb_t * entry = &s->utlb[index]; |
668 | bc656a29 | Aurelien Jarno | |
669 | bc656a29 | Aurelien Jarno | increment_urc(s); /* per utlb access */
|
670 | bc656a29 | Aurelien Jarno | |
671 | bc656a29 | Aurelien Jarno | return (entry->vpn << 10) | |
672 | bc656a29 | Aurelien Jarno | (entry->v << 8) |
|
673 | bc656a29 | Aurelien Jarno | (entry->asid); |
674 | bc656a29 | Aurelien Jarno | } |
675 | bc656a29 | Aurelien Jarno | |
676 | a8170e5e | Avi Kivity | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
|
677 | 29e179bc | aurel32 | uint32_t mem_value) |
678 | 29e179bc | aurel32 | { |
679 | 29e179bc | aurel32 | int associate = addr & 0x0000080; |
680 | 29e179bc | aurel32 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
681 | 29e179bc | aurel32 | uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
682 | 29e179bc | aurel32 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
683 | 29e179bc | aurel32 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
684 | eeda6778 | aurel32 | int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0; |
685 | 29e179bc | aurel32 | |
686 | 29e179bc | aurel32 | if (associate) {
|
687 | 29e179bc | aurel32 | int i;
|
688 | 29e179bc | aurel32 | tlb_t * utlb_match_entry = NULL;
|
689 | 29e179bc | aurel32 | int needs_tlb_flush = 0; |
690 | 29e179bc | aurel32 | |
691 | 29e179bc | aurel32 | /* search UTLB */
|
692 | 29e179bc | aurel32 | for (i = 0; i < UTLB_SIZE; i++) { |
693 | 29e179bc | aurel32 | tlb_t * entry = &s->utlb[i]; |
694 | 29e179bc | aurel32 | if (!entry->v)
|
695 | 29e179bc | aurel32 | continue;
|
696 | 29e179bc | aurel32 | |
697 | eeda6778 | aurel32 | if (entry->vpn == vpn
|
698 | eeda6778 | aurel32 | && (!use_asid || entry->asid == asid || entry->sh)) { |
699 | 29e179bc | aurel32 | if (utlb_match_entry) {
|
700 | 29e179bc | aurel32 | /* Multiple TLB Exception */
|
701 | 29e179bc | aurel32 | s->exception_index = 0x140;
|
702 | 29e179bc | aurel32 | s->tea = addr; |
703 | 29e179bc | aurel32 | break;
|
704 | 29e179bc | aurel32 | } |
705 | 29e179bc | aurel32 | if (entry->v && !v)
|
706 | 29e179bc | aurel32 | needs_tlb_flush = 1;
|
707 | 29e179bc | aurel32 | entry->v = v; |
708 | 29e179bc | aurel32 | entry->d = d; |
709 | 29e179bc | aurel32 | utlb_match_entry = entry; |
710 | 29e179bc | aurel32 | } |
711 | 29e179bc | aurel32 | increment_urc(s); /* per utlb access */
|
712 | 29e179bc | aurel32 | } |
713 | 29e179bc | aurel32 | |
714 | 29e179bc | aurel32 | /* search ITLB */
|
715 | 29e179bc | aurel32 | for (i = 0; i < ITLB_SIZE; i++) { |
716 | 29e179bc | aurel32 | tlb_t * entry = &s->itlb[i]; |
717 | eeda6778 | aurel32 | if (entry->vpn == vpn
|
718 | eeda6778 | aurel32 | && (!use_asid || entry->asid == asid || entry->sh)) { |
719 | 29e179bc | aurel32 | if (entry->v && !v)
|
720 | 29e179bc | aurel32 | needs_tlb_flush = 1;
|
721 | 29e179bc | aurel32 | if (utlb_match_entry)
|
722 | 29e179bc | aurel32 | *entry = *utlb_match_entry; |
723 | 29e179bc | aurel32 | else
|
724 | 29e179bc | aurel32 | entry->v = v; |
725 | 29e179bc | aurel32 | break;
|
726 | 29e179bc | aurel32 | } |
727 | 29e179bc | aurel32 | } |
728 | 29e179bc | aurel32 | |
729 | 29e179bc | aurel32 | if (needs_tlb_flush)
|
730 | 29e179bc | aurel32 | tlb_flush_page(s, vpn << 10);
|
731 | 29e179bc | aurel32 | |
732 | 29e179bc | aurel32 | } else {
|
733 | 29e179bc | aurel32 | int index = (addr & 0x00003f00) >> 8; |
734 | 29e179bc | aurel32 | tlb_t * entry = &s->utlb[index]; |
735 | 29e179bc | aurel32 | if (entry->v) {
|
736 | 29e179bc | aurel32 | /* Overwriting valid entry in utlb. */
|
737 | 29e179bc | aurel32 | target_ulong address = entry->vpn << 10;
|
738 | 5a25cc2b | Aurelien Jarno | tlb_flush_page(s, address); |
739 | 29e179bc | aurel32 | } |
740 | 29e179bc | aurel32 | entry->asid = asid; |
741 | 29e179bc | aurel32 | entry->vpn = vpn; |
742 | 29e179bc | aurel32 | entry->d = d; |
743 | 29e179bc | aurel32 | entry->v = v; |
744 | 29e179bc | aurel32 | increment_urc(s); |
745 | 29e179bc | aurel32 | } |
746 | 29e179bc | aurel32 | } |
747 | 29e179bc | aurel32 | |
748 | bc656a29 | Aurelien Jarno | uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, |
749 | a8170e5e | Avi Kivity | hwaddr addr) |
750 | bc656a29 | Aurelien Jarno | { |
751 | bc656a29 | Aurelien Jarno | int array = (addr & 0x00800000) >> 23; |
752 | bc656a29 | Aurelien Jarno | int index = (addr & 0x00003f00) >> 8; |
753 | bc656a29 | Aurelien Jarno | tlb_t * entry = &s->utlb[index]; |
754 | bc656a29 | Aurelien Jarno | |
755 | bc656a29 | Aurelien Jarno | increment_urc(s); /* per utlb access */
|
756 | bc656a29 | Aurelien Jarno | |
757 | bc656a29 | Aurelien Jarno | if (array == 0) { |
758 | bc656a29 | Aurelien Jarno | /* ITLB Data Array 1 */
|
759 | bc656a29 | Aurelien Jarno | return (entry->ppn << 10) | |
760 | bc656a29 | Aurelien Jarno | (entry->v << 8) |
|
761 | bc656a29 | Aurelien Jarno | (entry->pr << 5) |
|
762 | bc656a29 | Aurelien Jarno | ((entry->sz & 1) << 6) | |
763 | bc656a29 | Aurelien Jarno | ((entry->sz & 2) << 4) | |
764 | bc656a29 | Aurelien Jarno | (entry->c << 3) |
|
765 | bc656a29 | Aurelien Jarno | (entry->d << 2) |
|
766 | bc656a29 | Aurelien Jarno | (entry->sh << 1) |
|
767 | bc656a29 | Aurelien Jarno | (entry->wt); |
768 | bc656a29 | Aurelien Jarno | } else {
|
769 | bc656a29 | Aurelien Jarno | /* ITLB Data Array 2 */
|
770 | bc656a29 | Aurelien Jarno | return (entry->tc << 1) | |
771 | bc656a29 | Aurelien Jarno | (entry->sa); |
772 | bc656a29 | Aurelien Jarno | } |
773 | bc656a29 | Aurelien Jarno | } |
774 | bc656a29 | Aurelien Jarno | |
775 | a8170e5e | Avi Kivity | void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
|
776 | 9f97309a | Aurelien Jarno | uint32_t mem_value) |
777 | 9f97309a | Aurelien Jarno | { |
778 | 9f97309a | Aurelien Jarno | int array = (addr & 0x00800000) >> 23; |
779 | 9f97309a | Aurelien Jarno | int index = (addr & 0x00003f00) >> 8; |
780 | 9f97309a | Aurelien Jarno | tlb_t * entry = &s->utlb[index]; |
781 | 9f97309a | Aurelien Jarno | |
782 | 9f97309a | Aurelien Jarno | increment_urc(s); /* per utlb access */
|
783 | 9f97309a | Aurelien Jarno | |
784 | 9f97309a | Aurelien Jarno | if (array == 0) { |
785 | 9f97309a | Aurelien Jarno | /* UTLB Data Array 1 */
|
786 | 9f97309a | Aurelien Jarno | if (entry->v) {
|
787 | 9f97309a | Aurelien Jarno | /* Overwriting valid entry in utlb. */
|
788 | 9f97309a | Aurelien Jarno | target_ulong address = entry->vpn << 10;
|
789 | 9f97309a | Aurelien Jarno | tlb_flush_page(s, address); |
790 | 9f97309a | Aurelien Jarno | } |
791 | 9f97309a | Aurelien Jarno | entry->ppn = (mem_value & 0x1ffffc00) >> 10; |
792 | 9f97309a | Aurelien Jarno | entry->v = (mem_value & 0x00000100) >> 8; |
793 | 9f97309a | Aurelien Jarno | entry->sz = (mem_value & 0x00000080) >> 6 | |
794 | 9f97309a | Aurelien Jarno | (mem_value & 0x00000010) >> 4; |
795 | 9f97309a | Aurelien Jarno | entry->pr = (mem_value & 0x00000060) >> 5; |
796 | 9f97309a | Aurelien Jarno | entry->c = (mem_value & 0x00000008) >> 3; |
797 | 9f97309a | Aurelien Jarno | entry->d = (mem_value & 0x00000004) >> 2; |
798 | 9f97309a | Aurelien Jarno | entry->sh = (mem_value & 0x00000002) >> 1; |
799 | 9f97309a | Aurelien Jarno | entry->wt = (mem_value & 0x00000001);
|
800 | 9f97309a | Aurelien Jarno | } else {
|
801 | 9f97309a | Aurelien Jarno | /* UTLB Data Array 2 */
|
802 | 9f97309a | Aurelien Jarno | entry->tc = (mem_value & 0x00000008) >> 3; |
803 | 9f97309a | Aurelien Jarno | entry->sa = (mem_value & 0x00000007);
|
804 | 9f97309a | Aurelien Jarno | } |
805 | 9f97309a | Aurelien Jarno | } |
806 | 9f97309a | Aurelien Jarno | |
807 | 852d481f | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
808 | 852d481f | edgar_igl | { |
809 | 852d481f | edgar_igl | int n;
|
810 | 852d481f | edgar_igl | int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
811 | 852d481f | edgar_igl | |
812 | 852d481f | edgar_igl | /* check area */
|
813 | 852d481f | edgar_igl | if (env->sr & SR_MD) {
|
814 | 852d481f | edgar_igl | /* For previledged mode, P2 and P4 area is not cachable. */
|
815 | 852d481f | edgar_igl | if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
816 | 852d481f | edgar_igl | return 0; |
817 | 852d481f | edgar_igl | } else {
|
818 | 852d481f | edgar_igl | /* For user mode, only U0 area is cachable. */
|
819 | 852d481f | edgar_igl | if (0x80000000 <= addr) |
820 | 852d481f | edgar_igl | return 0; |
821 | 852d481f | edgar_igl | } |
822 | 852d481f | edgar_igl | |
823 | 852d481f | edgar_igl | /*
|
824 | 852d481f | edgar_igl | * TODO : Evaluate CCR and check if the cache is on or off.
|
825 | 852d481f | edgar_igl | * Now CCR is not in CPUSH4State, but in SH7750State.
|
826 | 4abf79a4 | Dong Xu Wang | * When you move the ccr into CPUSH4State, the code will be
|
827 | 852d481f | edgar_igl | * as follows.
|
828 | 852d481f | edgar_igl | */
|
829 | 852d481f | edgar_igl | #if 0
|
830 | 852d481f | edgar_igl | /* check if operand cache is enabled or not. */
|
831 | 852d481f | edgar_igl | if (!(env->ccr & 1))
|
832 | 852d481f | edgar_igl | return 0;
|
833 | 852d481f | edgar_igl | #endif
|
834 | 852d481f | edgar_igl | |
835 | 852d481f | edgar_igl | /* if MMU is off, no check for TLB. */
|
836 | 852d481f | edgar_igl | if (env->mmucr & MMUCR_AT)
|
837 | 852d481f | edgar_igl | return 1; |
838 | 852d481f | edgar_igl | |
839 | 852d481f | edgar_igl | /* check TLB */
|
840 | 852d481f | edgar_igl | n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); |
841 | 852d481f | edgar_igl | if (n >= 0) |
842 | 852d481f | edgar_igl | return env->itlb[n].c;
|
843 | 852d481f | edgar_igl | |
844 | 852d481f | edgar_igl | n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); |
845 | 852d481f | edgar_igl | if (n >= 0) |
846 | 852d481f | edgar_igl | return env->utlb[n].c;
|
847 | 852d481f | edgar_igl | |
848 | 852d481f | edgar_igl | return 0; |
849 | 852d481f | edgar_igl | } |
850 | 852d481f | edgar_igl | |
851 | 355fb23d | pbrook | #endif |