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# Date Author Comment
9c17d615 12/19/2012 09:32 am Paolo Bonzini

softmmu: move include files to include/sysemu/

Signed-off-by: Paolo Bonzini <>
8555f71d 06/24/2012 02:04 am Blue Swirl

ppc: Move misc helpers from helper.c to misc_helper.c

Move more misc helpers from helper.c to misc_helper.c.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
8cbbe385 06/24/2012 02:04 am Blue Swirl

ppc: Move MMU helpers from helper.c to mmu_helper.c

Move more MMU helpers from helper.c to mmu_helper.c.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
[update to current helper.c state]...
c79c73f6 06/24/2012 02:04 am Blue Swirl

ppc: Move exception helpers from helper.c to excp_helper.c

Move exception helpers from helper.c to excp_helper.c and
make cpu_dump_rfi() static.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>...
4d5ea5e5 06/24/2012 02:04 am Blue Swirl

ppc: Fix coding style in helper.c

helper.c will be spilt by the next patches, fix
style issues before that.

Signed-off-by: Blue Swirl <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Andreas Färber <>
Signed-off-by: Alexander Graf <>
71547a3b 06/21/2012 09:45 pm Blue Swirl

qemu-log: use LOG_UNIMP for some target CPU cases

Use LOG_UNIMP for some target CPU cases.

Signed-off-by: Blue Swirl <>
Acked-by: Alexander Graf <>
b7e516ce 06/05/2012 12:00 am Andreas Färber

Kill off cpu_state_reset()

In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()
was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()
that would operate on QOM objects.

All callers have been updated except for one in target-mips, so drop all...
397b457d 06/05/2012 12:00 am Andreas Färber

target-ppc: Let cpu_ppc_init() return PowerPCCPU

Adapt e500 mpc8544ds machine accordingly.

Turn cpu_init() into a static inline function returning CPUPPCState for
backwards compatibility.

Signed-off-by: Andreas Färber <>
Acked-by: Alexander Graf <>
a7388162 05/01/2012 10:47 pm François Revol

target-ppc: Some support for dumping TLB_EMB TLBs

Add mmubooke_dump_mmu().

TODO: Add printing of individual flags.

Signed-off-by: François Revol <>
[agraf: fix coding style]
Signed-off-by: Alexander Graf <>
a1389542 04/15/2012 06:12 pm Andreas Färber

target-ppc: QOM'ify CPU reset

Move code from cpu_state_reset() into ppc_cpu_reset().
Reorder #include of helper_regs.h to use it in translate_init.c.

Adjust whitespace and add braces.

Signed-off-by: Andreas Färber <>
Acked-by: David Gibson <>
6cca7ad6 04/15/2012 06:11 pm Andreas Färber

target-ppc: Start QOM'ifying CPU init

Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn.

Signed-off-by: Andreas Färber <>
Acked-by: David Gibson <>
1d0cb67d 04/15/2012 06:10 pm Andreas Färber

target-ppc: QOM'ify CPU

Embed CPUPPCState as first member of PowerPCCPU.
Distinguish between "powerpc-cpu", "powerpc64-cpu" and
"embedded-powerpc-cpu".

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <>...
12b1143b 04/15/2012 06:09 pm David Gibson

target-ppc: Add hooks for handling tcg and kvm limitations

On target-ppc, our table of CPU types and features encodes the features as
found on the hardware, regardless of whether these features are actually
usable under TCG or KVM. We already have cases where the information from...
52d631dc 04/15/2012 06:07 pm Mark Cave-Ayland

PPC: Fix TLB invalidation bug within the PPC interrupt handler.

Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB
flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR
bits at the start of the interrupt handler, the logic towards the end of the...
e2fbb432 04/15/2012 06:07 pm Andreas Färber

target-ppc: Drop cpu_ppc_close()

It is unused, so avoid QOM'ifying it unneededly.

Signed-off-by: Andreas Färber <>
Acked-by: David Gibson <>
5cbdb3a3 04/07/2012 05:00 pm Stefan Weil

Replace Qemu by QEMU in comments

The official spelling is QEMU.

Signed-off-by: Stefan Weil <>
Reviewed-by: Andreas Färber <>
[: fixed comment style in hw/sun4m.c]
Signed-off-by: Blue Swirl <>
eb6ea4b2 03/15/2012 02:12 pm Nathan Whitehorn

PPC: Fix large page support in TCG

Fix large page support in TCG. The old code would overwrite the large page
table entry with the fake 4 KB one generated here whenever the ref/change bits
were updated, causing it to point to the wrong area of memory.

Signed-off-by: Nathan Whitehorn <>...
1328c2bf 03/14/2012 11:20 pm Andreas Färber

target-ppc: Don't overuse CPUState

Scripted conversion:
sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc]
sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h

Signed-off-by: Andreas Färber <>
Acked-by: Anthony Liguori <>
1bba0dc9 03/14/2012 11:20 pm Andreas Färber

Rename cpu_reset() to cpu_state_reset()

Frees the identifier cpu_reset for QOM CPUs (manual rename).

Don't hide the parameter type behind explicit casts, use static
functions with strongly typed argument to indirect.

Signed-off-by: Andreas Färber <>...
550a82ec 02/28/2012 11:33 pm Stefan Weil

target-ppc: Clean includes

Remove some include statements which are not needed.

Acked-by: Alexander Graf <>
Signed-off-by: Stefan Weil <>
9d4df9c0 02/11/2012 01:03 pm Blue Swirl

ppc: remove unused variables

Fix this error:
/src/qemu/target-ppc/helper.c: In function 'booke206_tlb_to_page_size':
/src/qemu/target-ppc/helper.c:1296:14: error: variable 'tlbncfg' set but not used [-Werror=unused-but-set-variable]

Tested-by: Andreas Färber <>...
a9abd717 02/02/2012 03:47 am Alexander Graf

PPC: Enable doorbell excp handlers

We already had all the code available to have doorbell exceptions
be handled properly. It was just disabled.

Enable it, so we can rely on it.

Signed-off-by: Alexander Graf <>
3f162d11 02/02/2012 03:47 am Alexander Graf

PPC: booke206: Check for TLB overrun

Our internal helpers to fetch TLB entries were not able to tell us
that an entry doesn't even exist. Pass an error out if we hit such
a case to not accidently pass beyond the TLB array.

Signed-off-by: Alexander Graf <>
21a0b6ed 02/02/2012 03:47 am Alexander Graf

PPC: booke206: move avail check to tlbwe

We can have TLBs that only support a single page size. This is defined
by the absence of the AVAIL flag in TLBnCFG. If this is the case, we
currently write invalid size info into the TLB, but override it on
internal fault....
ffba8786 02/02/2012 03:47 am Alexander Graf

PPC: booke206: allow NULL raddr in ppcmas_tlb_check

We might want to call the tlb check function without actually caring about
the real address resolution. Check if we really should write the value
back.

Signed-off-by: Alexander Graf <>
4e9200a0 01/03/2012 03:49 am Nishanth Aravamudan

PPC: monitor: add ability to dump SLB entries

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the
qemu monitor reports "dump_mmu: unimplemented". However, during
bringup work, it can be quite handy to have the SLB entries, which are
available in the CPUPPCState. This patch adds an implementation of...
e97c3636 10/30/2011 06:11 pm David Gibson

pseries: Support SMT systems for KVM Book3S-HV

Alex Graf has already made qemu support KVM for the pseries machine
when using the Book3S-PR KVM variant (which runs the guest in
usermode, emulating supervisor operations). This code allows gets us
very close to also working with KVM Book3S-HV (using the hypervisor...
bebabbc7 10/06/2011 10:48 am Scott Wood

ppc: booke206: add "info tlb" support

Signed-off-by: Scott Wood <>
Signed-off-by: Alexander Graf <>
2bd9543c 10/06/2011 10:48 am Scott Wood

ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages

This definition is backward compatible with MAV=1.0 as long as
the guest does not set reserved bits in MAS1/MAS4.

Also, fix the shift in booke206_tlb_to_page_size -- it's the base
that should be able to hold a 4G page size, not the shift count....
b2bedb21 09/16/2011 04:25 pm Stefan Weil

Remove blanks before \n in output strings

Those blanks violate the coding conventions, see
scripts/checkpatch.pl.

Blanks missing after colons in the changed lines were added.

This patch does not try to fix tabs, long lines and other
problems in the changed lines, therefore checkpatch.pl reports...
542df9bf 08/23/2011 11:24 pm Alexander Graf

PPC: E500: Add ESR bit definitions

The BookE spec specifies a number of ESR bits. Add defines for them
so we can use them later on.

Reported-by: Jason Wessel <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Edgar E. Iglesias <>
e8906f35 08/23/2011 11:24 pm Alexander Graf

PPC: E500: Set ESR values

When an exception occurs on BookE, we need to set ESR bits to expose
to the guest information on what exactly happened. Add the obvious ones.

Reported-by: Jason Wessel <>
Signed-off-by: Alexander Graf <>...
7267c094 08/21/2011 07:01 am Anthony Liguori

Use glib memory allocation and free functions

qemu_malloc/qemu_free no longer exist after this commit.

Signed-off-by: Anthony Liguori <>
97b348e7 08/07/2011 12:32 pm Blue Swirl

Remove unused is_softmmu parameter from cpu_handle_mmu_fault

Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <>...
d5ab9713 08/05/2011 06:57 pm Jan Kiszka

Avoid allocating TCG resources in non-TCG mode

Do not allocate TCG-only resources like the translation buffer when
running over KVM or XEN. Saves a "few" bytes in the qemu address space
and is also conceptually cleaner.

Signed-off-by: Jan Kiszka <>...
3b886706 07/02/2011 12:12 am Blue Swirl

Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf

  • 'ppc-next' of git://repo.or.cz/qemu/agraf:
    PPC: move TLBs to their own arrays
    PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type
    PPC: E500: Use MAS registers instead of internal TLB representation...
2b41f10e 06/26/2011 09:25 pm Blue Swirl

Remove exec-all.h include directives

Most exec-all.h include directives are now useless, remove them.

Signed-off-by: Blue Swirl <>
1c53accc 06/17/2011 03:58 am Alexander Graf

PPC: move TLBs to their own arrays

Until now, we've created a union over multiple different TLB types and
allocated that union. While it's a waste of memory (and cache) to allocate
TLB information for a TLB type with much information when you only need
little, it also inflicts another issue....
d1e256fe 06/17/2011 03:58 am Alexander Graf

PPC: E500: Use MAS registers instead of internal TLB representation

The natural format for e500 cores to do TLB manipulation with are the MAS
registers. Instead of converting them into some internal representation
and back again when the guest reads them, we can just keep the data...
826e7b82 06/17/2011 03:58 am Hervé Poussineau

target-ppc: Handle memory-forced I/O controller access

On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07F
is special-cased as memory-forced I/O controller access. It is supposed
to be checked immediately if T=1, bypassing all protection mechanisms...
9bf0960a 06/08/2011 11:04 am Alexandre Raymond

Fix compilation warning due to missing header for sigaction (followup)

This patch removes all references to signal.h when qemu-common.h is included
as they become redundant.

Signed-off-by: Alexandre Raymond <>
Signed-off-by: Stefan Hajnoczi <>
decb4714 05/20/2011 06:56 pm David Gibson

Fix a bug in mtsr/mtsrin emulation on ppc64

Early ppc64 CPUs include a hack to partially simulate the ppc32 segment
registers, by translating writes to them into writes to the SLB. This is
not used by any current Linux kernel, but it is used by the openbios used...
01662f3e 05/12/2011 01:24 am Alexander Graf

PPC: Implement e500 (FSL) MMU

Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.

This patch adds support for the FSL style MMU.

Signed-off-by: Alexander Graf <>
8500e3a9 04/01/2011 07:34 pm David Gibson

Clean up slb_lookup() function

The slb_lookup() function, used in the ppc translation path returns a
number of slb entry fields in reference parameters. However, only one
of the two callers of slb_lookup() actually wants this information.

This patch, therefore, makes slb_lookup() return a simple pointer to the...
bb593904 04/01/2011 07:34 pm David Gibson

Parse SDR1 on mtspr instead of at translate time

On ppc machines with hash table MMUs, the special purpose register SDR1
contains both the base address of the encoded size (hashed) page tables.

At present, we interpret the SDR1 value within the address translation...
fda6a0ec 04/01/2011 07:34 pm David Gibson

Use "hash" more consistently in ppc mmu code

Currently, get_segment() has a variable called hash. However it doesn't
(quite) get the hash value for the ppc hashed page table. Instead it
gets the hash shifted - effectively the offset of the hash bucket within...
256cebe5 04/01/2011 07:34 pm David Gibson

Better factor the ppc hash translation path

Currently the path handling hash page table translation in get_segment()
has a mix of common and 32 or 64 bit specific code. However the
division is not done terribly well which results in a lot of messy code
flipping between common and divided paths....
cdaee006 04/01/2011 07:34 pm David Gibson

Support 1T segments on ppc

Traditionally, the "segments" used for the two-stage translation used on
powerpc MMUs were 256MB in size. This was the only option on all hash
page table based 32-bit powerpc cpus, and on the earlier 64-bit hash page
table based cpus. However, newer 64-bit cpus also permit 1TB segments...
9d52e907 04/01/2011 07:34 pm David Gibson

Add POWER7 support for ppc

This adds emulation support for the recent POWER7 cpu to qemu. It's far
from perfect - it's missing a number of POWER7 features so far, including
any support for VSX or decimal floating point instructions. However, it's
close enough to boot a kernel with the POWER7 PVR....
f43e3525 04/01/2011 07:34 pm David Gibson

Virtual hash page table handling on pSeries machine

On pSeries logical partitions, excepting the old POWER4-style full system
partitions, the guest does not have direct access to the hardware page
table. Instead, the pagetable exists in hypervisor memory, and the guest...
81762d6d 04/01/2011 07:34 pm David Gibson

Clean up PowerPC SLB handling code

Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'. While the layout in these fields does match the
description of the SLB in the architecture document, it is not...
d569956e 04/01/2011 07:34 pm David Gibson

Add a hook to allow hypercalls to be emulated on PowerPC

PowerPC and POWER chips since the POWER4 and 970 have a special
hypervisor mode, and a corresponding form of the system call
instruction which traps to the hypervisor.

qemu currently has stub implementations of hypervisor mode. That...
efdef95f 04/01/2011 07:34 pm David Gibson

Implement PowerPC slbmfee and slbmfev instructions

For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer. Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions...
ae0bfb79 10/13/2010 09:38 pm Blue Swirl

ppc: remove video.x

Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.

Remove video.x MoL hacks.

Signed-off-by: Alexander Graf <>
Signed-off-by: Blue Swirl <>
999fa40e 10/05/2010 07:38 pm John Clark

ppc: Minor 40x MMU fixes

  • Fix swapped reading of tlblo/hi.
  • Fix tlb exec permissions

Signed-off-by: John Clark <>
Signed-off-by: Alexander Graf <>
Signed-off-by: Edgar E. Iglesias <>
a586e548 09/24/2010 11:01 pm Edgar E. Iglesias

powerpc: Improve emulation of the BookE MMU

Improve the emulation of the BookE MMU to be able to boot linux
on virtex5 boards.

Signed-off-by: Edgar E. Iglesias <>
41557447 09/15/2010 05:18 pm Alexander Graf

PPC: Redesign interrupt trigger path

According to the Book3S spec, the interrupt context starts with an MSR
value that is rather simple. If we leave out the HV case, it's almost
always 0.

To reflect this, let's redesign the way that MSR value gets calculated....
24e0e38b 09/11/2010 03:29 pm Edgar E. Iglesias

powerpc: Avoid TLB related log spamming

Invalid TLB entries are normal and should not spam the log.

Signed-off-by: Edgar E. Iglesias <>
0f89cc7b 05/31/2010 08:18 pm Thomas Monjalon

target-ppc: remove useless line

This line was a bit clear.
The next lines set or reset this bit (LE) depending of another bit (ILE).
So the first line is useless.

Signed-off-by: Thomas Monjalon <>
Signed-off-by: Aurelien Jarno <>
c3d420ea 05/31/2010 08:17 pm Thomas Monjalon

target-ppc: fix RFI by clearing some bits of MSR

Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors
because some interrupt specifics bits of SRR1 are copied to MSR.

SRR1 is a save of MSR during interrupt.
During RFI, MSR must be restored from SRR1....
05f92404 04/25/2010 11:32 pm Blue Swirl

ppc: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>
d4c430a8 03/17/2010 04:44 am Paul Brook

Large page TLB flush

QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate...
4fcc562b 03/12/2010 08:34 pm Paul Brook

Remove cpu_get_phys_page_debug from userspace emulation

cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <>
b2eca445 02/14/2010 04:10 pm Alexander Graf

PPC: Fix large pages

We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviously
that breaks, so let's just ignore 1TB SLB entries for now and instead do
16MB pages correctly.

This fixes PPC64 Linux boot with -m above 256.

Signed-off-by: Alexander Graf <>...
dcbc9a70 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct ESR for zone protection faults.

Raise the zone protection fault in ESR for TLB faults caused by
zone protection bits.

Signed-off-by: Edgar E. Iglesias <>
ec5c3e48 01/14/2010 03:42 pm Edgar E. Iglesias

ppc-40x: Correct decoding of zone protection bits.

The 40x MMU has 15 zones in the ZPR register.

Signed-off-by: Edgar E. Iglesias <>
b55a37c9 11/07/2009 12:37 pm Blue Swirl

user: move CPU reset call to main.c for x86/PPC/Sparc

Signed-off-by: Blue Swirl <>
d84bda46 11/07/2009 12:36 pm Blue Swirl

PPC: rename cpu_ppc_reset to cpu_reset for consistency

Signed-off-by: Blue Swirl <>
e4394131 11/07/2009 11:32 am Blue Swirl

PPC: remove unneeded calls to device reset

Signed-off-by: Blue Swirl <>
c227f099 10/02/2009 12:12 am Anthony Liguori

Revert "Get rid of _t suffix"

In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem. Something
like this must be presented on the list first so people can provide input...
99a0949b 10/01/2009 09:45 pm malc

Get rid of _t suffix

Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <>
b11ebf64 08/16/2009 02:54 pm Blue Swirl

Replace REGX with PRIx64

Signed-off-by: Blue Swirl <>
90e189ec 08/16/2009 02:13 pm Blue Swirl

Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx

Signed-off-by: Blue Swirl <>
636aa200 08/16/2009 12:06 pm Blue Swirl

Replace always_inline with inline

We define inline as always_inline.

Signed-off-by: Blue Swirl <>
18b21a2f 08/03/2009 07:33 pm Nathan Froyd

target-ppc: retain l{w,d}arx loaded value

We do this so we can check on the corresponding stc{w,d}x. whether the
value has changed. It's a poor man's form of implementing atomic
operations and is valid only for NPTL usermode Linux emulation.

Signed-off-by: Nathan Froyd <>...
0bf9e31a 07/20/2009 08:19 pm Blue Swirl

Fix most warnings (errors with -Werror) when debugging is enabled

I used the following command to enable debugging:
perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*

Signed-off-by: Blue Swirl <>
8167ee88 07/16/2009 11:47 pm Blue Swirl

Update to a hopefully more future proof FSF address

Signed-off-by: Blue Swirl <>
55616505 05/13/2009 10:54 pm Paul Brook

Include assert.h from qemu-common.h

Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks

Signed-off-by: Paul Brook <>
fc1c67bc 04/28/2009 09:00 pm Blue Swirl

Fix PPC reset
0bf46a40 04/24/2009 09:03 pm aliguori

qemu: introduce qemu_init_vcpu (Marcelo Tosatti)

Signed-off-by: Marcelo Tosatti <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
bf1752ef 03/29/2009 04:36 pm aurel32

target-ppc: Explain why the whole TLB is flushed on SR write

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
94855937 03/07/2009 10:58 pm blueswir1

Disable BAT for 970

The 970 doesn't know BAT, so let's not search BATs there.
This was only in as a hack for OpenHackWare so it would
work on PPC64.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
8eee0af9 03/07/2009 10:57 pm blueswir1

Keep SLB in-CPU

Real 970 CPUs have the SLB not memory backed, but inside the CPU.
This breaks bridge mode for 970 for now, but at least keeps us from
overwriting physical addresses 0x0 - 0x300, rendering our interrupt
handlers useless.

I put in a stub for bridge mode operation that could be enabled...
29c8ca6f 03/07/2009 10:57 pm blueswir1

Fix NX bit

ctx->nx only got ORed, but never reset. So when one page in the
lifetime of the VM was ever NX, all later pages were too.

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
6ce0ca12 03/07/2009 10:54 pm blueswir1

Enable 64bit mode on interrupts

Real 970s enable MSR_SF on all interrupts. The current code didn't do
this until now, so let's activate it!

Signed-off-by: Alexander Graf <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
5b5aba4f 03/07/2009 10:51 pm blueswir1

Implement large pages

The current SLB/PTE code does not support large pages, which are
required by Linux, as it boots up with the kernel regions up as large.

This patch implements large page support, so we can run Linux.

Signed-off-by: Alexander Graf <>...
f6b868fc 03/07/2009 10:50 pm blueswir1

Implement slbmte

In order to modify SLB entries on recent PPC64 machines, the slbmte
instruction is used.

This patch implements the slbmte instruction and makes the "bridge"
mode code use the slb set functions, so we can move the SLB into
the CPU struct later....
07c485ce 02/21/2009 07:29 pm blueswir1

Turn MMU off on reset

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6637 c046a42c-6fe2-441c-8c8c-71466251a162
0d0266a5 02/06/2009 12:06 am aliguori

targets: remove error handling from qemu_malloc() callers (Avi Kivity)

Signed-off-by: Avi Kivity <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
eca1bdf4 01/26/2009 09:54 pm aliguori

Log reset events (Jan Kiszka)

Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <>...
93fcfe39 01/16/2009 12:34 am aliguori

Convert references to logfile/loglevel to use qemu_log*() macros

This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <>
Signed-off-by: Anthony Liguori <>...
d12d51d5 01/15/2009 11:48 pm aliguori

Clean up debugging code #ifdefs (Eduardo Habkost)

Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later...
da07cf59 01/15/2009 11:24 pm aliguori

powerpc/kvm: enable POWERPC_MMU_BOOKE_FSL when kvm is enabled (Liu Yu)

Signed-off-by: Liu Yu <>
Acked-by: Hollis Blanchard <>
Signed-off-by: Anthony Liguori <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6329 c046a42c-6fe2-441c-8c8c-71466251a162
fad6cb1a 01/05/2009 12:05 am aurel32

Update FSF address in GPL/LGPL boilerplate

The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <>
Signed-off-by: Aurelien Jarno <>...
d76d1650 12/16/2008 12:43 pm aurel32

target-ppc: Enable KVM for ppcemb.

Implement hooks called by generic KVM code.

Also add code that will copy the host's CPU and timebase frequencies to the
guest, which is necessary on KVM because the guest can directly access the
timebase.

Signed-off-by: Hollis Blanchard <>...
93220573 12/12/2008 12:42 am aurel32

target-ppc: remove remaining warnings

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
94fa46e2 12/12/2008 12:42 am aurel32

target-ppc: remove unneeded include

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5990 c046a42c-6fe2-441c-8c8c-71466251a162
e06fcd75 12/12/2008 12:42 am aurel32

target-ppc: rework exception code

... also remove two warnings.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
4c2ab988 12/10/2008 05:02 pm aurel32

target-ppc: enable SPE and Altivec in user mode

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5965 c046a42c-6fe2-441c-8c8c-71466251a162
fe463b7d 12/10/2008 05:02 pm aurel32

target-ppc: initialize MSR appropriately in user-mode

Mask the initial MSR with the mask from the PowerPC CPU definition.

Noticed by Nathan Froyd.

Signed-off-by: Aurelien Jarno <>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5964 c046a42c-6fe2-441c-8c8c-71466251a162