Archipelago » qemu

/*

 *  MIPS32 emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2004-2005 Jocelyn Mayer

 *  Copyright (c) 2006 Marius Groeger (FPU operations)

 *  Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)

 *  Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-common.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

//#define MIPS_DEBUG_DISAS

//#define MIPS_DEBUG_SIGN_EXTENSIONS

/* MIPS major opcodes */

#define MASK_OP_MAJOR(op)  (op & (0x3F << 26))

enum {

    /* indirect opcode tables */

    OPC_SPECIAL  = (0x00 << 26),

    OPC_REGIMM   = (0x01 << 26),

    OPC_CP0      = (0x10 << 26),

    OPC_CP1      = (0x11 << 26),

    OPC_CP2      = (0x12 << 26),

    OPC_CP3      = (0x13 << 26),

    OPC_SPECIAL2 = (0x1C << 26),

    OPC_SPECIAL3 = (0x1F << 26),

    /* arithmetic with immediate */

    OPC_ADDI     = (0x08 << 26),

    OPC_ADDIU    = (0x09 << 26),

    OPC_SLTI     = (0x0A << 26),

    OPC_SLTIU    = (0x0B << 26),

    /* logic with immediate */

    OPC_ANDI     = (0x0C << 26),

    OPC_ORI      = (0x0D << 26),

    OPC_XORI     = (0x0E << 26),

    OPC_LUI      = (0x0F << 26),

    /* arithmetic with immediate */

    OPC_DADDI    = (0x18 << 26),

    OPC_DADDIU   = (0x19 << 26),

    /* Jump and branches */

    OPC_J        = (0x02 << 26),

    OPC_JAL      = (0x03 << 26),

    OPC_JALS     = OPC_JAL | 0x5,

    OPC_BEQ      = (0x04 << 26),  /* Unconditional if rs = rt = 0 (B) */

    OPC_BEQL     = (0x14 << 26),

    OPC_BNE      = (0x05 << 26),

    OPC_BNEL     = (0x15 << 26),

    OPC_BLEZ     = (0x06 << 26),

    OPC_BLEZL    = (0x16 << 26),

    OPC_BGTZ     = (0x07 << 26),

    OPC_BGTZL    = (0x17 << 26),

    OPC_JALX     = (0x1D << 26),  /* MIPS 16 only */

    OPC_JALXS    = OPC_JALX | 0x5,

    /* Load and stores */

    OPC_LDL      = (0x1A << 26),

    OPC_LDR      = (0x1B << 26),

    OPC_LB       = (0x20 << 26),

    OPC_LH       = (0x21 << 26),

    OPC_LWL      = (0x22 << 26),

    OPC_LW       = (0x23 << 26),

    OPC_LWPC     = OPC_LW | 0x5,

    OPC_LBU      = (0x24 << 26),

    OPC_LHU      = (0x25 << 26),

    OPC_LWR      = (0x26 << 26),

    OPC_LWU      = (0x27 << 26),

    OPC_SB       = (0x28 << 26),

    OPC_SH       = (0x29 << 26),

    OPC_SWL      = (0x2A << 26),

    OPC_SW       = (0x2B << 26),

    OPC_SDL      = (0x2C << 26),

    OPC_SDR      = (0x2D << 26),

    OPC_SWR      = (0x2E << 26),

    OPC_LL       = (0x30 << 26),

    OPC_LLD      = (0x34 << 26),

    OPC_LD       = (0x37 << 26),

    OPC_LDPC     = OPC_LD | 0x5,

    OPC_SC       = (0x38 << 26),

    OPC_SCD      = (0x3C << 26),

    OPC_SD       = (0x3F << 26),

    /* Floating point load/store */

    OPC_LWC1     = (0x31 << 26),

    OPC_LWC2     = (0x32 << 26),

    OPC_LDC1     = (0x35 << 26),

    OPC_LDC2     = (0x36 << 26),

    OPC_SWC1     = (0x39 << 26),

    OPC_SWC2     = (0x3A << 26),

    OPC_SDC1     = (0x3D << 26),

    OPC_SDC2     = (0x3E << 26),

    /* MDMX ASE specific */

    OPC_MDMX     = (0x1E << 26),

    /* Cache and prefetch */

    OPC_CACHE    = (0x2F << 26),

    OPC_PREF     = (0x33 << 26),

    /* Reserved major opcode */

    OPC_MAJOR3B_RESERVED = (0x3B << 26),

};

/* MIPS special opcodes */

#define MASK_SPECIAL(op)   MASK_OP_MAJOR(op) | (op & 0x3F)

enum {

    /* Shifts */

    OPC_SLL      = 0x00 | OPC_SPECIAL,

    /* NOP is SLL r0, r0, 0   */

    /* SSNOP is SLL r0, r0, 1 */

    /* EHB is SLL r0, r0, 3 */

    OPC_SRL      = 0x02 | OPC_SPECIAL, /* also ROTR */

    OPC_ROTR     = OPC_SRL | (1 << 21),

    OPC_SRA      = 0x03 | OPC_SPECIAL,

    OPC_SLLV     = 0x04 | OPC_SPECIAL,

    OPC_SRLV     = 0x06 | OPC_SPECIAL, /* also ROTRV */

    OPC_ROTRV    = OPC_SRLV | (1 << 6),

    OPC_SRAV     = 0x07 | OPC_SPECIAL,

    OPC_DSLLV    = 0x14 | OPC_SPECIAL,

    OPC_DSRLV    = 0x16 | OPC_SPECIAL, /* also DROTRV */

    OPC_DROTRV   = OPC_DSRLV | (1 << 6),

    OPC_DSRAV    = 0x17 | OPC_SPECIAL,

    OPC_DSLL     = 0x38 | OPC_SPECIAL,

    OPC_DSRL     = 0x3A | OPC_SPECIAL, /* also DROTR */

    OPC_DROTR    = OPC_DSRL | (1 << 21),

    OPC_DSRA     = 0x3B | OPC_SPECIAL,

    OPC_DSLL32   = 0x3C | OPC_SPECIAL,

    OPC_DSRL32   = 0x3E | OPC_SPECIAL, /* also DROTR32 */

    OPC_DROTR32  = OPC_DSRL32 | (1 << 21),

    OPC_DSRA32   = 0x3F | OPC_SPECIAL,

    /* Multiplication / division */

    OPC_MULT     = 0x18 | OPC_SPECIAL,

    OPC_MULTU    = 0x19 | OPC_SPECIAL,

    OPC_DIV      = 0x1A | OPC_SPECIAL,

    OPC_DIVU     = 0x1B | OPC_SPECIAL,

    OPC_DMULT    = 0x1C | OPC_SPECIAL,

    OPC_DMULTU   = 0x1D | OPC_SPECIAL,

    OPC_DDIV     = 0x1E | OPC_SPECIAL,

    OPC_DDIVU    = 0x1F | OPC_SPECIAL,

    /* 2 registers arithmetic / logic */

    OPC_ADD      = 0x20 | OPC_SPECIAL,

    OPC_ADDU     = 0x21 | OPC_SPECIAL,

    OPC_SUB      = 0x22 | OPC_SPECIAL,

    OPC_SUBU     = 0x23 | OPC_SPECIAL,

    OPC_AND      = 0x24 | OPC_SPECIAL,

    OPC_OR       = 0x25 | OPC_SPECIAL,

    OPC_XOR      = 0x26 | OPC_SPECIAL,

    OPC_NOR      = 0x27 | OPC_SPECIAL,

    OPC_SLT      = 0x2A | OPC_SPECIAL,

    OPC_SLTU     = 0x2B | OPC_SPECIAL,

    OPC_DADD     = 0x2C | OPC_SPECIAL,

    OPC_DADDU    = 0x2D | OPC_SPECIAL,

    OPC_DSUB     = 0x2E | OPC_SPECIAL,

    OPC_DSUBU    = 0x2F | OPC_SPECIAL,

    /* Jumps */

    OPC_JR       = 0x08 | OPC_SPECIAL, /* Also JR.HB */

    OPC_JALR     = 0x09 | OPC_SPECIAL, /* Also JALR.HB */

    OPC_JALRC    = OPC_JALR | (0x5 << 6),

    OPC_JALRS    = 0x10 | OPC_SPECIAL | (0x5 << 6),

    /* Traps */

    OPC_TGE      = 0x30 | OPC_SPECIAL,

    OPC_TGEU     = 0x31 | OPC_SPECIAL,

    OPC_TLT      = 0x32 | OPC_SPECIAL,

    OPC_TLTU     = 0x33 | OPC_SPECIAL,

    OPC_TEQ      = 0x34 | OPC_SPECIAL,

    OPC_TNE      = 0x36 | OPC_SPECIAL,

    /* HI / LO registers load & stores */

    OPC_MFHI     = 0x10 | OPC_SPECIAL,

    OPC_MTHI     = 0x11 | OPC_SPECIAL,

    OPC_MFLO     = 0x12 | OPC_SPECIAL,

    OPC_MTLO     = 0x13 | OPC_SPECIAL,

    /* Conditional moves */

    OPC_MOVZ     = 0x0A | OPC_SPECIAL,

    OPC_MOVN     = 0x0B | OPC_SPECIAL,

    OPC_MOVCI    = 0x01 | OPC_SPECIAL,

    /* Special */

    OPC_PMON     = 0x05 | OPC_SPECIAL, /* unofficial */

    OPC_SYSCALL  = 0x0C | OPC_SPECIAL,

    OPC_BREAK    = 0x0D | OPC_SPECIAL,

    OPC_SPIM     = 0x0E | OPC_SPECIAL, /* unofficial */

    OPC_SYNC     = 0x0F | OPC_SPECIAL,

    OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL,

    OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,

    OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,

    OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL,

    OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL,

    OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,

    OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,

};

/* Multiplication variants of the vr54xx. */

#define MASK_MUL_VR54XX(op)   MASK_SPECIAL(op) | (op & (0x1F << 6))

enum {

    OPC_VR54XX_MULS    = (0x03 << 6) | OPC_MULT,

    OPC_VR54XX_MULSU   = (0x03 << 6) | OPC_MULTU,

    OPC_VR54XX_MACC    = (0x05 << 6) | OPC_MULT,

    OPC_VR54XX_MACCU   = (0x05 << 6) | OPC_MULTU,

    OPC_VR54XX_MSAC    = (0x07 << 6) | OPC_MULT,

    OPC_VR54XX_MSACU   = (0x07 << 6) | OPC_MULTU,

    OPC_VR54XX_MULHI   = (0x09 << 6) | OPC_MULT,

    OPC_VR54XX_MULHIU  = (0x09 << 6) | OPC_MULTU,

    OPC_VR54XX_MULSHI  = (0x0B << 6) | OPC_MULT,

    OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU,

    OPC_VR54XX_MACCHI  = (0x0D << 6) | OPC_MULT,

    OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU,

    OPC_VR54XX_MSACHI  = (0x0F << 6) | OPC_MULT,

    OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU,

};

/* REGIMM (rt field) opcodes */

#define MASK_REGIMM(op)    MASK_OP_MAJOR(op) | (op & (0x1F << 16))

enum {

    OPC_BLTZ     = (0x00 << 16) | OPC_REGIMM,

    OPC_BLTZL    = (0x02 << 16) | OPC_REGIMM,

    OPC_BGEZ     = (0x01 << 16) | OPC_REGIMM,

    OPC_BGEZL    = (0x03 << 16) | OPC_REGIMM,

    OPC_BLTZAL   = (0x10 << 16) | OPC_REGIMM,

    OPC_BLTZALS  = OPC_BLTZAL | 0x5, /* microMIPS */

    OPC_BLTZALL  = (0x12 << 16) | OPC_REGIMM,

    OPC_BGEZAL   = (0x11 << 16) | OPC_REGIMM,

    OPC_BGEZALS  = OPC_BGEZAL | 0x5, /* microMIPS */

    OPC_BGEZALL  = (0x13 << 16) | OPC_REGIMM,

    OPC_TGEI     = (0x08 << 16) | OPC_REGIMM,

    OPC_TGEIU    = (0x09 << 16) | OPC_REGIMM,

    OPC_TLTI     = (0x0A << 16) | OPC_REGIMM,

    OPC_TLTIU    = (0x0B << 16) | OPC_REGIMM,

    OPC_TEQI     = (0x0C << 16) | OPC_REGIMM,

    OPC_TNEI     = (0x0E << 16) | OPC_REGIMM,

    OPC_SYNCI    = (0x1F << 16) | OPC_REGIMM,

};

/* Special2 opcodes */

#define MASK_SPECIAL2(op)  MASK_OP_MAJOR(op) | (op & 0x3F)

enum {

    /* Multiply & xxx operations */

    OPC_MADD     = 0x00 | OPC_SPECIAL2,

    OPC_MADDU    = 0x01 | OPC_SPECIAL2,

    OPC_MUL      = 0x02 | OPC_SPECIAL2,

    OPC_MSUB     = 0x04 | OPC_SPECIAL2,

    OPC_MSUBU    = 0x05 | OPC_SPECIAL2,

    /* Loongson 2F */

    OPC_MULT_G_2F   = 0x10 | OPC_SPECIAL2,

    OPC_DMULT_G_2F  = 0x11 | OPC_SPECIAL2,

    OPC_MULTU_G_2F  = 0x12 | OPC_SPECIAL2,

    OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,

    OPC_DIV_G_2F    = 0x14 | OPC_SPECIAL2,

    OPC_DDIV_G_2F   = 0x15 | OPC_SPECIAL2,

    OPC_DIVU_G_2F   = 0x16 | OPC_SPECIAL2,

    OPC_DDIVU_G_2F  = 0x17 | OPC_SPECIAL2,

    OPC_MOD_G_2F    = 0x1c | OPC_SPECIAL2,

    OPC_DMOD_G_2F   = 0x1d | OPC_SPECIAL2,

    OPC_MODU_G_2F   = 0x1e | OPC_SPECIAL2,

    OPC_DMODU_G_2F  = 0x1f | OPC_SPECIAL2,

    /* Misc */

    OPC_CLZ      = 0x20 | OPC_SPECIAL2,

    OPC_CLO      = 0x21 | OPC_SPECIAL2,

    OPC_DCLZ     = 0x24 | OPC_SPECIAL2,

    OPC_DCLO     = 0x25 | OPC_SPECIAL2,

    /* Special */

    OPC_SDBBP    = 0x3F | OPC_SPECIAL2,

};

/* Special3 opcodes */

#define MASK_SPECIAL3(op)  MASK_OP_MAJOR(op) | (op & 0x3F)

enum {

    OPC_EXT      = 0x00 | OPC_SPECIAL3,

    OPC_DEXTM    = 0x01 | OPC_SPECIAL3,

    OPC_DEXTU    = 0x02 | OPC_SPECIAL3,

    OPC_DEXT     = 0x03 | OPC_SPECIAL3,

    OPC_INS      = 0x04 | OPC_SPECIAL3,

    OPC_DINSM    = 0x05 | OPC_SPECIAL3,

    OPC_DINSU    = 0x06 | OPC_SPECIAL3,

    OPC_DINS     = 0x07 | OPC_SPECIAL3,

    OPC_FORK     = 0x08 | OPC_SPECIAL3,

    OPC_YIELD    = 0x09 | OPC_SPECIAL3,

    OPC_BSHFL    = 0x20 | OPC_SPECIAL3,

    OPC_DBSHFL   = 0x24 | OPC_SPECIAL3,

    OPC_RDHWR    = 0x3B | OPC_SPECIAL3,

    /* Loongson 2E */

    OPC_MULT_G_2E   = 0x18 | OPC_SPECIAL3,

    OPC_MULTU_G_2E  = 0x19 | OPC_SPECIAL3,

    OPC_DIV_G_2E    = 0x1A | OPC_SPECIAL3,

    OPC_DIVU_G_2E   = 0x1B | OPC_SPECIAL3,

    OPC_DMULT_G_2E  = 0x1C | OPC_SPECIAL3,

    OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,

    OPC_DDIV_G_2E   = 0x1E | OPC_SPECIAL3,

    OPC_DDIVU_G_2E  = 0x1F | OPC_SPECIAL3,

    OPC_MOD_G_2E    = 0x22 | OPC_SPECIAL3,

    OPC_MODU_G_2E   = 0x23 | OPC_SPECIAL3,

    OPC_DMOD_G_2E   = 0x26 | OPC_SPECIAL3,

    OPC_DMODU_G_2E  = 0x27 | OPC_SPECIAL3,

};

/* BSHFL opcodes */

#define MASK_BSHFL(op)     MASK_SPECIAL3(op) | (op & (0x1F << 6))

enum {

    OPC_WSBH     = (0x02 << 6) | OPC_BSHFL,

    OPC_SEB      = (0x10 << 6) | OPC_BSHFL,

    OPC_SEH      = (0x18 << 6) | OPC_BSHFL,

};

/* DBSHFL opcodes */

#define MASK_DBSHFL(op)    MASK_SPECIAL3(op) | (op & (0x1F << 6))

enum {

    OPC_DSBH     = (0x02 << 6) | OPC_DBSHFL,

    OPC_DSHD     = (0x05 << 6) | OPC_DBSHFL,

};

/* Coprocessor 0 (rs field) */

#define MASK_CP0(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))

enum {

    OPC_MFC0     = (0x00 << 21) | OPC_CP0,

    OPC_DMFC0    = (0x01 << 21) | OPC_CP0,

    OPC_MTC0     = (0x04 << 21) | OPC_CP0,

    OPC_DMTC0    = (0x05 << 21) | OPC_CP0,

    OPC_MFTR     = (0x08 << 21) | OPC_CP0,

    OPC_RDPGPR   = (0x0A << 21) | OPC_CP0,

    OPC_MFMC0    = (0x0B << 21) | OPC_CP0,

    OPC_MTTR     = (0x0C << 21) | OPC_CP0,

    OPC_WRPGPR   = (0x0E << 21) | OPC_CP0,

    OPC_C0       = (0x10 << 21) | OPC_CP0,

    OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,

    OPC_C0_LAST  = (0x1F << 21) | OPC_CP0,

};

/* MFMC0 opcodes */

#define MASK_MFMC0(op)     MASK_CP0(op) | (op & 0xFFFF)

enum {

    OPC_DMT      = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,

    OPC_EMT      = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,

    OPC_DVPE     = 0x01 | (0 << 5) | OPC_MFMC0,

    OPC_EVPE     = 0x01 | (1 << 5) | OPC_MFMC0,

    OPC_DI       = (0 << 5) | (0x0C << 11) | OPC_MFMC0,

    OPC_EI       = (1 << 5) | (0x0C << 11) | OPC_MFMC0,

};

/* Coprocessor 0 (with rs == C0) */

#define MASK_C0(op)        MASK_CP0(op) | (op & 0x3F)

enum {

    OPC_TLBR     = 0x01 | OPC_C0,

    OPC_TLBWI    = 0x02 | OPC_C0,

    OPC_TLBWR    = 0x06 | OPC_C0,

    OPC_TLBP     = 0x08 | OPC_C0,

    OPC_RFE      = 0x10 | OPC_C0,

    OPC_ERET     = 0x18 | OPC_C0,

    OPC_DERET    = 0x1F | OPC_C0,

    OPC_WAIT     = 0x20 | OPC_C0,

};

/* Coprocessor 1 (rs field) */

#define MASK_CP1(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))

/* Values for the fmt field in FP instructions */

enum {

    /* 0 - 15 are reserved */

    FMT_S = 16,          /* single fp */

    FMT_D = 17,          /* double fp */

    FMT_E = 18,          /* extended fp */

    FMT_Q = 19,          /* quad fp */

    FMT_W = 20,          /* 32-bit fixed */

    FMT_L = 21,          /* 64-bit fixed */

    FMT_PS = 22,         /* paired single fp */

    /* 23 - 31 are reserved */

};

enum {

    OPC_MFC1     = (0x00 << 21) | OPC_CP1,

    OPC_DMFC1    = (0x01 << 21) | OPC_CP1,

    OPC_CFC1     = (0x02 << 21) | OPC_CP1,

    OPC_MFHC1    = (0x03 << 21) | OPC_CP1,

    OPC_MTC1     = (0x04 << 21) | OPC_CP1,

    OPC_DMTC1    = (0x05 << 21) | OPC_CP1,

    OPC_CTC1     = (0x06 << 21) | OPC_CP1,

    OPC_MTHC1    = (0x07 << 21) | OPC_CP1,

    OPC_BC1      = (0x08 << 21) | OPC_CP1, /* bc */

    OPC_BC1ANY2  = (0x09 << 21) | OPC_CP1,

    OPC_BC1ANY4  = (0x0A << 21) | OPC_CP1,

    OPC_S_FMT    = (FMT_S << 21) | OPC_CP1,

    OPC_D_FMT    = (FMT_D << 21) | OPC_CP1,

    OPC_E_FMT    = (FMT_E << 21) | OPC_CP1,

    OPC_Q_FMT    = (FMT_Q << 21) | OPC_CP1,

    OPC_W_FMT    = (FMT_W << 21) | OPC_CP1,

    OPC_L_FMT    = (FMT_L << 21) | OPC_CP1,

    OPC_PS_FMT   = (FMT_PS << 21) | OPC_CP1,

};

#define MASK_CP1_FUNC(op)       MASK_CP1(op) | (op & 0x3F)

#define MASK_BC1(op)            MASK_CP1(op) | (op & (0x3 << 16))

enum {

    OPC_BC1F     = (0x00 << 16) | OPC_BC1,

    OPC_BC1T     = (0x01 << 16) | OPC_BC1,

    OPC_BC1FL    = (0x02 << 16) | OPC_BC1,

    OPC_BC1TL    = (0x03 << 16) | OPC_BC1,

};

enum {

    OPC_BC1FANY2     = (0x00 << 16) | OPC_BC1ANY2,

    OPC_BC1TANY2     = (0x01 << 16) | OPC_BC1ANY2,

};

enum {

    OPC_BC1FANY4     = (0x00 << 16) | OPC_BC1ANY4,

    OPC_BC1TANY4     = (0x01 << 16) | OPC_BC1ANY4,

};

#define MASK_CP2(op)       MASK_OP_MAJOR(op) | (op & (0x1F << 21))

enum {

    OPC_MFC2    = (0x00 << 21) | OPC_CP2,

    OPC_DMFC2   = (0x01 << 21) | OPC_CP2,

    OPC_CFC2    = (0x02 << 21) | OPC_CP2,

    OPC_MFHC2   = (0x03 << 21) | OPC_CP2,

    OPC_MTC2    = (0x04 << 21) | OPC_CP2,

    OPC_DMTC2   = (0x05 << 21) | OPC_CP2,

    OPC_CTC2    = (0x06 << 21) | OPC_CP2,

    OPC_MTHC2   = (0x07 << 21) | OPC_CP2,

    OPC_BC2     = (0x08 << 21) | OPC_CP2,

};

#define MASK_CP3(op)       MASK_OP_MAJOR(op) | (op & 0x3F)

enum {

    OPC_LWXC1   = 0x00 | OPC_CP3,

    OPC_LDXC1   = 0x01 | OPC_CP3,

    OPC_LUXC1   = 0x05 | OPC_CP3,

    OPC_SWXC1   = 0x08 | OPC_CP3,

    OPC_SDXC1   = 0x09 | OPC_CP3,

    OPC_SUXC1   = 0x0D | OPC_CP3,

    OPC_PREFX   = 0x0F | OPC_CP3,

    OPC_ALNV_PS = 0x1E | OPC_CP3,

    OPC_MADD_S  = 0x20 | OPC_CP3,

    OPC_MADD_D  = 0x21 | OPC_CP3,

    OPC_MADD_PS = 0x26 | OPC_CP3,

    OPC_MSUB_S  = 0x28 | OPC_CP3,

    OPC_MSUB_D  = 0x29 | OPC_CP3,

    OPC_MSUB_PS = 0x2E | OPC_CP3,

    OPC_NMADD_S = 0x30 | OPC_CP3,

    OPC_NMADD_D = 0x31 | OPC_CP3,

    OPC_NMADD_PS= 0x36 | OPC_CP3,

    OPC_NMSUB_S = 0x38 | OPC_CP3,

    OPC_NMSUB_D = 0x39 | OPC_CP3,

    OPC_NMSUB_PS= 0x3E | OPC_CP3,

};

/* global register indices */

static TCGv_ptr cpu_env;

static TCGv cpu_gpr[32], cpu_PC;

static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];

static TCGv cpu_dspctrl, btarget, bcond;

static TCGv_i32 hflags;

static TCGv_i32 fpu_fcr0, fpu_fcr31;

static uint32_t gen_opc_hflags[OPC_BUF_SIZE];

#include "gen-icount.h"

#define gen_helper_0i(name, arg) do {                             \

    TCGv_i32 helper_tmp = tcg_const_i32(arg);                     \

    gen_helper_##name(helper_tmp);                                \

    tcg_temp_free_i32(helper_tmp);                                \

    } while(0)

#define gen_helper_1i(name, arg1, arg2) do {                      \

    TCGv_i32 helper_tmp = tcg_const_i32(arg2);                    \

    gen_helper_##name(arg1, helper_tmp);                          \

    tcg_temp_free_i32(helper_tmp);                                \

    } while(0)

#define gen_helper_2i(name, arg1, arg2, arg3) do {                \

    TCGv_i32 helper_tmp = tcg_const_i32(arg3);                    \

    gen_helper_##name(arg1, arg2, helper_tmp);                    \

    tcg_temp_free_i32(helper_tmp);                                \

    } while(0)

#define gen_helper_3i(name, arg1, arg2, arg3, arg4) do {          \

    TCGv_i32 helper_tmp = tcg_const_i32(arg4);                    \

    gen_helper_##name(arg1, arg2, arg3, helper_tmp);              \

    tcg_temp_free_i32(helper_tmp);                                \

    } while(0)

typedef struct DisasContext {

    struct TranslationBlock *tb;

    target_ulong pc, saved_pc;

    uint32_t opcode;

    int singlestep_enabled;

    /* Routine used to access memory */

    int mem_idx;

    uint32_t hflags, saved_hflags;

    int bstate;

    target_ulong btarget;

} DisasContext;

enum {

    BS_NONE     = 0, /* We go out of the TB without reaching a branch or an

                      * exception condition */

    BS_STOP     = 1, /* We want to stop translation for any reason */

    BS_BRANCH   = 2, /* We reached a branch condition     */

    BS_EXCP     = 3, /* We reached an exception condition */

};

static const char *regnames[] =

    { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",

      "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",

      "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",

      "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };

static const char *regnames_HI[] =

    { "HI0", "HI1", "HI2", "HI3", };

static const char *regnames_LO[] =

    { "LO0", "LO1", "LO2", "LO3", };

static const char *regnames_ACX[] =

    { "ACX0", "ACX1", "ACX2", "ACX3", };

static const char *fregnames[] =

    { "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",

      "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",

      "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",

      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };

#ifdef MIPS_DEBUG_DISAS

#define MIPS_DEBUG(fmt, ...)                         \

        qemu_log_mask(CPU_LOG_TB_IN_ASM,                \

                       TARGET_FMT_lx ": %08x " fmt "\n", \

                       ctx->pc, ctx->opcode , ## __VA_ARGS__)

#define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)

#else

#define MIPS_DEBUG(fmt, ...) do { } while(0)

#define LOG_DISAS(...) do { } while (0)

#endif

#define MIPS_INVAL(op)                                                        \

do {                                                                          \

    MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26,            \

               ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F));             \

} while (0)

/* General purpose registers moves. */

static inline void gen_load_gpr (TCGv t, int reg)

{

    if (reg == 0)

        tcg_gen_movi_tl(t, 0);

    else

        tcg_gen_mov_tl(t, cpu_gpr[reg]);

}

static inline void gen_store_gpr (TCGv t, int reg)

{

    if (reg != 0)

        tcg_gen_mov_tl(cpu_gpr[reg], t);

}

/* Moves to/from ACX register.  */

static inline void gen_load_ACX (TCGv t, int reg)

{

    tcg_gen_mov_tl(t, cpu_ACX[reg]);

}

static inline void gen_store_ACX (TCGv t, int reg)

{

    tcg_gen_mov_tl(cpu_ACX[reg], t);

}

/* Moves to/from shadow registers. */

static inline void gen_load_srsgpr (int from, int to)

{

    TCGv t0 = tcg_temp_new();

    if (from == 0)

        tcg_gen_movi_tl(t0, 0);

    else {

        TCGv_i32 t2 = tcg_temp_new_i32();

        TCGv_ptr addr = tcg_temp_new_ptr();

        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));

        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);

        tcg_gen_andi_i32(t2, t2, 0xf);

        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);

        tcg_gen_ext_i32_ptr(addr, t2);

        tcg_gen_add_ptr(addr, cpu_env, addr);

        tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);

        tcg_temp_free_ptr(addr);

        tcg_temp_free_i32(t2);

    }

    gen_store_gpr(t0, to);

    tcg_temp_free(t0);

}

static inline void gen_store_srsgpr (int from, int to)

{

    if (to != 0) {

        TCGv t0 = tcg_temp_new();

        TCGv_i32 t2 = tcg_temp_new_i32();

        TCGv_ptr addr = tcg_temp_new_ptr();

        gen_load_gpr(t0, from);

        tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));

        tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);

        tcg_gen_andi_i32(t2, t2, 0xf);

        tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);

        tcg_gen_ext_i32_ptr(addr, t2);

        tcg_gen_add_ptr(addr, cpu_env, addr);

        tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);

        tcg_temp_free_ptr(addr);

        tcg_temp_free_i32(t2);

        tcg_temp_free(t0);

    }

}

/* Floating point register moves. */

static inline void gen_load_fpr32 (TCGv_i32 t, int reg)

{

    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));

}

static inline void gen_store_fpr32 (TCGv_i32 t, int reg)

{

    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));

}

static inline void gen_load_fpr32h (TCGv_i32 t, int reg)

{

    tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));

}

static inline void gen_store_fpr32h (TCGv_i32 t, int reg)

{

    tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));

}

static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)

{

    if (ctx->hflags & MIPS_HFLAG_F64) {

        tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));

    } else {

        TCGv_i32 t0 = tcg_temp_new_i32();

        TCGv_i32 t1 = tcg_temp_new_i32();

        gen_load_fpr32(t0, reg & ~1);

        gen_load_fpr32(t1, reg | 1);

        tcg_gen_concat_i32_i64(t, t0, t1);

        tcg_temp_free_i32(t0);

        tcg_temp_free_i32(t1);

    }

}

static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg)

{

    if (ctx->hflags & MIPS_HFLAG_F64) {

        tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));

    } else {

        TCGv_i64 t0 = tcg_temp_new_i64();

        TCGv_i32 t1 = tcg_temp_new_i32();

        tcg_gen_trunc_i64_i32(t1, t);

        gen_store_fpr32(t1, reg & ~1);

        tcg_gen_shri_i64(t0, t, 32);

        tcg_gen_trunc_i64_i32(t1, t0);

        gen_store_fpr32(t1, reg | 1);

        tcg_temp_free_i32(t1);

        tcg_temp_free_i64(t0);

    }

}

static inline int get_fp_bit (int cc)

{

    if (cc)

        return 24 + cc;

    else

        return 23;

}

/* Tests */

static inline void gen_save_pc(target_ulong pc)

{

    tcg_gen_movi_tl(cpu_PC, pc);

}

static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)

{

    LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);

    if (do_save_pc && ctx->pc != ctx->saved_pc) {

        gen_save_pc(ctx->pc);

        ctx->saved_pc = ctx->pc;

    }

    if (ctx->hflags != ctx->saved_hflags) {

        tcg_gen_movi_i32(hflags, ctx->hflags);

        ctx->saved_hflags = ctx->hflags;

        switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {

        case MIPS_HFLAG_BR:

            break;

        case MIPS_HFLAG_BC:

        case MIPS_HFLAG_BL:

        case MIPS_HFLAG_B:

            tcg_gen_movi_tl(btarget, ctx->btarget);

            break;

        }

    }

}

static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)

{

    ctx->saved_hflags = ctx->hflags;

    switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {

    case MIPS_HFLAG_BR:

        break;

    case MIPS_HFLAG_BC:

    case MIPS_HFLAG_BL:

    case MIPS_HFLAG_B:

        ctx->btarget = env->btarget;

        break;

    }

}

static inline void

generate_exception_err (DisasContext *ctx, int excp, int err)

{

    TCGv_i32 texcp = tcg_const_i32(excp);

    TCGv_i32 terr = tcg_const_i32(err);

    save_cpu_state(ctx, 1);

    gen_helper_raise_exception_err(texcp, terr);

    tcg_temp_free_i32(terr);

    tcg_temp_free_i32(texcp);

}

static inline void

generate_exception (DisasContext *ctx, int excp)

{

    save_cpu_state(ctx, 1);

    gen_helper_0i(raise_exception, excp);

}

/* Addresses computation */

static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)

{

    tcg_gen_add_tl(ret, arg0, arg1);

#if defined(TARGET_MIPS64)

    /* For compatibility with 32-bit code, data reference in user mode

       with Status_UX = 0 should be casted to 32-bit and sign extended.

       See the MIPS64 PRA manual, section 4.10. */

    if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&

        !(ctx->hflags & MIPS_HFLAG_UX)) {

        tcg_gen_ext32s_i64(ret, ret);

    }

#endif

}

static inline void check_cp0_enabled(DisasContext *ctx)

{

    if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))

        generate_exception_err(ctx, EXCP_CpU, 0);

}

static inline void check_cp1_enabled(DisasContext *ctx)

{

    if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))

        generate_exception_err(ctx, EXCP_CpU, 1);

}

/* Verify that the processor is running with COP1X instructions enabled.

   This is associated with the nabla symbol in the MIPS32 and MIPS64

   opcode tables.  */

static inline void check_cop1x(DisasContext *ctx)

{

    if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X)))

        generate_exception(ctx, EXCP_RI);

}

/* Verify that the processor is running with 64-bit floating-point

   operations enabled.  */

static inline void check_cp1_64bitmode(DisasContext *ctx)

{

    if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X)))

        generate_exception(ctx, EXCP_RI);

}

/*

 * Verify if floating point register is valid; an operation is not defined

 * if bit 0 of any register specification is set and the FR bit in the

 * Status register equals zero, since the register numbers specify an

 * even-odd pair of adjacent coprocessor general registers. When the FR bit

 * in the Status register equals one, both even and odd register numbers

 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.

 *

 * Multiple 64 bit wide registers can be checked by calling

 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);

 */

static inline void check_cp1_registers(DisasContext *ctx, int regs)

{

    if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))

        generate_exception(ctx, EXCP_RI);

}

/* This code generates a "reserved instruction" exception if the

   CPU does not support the instruction set corresponding to flags. */

static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)