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Kill off cpu_state_reset()
In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset()was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()that would operate on QOM objects.
All callers have been updated except for one in target-mips, so drop all...
target-ppc: Let cpu_ppc_init() return PowerPCCPU
Adapt e500 mpc8544ds machine accordingly.
Turn cpu_init() into a static inline function returning CPUPPCState forbackwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>
target-ppc: Some support for dumping TLB_EMB TLBs
Add mmubooke_dump_mmu().
TODO: Add printing of individual flags.
Signed-off-by: François Revol <revol@free.fr>[agraf: fix coding style]Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: QOM'ify CPU reset
Move code from cpu_state_reset() into ppc_cpu_reset().Reorder #include of helper_regs.h to use it in translate_init.c.
Adjust whitespace and add braces.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: David Gibson <david@gibson.dropbear.id.au>
target-ppc: Start QOM'ifying CPU init
Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn.
target-ppc: QOM'ify CPU
Embed CPUPPCState as first member of PowerPCCPU.Distinguish between "powerpc-cpu", "powerpc64-cpu" and"embedded-powerpc-cpu".
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-ppc: Add hooks for handling tcg and kvm limitations
On target-ppc, our table of CPU types and features encodes the features asfound on the hardware, regardless of whether these features are actuallyusable under TCG or KVM. We already have cases where the information from...
PPC: Fix TLB invalidation bug within the PPC interrupt handler.
Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLBflush bug. By applying a mask to the interrupt MSR which cleared the IR/DRbits at the start of the interrupt handler, the logic towards the end of the...
target-ppc: Drop cpu_ppc_close()
It is unused, so avoid QOM'ifying it unneededly.
Replace Qemu by QEMU in comments
The official spelling is QEMU.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Reviewed-by: Andreas Färber <afaerber@suse.de>[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: Fix large page support in TCG
Fix large page support in TCG. The old code would overwrite the large pagetable entry with the fake 4 KB one generated here whenever the ref/change bitswere updated, causing it to point to the wrong area of memory.
Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org>...
target-ppc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
target-ppc: Clean includes
Remove some include statements which are not needed.
Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Stefan Weil <sw@weilnetz.de>
ppc: remove unused variables
Fix this error:/src/qemu/target-ppc/helper.c: In function 'booke206_tlb_to_page_size':/src/qemu/target-ppc/helper.c:1296:14: error: variable 'tlbncfg' set but not used [-Werror=unused-but-set-variable]
Tested-by: Andreas Färber <afaerber@suse.de>...
PPC: Enable doorbell excp handlers
We already had all the code available to have doorbell exceptionsbe handled properly. It was just disabled.
Enable it, so we can rely on it.
Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: booke206: Check for TLB overrun
Our internal helpers to fetch TLB entries were not able to tell usthat an entry doesn't even exist. Pass an error out if we hit sucha case to not accidently pass beyond the TLB array.
PPC: booke206: move avail check to tlbwe
We can have TLBs that only support a single page size. This is definedby the absence of the AVAIL flag in TLBnCFG. If this is the case, wecurrently write invalid size info into the TLB, but override it oninternal fault....
PPC: booke206: allow NULL raddr in ppcmas_tlb_check
We might want to call the tlb check function without actually caring aboutthe real address resolution. Check if we really should write the valueback.
PPC: monitor: add ability to dump SLB entries
When run with a PPC Book3S (server) CPU Currently 'info tlb' in theqemu monitor reports "dump_mmu: unimplemented". However, duringbringup work, it can be quite handy to have the SLB entries, which areavailable in the CPUPPCState. This patch adds an implementation of...
pseries: Support SMT systems for KVM Book3S-HV
Alex Graf has already made qemu support KVM for the pseries machinewhen using the Book3S-PR KVM variant (which runs the guest inusermode, emulating supervisor operations). This code allows gets usvery close to also working with KVM Book3S-HV (using the hypervisor...
ppc: booke206: add "info tlb" support
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages
This definition is backward compatible with MAV=1.0 as long asthe guest does not set reserved bits in MAS1/MAS4.
Also, fix the shift in booke206_tlb_to_page_size -- it's the basethat should be able to hold a 4G page size, not the shift count....
Remove blanks before \n in output strings
Those blanks violate the coding conventions, seescripts/checkpatch.pl.
Blanks missing after colons in the changed lines were added.
This patch does not try to fix tabs, long lines and otherproblems in the changed lines, therefore checkpatch.pl reports...
PPC: E500: Add ESR bit definitions
The BookE spec specifies a number of ESR bits. Add defines for themso we can use them later on.
Reported-by: Jason Wessel <jason.wessel@windriver.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
PPC: E500: Set ESR values
When an exception occurs on BookE, we need to set ESR bits to exposeto the guest information on what exactly happened. Add the obvious ones.
Reported-by: Jason Wessel <jason.wessel@windriver.com>Signed-off-by: Alexander Graf <agraf@suse.de>...
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)is not used in cpu_*_handle_mmu_fault() functions, remove themand adjust callers.
Acked-by: Richard Henderson <rth@twiddle.net>...
Avoid allocating TCG resources in non-TCG mode
Do not allocate TCG-only resources like the translation buffer whenrunning over KVM or XEN. Saves a "few" bytes in the qemu address spaceand is also conceptually cleaner.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types andallocated that union. While it's a waste of memory (and cache) to allocateTLB information for a TLB type with much information when you only needlittle, it also inflicts another issue....
PPC: E500: Use MAS registers instead of internal TLB representation
The natural format for e500 cores to do TLB manipulation with are the MASregisters. Instead of converting them into some internal representationand back again when the guest reads them, we can just keep the data...
target-ppc: Handle memory-forced I/O controller access
On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07Fis special-cased as memory-forced I/O controller access. It is supposedto be checked immediately if T=1, bypassing all protection mechanisms...
Fix compilation warning due to missing header for sigaction (followup)
This patch removes all references to signal.h when qemu-common.h is includedas they become redundant.
Signed-off-by: Alexandre Raymond <cerbere@gmail.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix a bug in mtsr/mtsrin emulation on ppc64
Early ppc64 CPUs include a hack to partially simulate the ppc32 segmentregisters, by translating writes to them into writes to the SLB. This isnot used by any current Linux kernel, but it is used by the openbios used...
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
Clean up slb_lookup() function
The slb_lookup() function, used in the ppc translation path returns anumber of slb entry fields in reference parameters. However, only oneof the two callers of slb_lookup() actually wants this information.
This patch, therefore, makes slb_lookup() return a simple pointer to the...
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't(quite) get the hash value for the ppc hashed page table. Instead itgets the hash shifted - effectively the offset of the hash bucket within...
Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()has a mix of common and 32 or 64 bit specific code. However thedivision is not done terribly well which results in a lot of messy codeflipping between common and divided paths....
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used onpowerpc MMUs were 256MB in size. This was the only option on all hashpage table based 32-bit powerpc cpus, and on the earlier 64-bit hash pagetable based cpus. However, newer 64-bit cpus also permit 1TB segments...
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's farfrom perfect - it's missing a number of POWER7 features so far, includingany support for VSX or decimal floating point instructions. However, it'sclose enough to boot a kernel with the POWER7 PVR....
Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full systempartitions, the guest does not have direct access to the hardware pagetable. Instead, the pagetable exists in hypervisor memory, and the guest...
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 isstoreed in a structure with the unhelpfully named fields 'tmp'and 'tmp64'. While the layout in these fields does match thedescription of the SLB in the architecture document, it is not...
Add a hook to allow hypercalls to be emulated on PowerPC
PowerPC and POWER chips since the POWER4 and 970 have a specialhypervisor mode, and a corresponding form of the system callinstruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. That...
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translationthrough the segment lookaside buffer. Likewise it supports theslbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions...
ppc: remove video.x
Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.
Remove video.x MoL hacks.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ppc: Minor 40x MMU fixes
Signed-off-by: John Clark <clarkjc@runbox.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
powerpc: Improve emulation of the BookE MMU
Improve the emulation of the BookE MMU to be able to boot linuxon virtex5 boards.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSRvalue that is rather simple. If we leave out the HV case, it's almostalways 0.
To reflect this, let's redesign the way that MSR value gets calculated....
powerpc: Avoid TLB related log spamming
Invalid TLB entries are normal and should not spam the log.
target-ppc: remove useless line
This line was a bit clear.The next lines set or reset this bit (LE) depending of another bit (ILE).So the first line is useless.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix RFI by clearing some bits of MSR
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processorsbecause some interrupt specifics bits of SRR1 are copied to MSR.
SRR1 is a save of MSR during interrupt.During RFI, MSR must be restored from SRR1....
ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Signed-off-by: Paul Brook <paul@codesourcery.com>
PPC: Fix large pages
We were masking 1TB SLB entries on the feature bit of 16 MB pages. Obviouslythat breaks, so let's just ignore 1TB SLB entries for now and instead do16MB pages correctly.
This fixes PPC64 Linux boot with -m above 256.
Signed-off-by: Alexander Graf <agraf@suse.de>...
ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused byzone protection bits.
ppc-40x: Correct decoding of zone protection bits.
The 40x MMU has 15 zones in the ZPR register.
user: move CPU reset call to main.c for x86/PPC/Sparc
PPC: rename cpu_ppc_reset to cpu_reset for consistency
PPC: remove unneeded calls to device reset
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Replace REGX with PRIx64
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
Update to a hopefully more future proof FSF address
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Fix PPC reset
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Explain why the whole TLB is flushed on SR write
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
Disable BAT for 970
The 970 doesn't know BAT, so let's not search BATs there.This was only in as a hack for OpenHackWare so it wouldwork on PPC64.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
Keep SLB in-CPU
Real 970 CPUs have the SLB not memory backed, but inside the CPU.This breaks bridge mode for 970 for now, but at least keeps us fromoverwriting physical addresses 0x0 - 0x300, rendering our interrupthandlers useless.
I put in a stub for bridge mode operation that could be enabled...
Fix NX bit
ctx->nx only got ORed, but never reset. So when one page in thelifetime of the VM was ever NX, all later pages were too.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
Enable 64bit mode on interrupts
Real 970s enable MSR_SF on all interrupts. The current code didn't dothis until now, so let's activate it!
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
Implement large pages
The current SLB/PTE code does not support large pages, which arerequired by Linux, as it boots up with the kernel regions up as large.
This patch implements large page support, so we can run Linux.
Signed-off-by: Alexander Graf <alex@csgraf.de>...
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
Turn MMU off on reset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6637 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.
This patch doesn't try to merge logging macros from different files,but just unify the debugging code #ifdefs onto a macro on each file. Afurther cleanup can unify the debugging macros on a common header, later...
powerpc/kvm: enable POWERPC_MMU_BOOKE_FSL when kvm is enabled (Liu Yu)
Signed-off-by: Liu Yu <yu.liu@freescale.com>Acked-by: Hollis Blanchard <hollisb@us.ibm.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6329 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: Enable KVM for ppcemb.
Implement hooks called by generic KVM code.
Also add code that will copy the host's CPU and timebase frequencies to theguest, which is necessary on KVM because the guest can directly access thetimebase.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>...
target-ppc: remove remaining warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove unneeded include
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5990 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: rework exception code
... also remove two warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: enable SPE and Altivec in user mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5965 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: initialize MSR appropriately in user-mode
Mask the initial MSR with the mask from the PowerPC CPU definition.
Noticed by Nathan Froyd.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5964 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: enable access type in MMU
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5950 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SPR accesses to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SLB/TLB instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert exceptions generation to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Convert XER accesses to TCG
Define XER bits as a single register and access them individually toavoid defining 5 32-bit registers (TCG doesn't permit to map 8-bitregisters).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162