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MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of codethat figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1Xnot being set where applicable that causes floating-point MADD family...
target-mips: allow microMIPS SWP and SDP to have RD equal to BASE
The microMIPS SWP and SDP instructions do not modify GPRs. So theirbehavior is well defined when RD equals BASE. The MIPS ArchitectureVerification Programs (AVPs) check that they work as expected. This...
target-mips: add privilege level check to several Cop0 instructions
The MIPS Architecture Verification Programs (AVPs) check privilegedinstructions for the required privilege level. These changes are neededto pass the AVP suite.
Signed-off-by: Eric Johnson <ericj@mips.com>...
mips-linux-user: Always support rdhwr.
The kernel will emulate this instruction if it's not supportednatively. This insn is used for TLS, among other things, andso is required by modern glibc.
Signed-off-by: Richard Henderson <rth@twiddle.net>Cc: Riku Voipio <riku.voipio@iki.fi>...
target-mips: Streamline indexed cp1 memory addressing.
We've already eliminated both base and index being zero.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix order of CVT.PS.S operands
The FS input to CVT.PS.S is the high half and FT is the low half.tcg_gen_concat_i32_i64 takes the low half first, so the operandswere in the wrong order.
Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix operands of RECIP2.S and RECIP2.PS
Read the second input operand of RECIP2.S and RECIP2.PS from FT ratherthan FD. RECIP2.D is already correct.
target-mips: Enable access to required RDHWR hardware registers
While running in the usermode emulator all of the required*MIPS32r2 RDHWR hardware registers should be accessible (theLinux kernel enables access to these same registers). Notethat these registers are still enabled when the MIPS ISA is...
MIPS: Correct FCR0 initialization
This change addresses a problem where QEMU incorrectly traps onfloating-point MADD group instructions with SIGILL, at least whileemulating MIPS32r2 processors. These instructions use the COP1X majoropcode and include ones like:...
target-mips: Use cpu_reset() in cpu_mips_init()
Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ifyCPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping theintroduction of subclasses for 1.1, due to mips_def_t the reset code...
target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSStatefor backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>
mips: Fix BC1ANY24F instructions
There's some dodgy application of De Morgan's law in the emulationof the MIPS BC1ANY24F instructions: they end up branching onlyif all CCs are false, rather than if one CC is.
Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests....
target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.
Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Richard Henderson <rth@twiddle.net>
target-mips: Start QOM'ifying CPU init
Move code not dependent on mips_def_t from cpu_mips_init() into aQOM initfn, as a start.
target-mips: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc] sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Rename cpu_reset() to cpu_state_reset()
Frees the identifier cpu_reset for QOM CPUs (manual rename).
Don't hide the parameter type behind explicit casts, use staticfunctions with strongly typed argument to indirect.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-mips: Clean includes
Remove some include statements which are not needed.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>
mips: Initialize MT state at reset
Only TC0 on VPE0 is active after reset. All other VPEs andTCs start in sleep.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
mips: Hook in more reg accesses via mttr/mftr
Use glib memory allocation and free functions
qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-mips: fix save_cpu_state() calls
The rule is:- don't save PC if the exception is only triggered by softmmu.- save PC if the exception can be triggered by an helper.
Fix a 64-bit kernel crash when loading modules.
mips: Break TBs after mfc0_count
Break the TB after reading the count register. This makes itpossible to take timer interrupts immediately after a read ofa possibly expired timer.
target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:
int x; ... /* no initialization of x */ x = f (x);
which confused later bits of TCG rather badly, leading to crashes.
Fix the helpers to only return results (those instructions have no...
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
mips: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:/src/qemu/target-mips/translate.c: In function 'gen_ld':/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set but not used [-Werror=unused-but-set-variable]...
Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
mips: more fixes to the MIPS interrupt glue logic
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of theinterrupt logic to cpu-exec.c. Remove the remaining useless codeand fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-mips: add loongson 2E & 2F integer instructions
This patch adds support for loongson 2E & 2F instructions. They are thesame instructions, but differ by the opcode encoding.
target-mips: add Loongson support prefetch
Loongson CPU uses a load to zero register for prefetch.Emulate it as a NOP.
target-mips: split load and store
target-mips: fix DINSU instruction
target-mips: enable movn/movz on loongson 2E & 2F
target-mips: Fix compilation
TCGv t1 needs tcg_temp_free instead of tcg_temp_free_i32.
Cc: Nathan Froyd <froydnj@codesourcery.com>Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: define constants for magic numbers
Add FMT_* constants for the floating-point format field in opcodes andtweak a few places to use them. Add enums for various invocations ofFOP and tweak gen_farith and its lone caller accordingly.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-mips: move FP FMT comments closer to the definitions
target-mips: refactor c{, abs}.cond.fmt insns
Move all knowledge about coprocessor-checking and register numberinginto the gen_cmp* helper functions.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: mips16 cleanups
Change code handling mips16-specific branches to use ISA-neutral specialopcodes. Since there are several places where the delay slotrequirements for microMIPS branches differ from mips16 branches, usingopcodes is easier than checking hflags, then checking mips16...
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.
target-mips: break out [ls][wd]c1 and rdhwr insn generation
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Acked-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Remove duplicate CPU log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Fix format specifiers for fpu_fprintf
In the previous patch which introduced fprintf_function toallow parameter checking by gcc some compiler warningsremained unfixed.
These warnings are fixed here.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
target-mips: Fix one more format specifier for cpu_fprintf
env->bcond must be printed using TARGET_FMT_ld.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: use newer logical ops
target-mips: use setcond when possible
target-mips: fix ROTR and DROTR by zero
target-mips: remove useless sign extension
target-mips: fix CpU exception for coprocessor 0
When we signal a CpU exception for coprocessor 0, we should indicatethat it's for coprocessor 0 instead of coprocessor 1.
target-mips: fix user-mode emulation startup
Running programs with the MIPS user-mode emulator fails during dynamicloading, as floating-point instructions are not enabled in inenv->hflags. Move the code for doing so from fpu_init to cpu_reset sothe MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset...
target-mips: add enums for MIPS16 opcodes
target-mips: add mips16 instruction decoding
There's no good way to add this incrementally, so we do it all at once.The only changes to shared code are in handle_delay_slot. We need toflip ISAMode when doing a jump-and-exchange. We also need to setISAMode the low bit of the target address for jump-to-register....
target-mips: add copyright notice for mips16 work
Also cross off mips16 ASE in TODO.
target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
It's easier to implement mips16 shift instructions if we're notexamining the opcode inside gen_shift_{imm,}. So move ROTR and ROTRVand do the special-case handling of SRL and SRLV inside decode_opc....
target-mips: make gen_compute_branch 16/32-bit-aware
target-mips: add gen_base_offset_addr
This is a common pattern in existing code. We'll also use it toimplement the mips16 SAVE/RESTORE instructions.
target-mips: split out delay slot handling
Move delay slot handling to common code whose invocation can becontrolled from gen_intermediate_code_internal.
target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in bothuser and system mode. Use the physical address insteead in systemmode.
target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actualregister value, which is only part of this value and depends on theCPU.
target-mips: fix indentation
mips: fix cpu_reset memory leak
Remove cpu_mips_register()- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()- move the other parts in cpu_mips_init()
Reported-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
target-mips: make sure constants are in the second argument
mips: Fix spelling in comment
inofficial -> unofficial
Thanks to Blue Swirl.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: log instructions start in TCG code
target-mips: remove MAX_OP_PER_INSTR workaround
Now that MAX_OP_PER_INSTR has been increased to a safer value, removedthe target-mips specific workaround.
target-mips: fix single-stepping
Single-stepping branches on MIPS didn't work right, because thegeneration of EXCP_DEBUG happened after the generation of the code toexit the current TB. That is, given the code:
bne v0,v1,target nop ... target:...
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
target-mips: fix conditional moves off fp condition codes
Conditional moves off fp condition codes were using the result ofget_fp_bit to isolate and test the relevant condition code. However,get_fp_bit returns the bit number of the condition code, not a...
Update to a hopefully more future proof FSF address
target-mips: remove useless code in gen_st_cond()
Fix MIPS SC
Fix botched merge of op_ldst_sc calls to match actual implementation.Thanks to Aurelien Jarno for diagnosing this.
Signed-off-by: Paul Brook <paul@codesourcery.com>
MIPS atomic instructions
Implement MIPS ll/sc instructions using atomic compare+exchange.
target-mips: fix MADD and MSUB/MSUBU instructions
MADD was not correctly writing to HI.
MSUB/MSUBU are specified as `HI||LO - product', not `product - HI||LO'.
Replace gcc variadic macro extension with C99 version
target-mips: proper sign extension for 'SUBU rd, zero, rt'
target-mips: fix comments about SUB/DSUB
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
Enable access to SYNCI_Step register in usermode emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7191 c046a42c-6fe2-441c-8c8c-71466251a162
Revert "target-mips: fix call to check_*() functions"
This reverts commit r7127, r7132 is a better fix for that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7133 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: simplify exception generation
There is no need to exit the tb after a call to helper_raise_exceptionas it already calls cpu_loop_exit().
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7132 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix revision r7126
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7128 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix call to check_*() functions
check_*() functions may in fine call generate_exception(), which endsby a call to tcg_gen_exit_tb(). As a consequence, we have to make surethat no TCG temp variables are crossing a check_*() function.
target-mips: optimize gen_flt3_ldst()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7126 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: optimize gen_flt_ldst()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7125 c046a42c-6fe2-441c-8c8c-71466251a162
Stop translation after a syscall instruciton.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7124 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: mark zero register as unused.
Suggested by Stuart Brady.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7107 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: variable names consistency
Use a consistent naming of arguments and TCG variables across the wholefile, the same as in tcg/tcg-op.h:- arg1, arg2, ... for arguments- t0, t1, t2, ... for variables
target-mips: fix commits 7040 and 7042
CPU state should also be saved for helpers that in fine callcpu_unlink_tb(). Reported by Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7096 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix commit 7046
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7095 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: don't map zero register as a TCG global
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7094 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: optimize gen_ldst()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7093 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: optimize gen_arith_imm()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7092 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix commit r7076
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7078 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: optimize gen_movcf_d()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7077 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: optimize a few tcg_temp_free()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7076 c046a42c-6fe2-441c-8c8c-71466251a162